1 /* src/vm/jit/i386/codegen.h - code generation macros and definitions for i386
3 Copyright (C) 1996-2005 R. Grafl, A. Krall, C. Kruegel, C. Oates,
4 R. Obermaisser, M. Platter, M. Probst, S. Ring, E. Steiner,
5 C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich, J. Wenninger,
6 Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
25 Contact: cacao@complang.tuwien.ac.at
27 Authors: Andreas Krall
32 $Id: codegen.h 3991 2005-12-22 13:58:17Z twisti $
46 #include "vm/jit/jit.h"
49 #if defined(ENABLE_LSRA)
50 /* let LSRA allocate reserved registers (REG_ITMP[1|2|3]) */
51 # define LSRA_USES_REG_RES
54 /* some defines ***************************************************************/
56 #define PATCHER_CALL_SIZE 5 /* size in bytes of a patcher call */
59 /* additional functions and macros to generate code ***************************/
61 #define CALCOFFSETBYTES(var, reg, val) \
62 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
63 else if ((s4) (val) != 0) (var) += 1; \
64 else if ((reg) == EBP) (var) += 1;
67 #define CALCIMMEDIATEBYTES(var, val) \
68 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
72 /* gen_nullptr_check(objreg) */
74 #define gen_nullptr_check(objreg) \
76 i386_test_reg_reg(cd, (objreg), (objreg)); \
77 i386_jcc(cd, I386_CC_E, 0); \
78 codegen_addxnullrefs(cd, cd->mcodeptr); \
81 #define gen_bound_check \
83 i386_alu_membase_reg(cd, ALU_CMP, s1, OFFSET(java_arrayheader, size), s2); \
84 i386_jcc(cd, I386_CC_AE, 0); \
85 codegen_addxboundrefs(cd, cd->mcodeptr, s2); \
88 #define gen_div_check(v) \
90 if ((v)->flags & INMEMORY) { \
91 i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, src->regoff * 4); \
93 i386_test_reg_reg(cd, src->regoff, src->regoff); \
95 i386_jcc(cd, I386_CC_E, 0); \
96 codegen_addxdivrefs(cd, cd->mcodeptr); \
100 /* MCODECHECK(icnt) */
102 #define MCODECHECK(icnt) \
103 if ((cd->mcodeptr + (icnt)) > (u1 *) cd->mcodeend) \
104 cd->mcodeptr = (u1 *) codegen_increase(cd, cd->mcodeptr)
108 generates an integer-move from register a to b.
109 if a and b are the same int-register, no code will be generated.
112 #define M_INTMOVE(reg,dreg) \
113 if ((reg) != (dreg)) { \
114 i386_mov_reg_reg(cd, (reg),(dreg)); \
119 generates a floating-point-move from register a to b.
120 if a and b are the same float-register, no code will be generated
123 #define M_FLTMOVE(reg,dreg) \
125 log_text("M_FLTMOVE"); \
130 #define M_LNGMEMMOVE(reg,dreg) \
132 i386_mov_membase_reg(cd, REG_SP, (reg) * 4, REG_ITMP1); \
133 i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, (dreg) * 4); \
134 i386_mov_membase_reg(cd, REG_SP, (reg) * 4 + 4, REG_ITMP1); \
135 i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, (dreg) * 4 + 4); \
140 this function generates code to fetch data from a pseudo-register
141 into a real register.
142 If the pseudo-register has actually been assigned to a real
143 register, no code will be emitted, since following operations
144 can use this register directly.
146 v: pseudoregister to be fetched from
147 tempregnum: temporary register to be used if v is actually spilled to ram
149 return: the register number, where the operand can be found after
150 fetching (this wil be either tempregnum or the register
151 number allready given to v)
154 #define var_to_reg_int(regnr,v,tempnr) \
155 if ((v)->flags & INMEMORY) { \
157 i386_mov_membase_reg(cd, REG_SP, (v)->regoff * 4, tempnr); \
160 regnr = (v)->regoff; \
165 #define var_to_reg_flt(regnr,v,tempnr) \
166 if ((v)->type == TYPE_FLT) { \
167 if ((v)->flags & INMEMORY) { \
169 i386_flds_membase(cd, REG_SP, (v)->regoff * 4); \
173 i386_fld_reg(cd, (v)->regoff + fpu_st_offset); \
175 regnr = (v)->regoff; \
178 if ((v)->flags & INMEMORY) { \
180 i386_fldl_membase(cd, REG_SP, (v)->regoff * 4); \
184 i386_fld_reg(cd, (v)->regoff + fpu_st_offset); \
186 regnr = (v)->regoff; \
190 #define NEW_var_to_reg_flt(regnr,v,tempnr) \
191 if ((v)->type == TYPE_FLT) { \
192 if ((v)->flags & INMEMORY) { \
194 i386_flds_membase(cd, REG_SP, (v)->regoff * 4); \
198 regnr = (v)->regoff; \
201 if ((v)->flags & INMEMORY) { \
203 i386_fldl_membase(cd, REG_SP, (v)->regoff * 4); \
207 regnr = (v)->regoff; \
212 /* store_reg_to_var_xxx:
213 This function generates the code to store the result of an operation
214 back into a spilled pseudo-variable.
215 If the pseudo-variable has not been spilled in the first place, this
216 function will generate nothing.
218 v ............ Pseudovariable
219 tempregnum ... Number of the temporary registers as returned by
223 #define store_reg_to_var_int(sptr, tempregnum) \
224 if ((sptr)->flags & INMEMORY) { \
226 i386_mov_reg_membase(cd, tempregnum, REG_SP, (sptr)->regoff * 4); \
230 #define store_reg_to_var_flt(sptr, tempregnum) \
231 if ((sptr)->type == TYPE_FLT) { \
232 if ((sptr)->flags & INMEMORY) { \
234 i386_fstps_membase(cd, REG_SP, (sptr)->regoff * 4); \
237 /* i386_fxch_reg((sptr)->regoff);*/ \
238 i386_fstp_reg(cd, (sptr)->regoff + fpu_st_offset); \
242 if ((sptr)->flags & INMEMORY) { \
244 i386_fstpl_membase(cd, REG_SP, (sptr)->regoff * 4); \
247 /* i386_fxch_reg((sptr)->regoff);*/ \
248 i386_fstp_reg(cd, (sptr)->regoff + fpu_st_offset); \
254 #define M_COPY(from,to) \
255 d = reg_of_var(rd, to, REG_ITMP1); \
256 if ((from->regoff != to->regoff) || \
257 ((from->flags ^ to->flags) & INMEMORY)) { \
258 if (IS_FLT_DBL_TYPE(from->type)) { \
259 var_to_reg_flt(s1, from, d); \
260 /*M_FLTMOVE(s1, d);*/ \
261 store_reg_to_var_flt(to, d); \
263 if (!IS_2_WORD_TYPE(from->type)) { \
264 if (to->flags & INMEMORY) { \
265 if (from->flags & INMEMORY) { \
266 i386_mov_membase_reg(cd, REG_SP, from->regoff * 4, REG_ITMP1); \
267 i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, to->regoff * 4); \
269 i386_mov_reg_membase(cd, from->regoff, REG_SP, to->regoff * 4); \
272 if (from->flags & INMEMORY) { \
273 i386_mov_membase_reg(cd, REG_SP, from->regoff * 4, to->regoff); \
275 i386_mov_reg_reg(cd, from->regoff, to->regoff); \
279 M_LNGMEMMOVE(from->regoff, to->regoff); \
284 /* macros to create code ******************************************************/
299 /* opcodes for alu instructions */
327 I386_CC_B = 2, I386_CC_C = 2, I386_CC_NAE = 2,
328 I386_CC_BE = 6, I386_CC_NA = 6,
329 I386_CC_AE = 3, I386_CC_NB = 3, I386_CC_NC = 3,
330 I386_CC_E = 4, I386_CC_Z = 4,
331 I386_CC_NE = 5, I386_CC_NZ = 5,
332 I386_CC_A = 7, I386_CC_NBE = 7,
333 I386_CC_S = 8, I386_CC_LZ = 8,
334 I386_CC_NS = 9, I386_CC_GEZ = 9,
335 I386_CC_P = 0x0a, I386_CC_PE = 0x0a,
336 I386_CC_NP = 0x0b, I386_CC_PO = 0x0b,
337 I386_CC_L = 0x0c, I386_CC_NGE = 0x0c,
338 I386_CC_GE = 0x0d, I386_CC_NL = 0x0d,
339 I386_CC_LE = 0x0e, I386_CC_NG = 0x0e,
340 I386_CC_G = 0x0f, I386_CC_NLE = 0x0f,
345 /* modrm and stuff */
347 #define i386_address_byte(mod,reg,rm) \
348 *(cd->mcodeptr++) = ((((mod) & 0x03) << 6) | (((reg) & 0x07) << 3) | (((rm) & 0x07)));
351 #define i386_emit_reg(reg,rm) \
352 i386_address_byte(3,(reg),(rm));
355 #define i386_is_imm8(imm) \
356 (((int)(imm) >= -128 && (int)(imm) <= 127))
359 #define i386_emit_imm8(imm) \
360 *(cd->mcodeptr++) = (u1) ((imm) & 0xff);
363 #define i386_emit_imm16(imm) \
366 imb.i = (int) (imm); \
367 *(cd->mcodeptr++) = imb.b[0]; \
368 *(cd->mcodeptr++) = imb.b[1]; \
372 #define i386_emit_imm32(imm) \
375 imb.i = (int) (imm); \
376 *(cd->mcodeptr++) = imb.b[0]; \
377 *(cd->mcodeptr++) = imb.b[1]; \
378 *(cd->mcodeptr++) = imb.b[2]; \
379 *(cd->mcodeptr++) = imb.b[3]; \
383 #define i386_emit_mem(r,mem) \
385 i386_address_byte(0,(r),5); \
386 i386_emit_imm32((mem)); \
390 #define i386_emit_membase(basereg,disp,dreg) \
392 if ((basereg) == ESP) { \
394 i386_address_byte(0, (dreg), ESP); \
395 i386_address_byte(0, ESP, ESP); \
396 } else if (i386_is_imm8((disp))) { \
397 i386_address_byte(1, (dreg), ESP); \
398 i386_address_byte(0, ESP, ESP); \
399 i386_emit_imm8((disp)); \
401 i386_address_byte(2, (dreg), ESP); \
402 i386_address_byte(0, ESP, ESP); \
403 i386_emit_imm32((disp)); \
408 if ((disp) == 0 && (basereg) != EBP) { \
409 i386_address_byte(0, (dreg), (basereg)); \
413 if (i386_is_imm8((disp))) { \
414 i386_address_byte(1, (dreg), (basereg)); \
415 i386_emit_imm8((disp)); \
417 i386_address_byte(2, (dreg), (basereg)); \
418 i386_emit_imm32((disp)); \
423 #define i386_emit_membase32(basereg,disp,dreg) \
425 if ((basereg) == ESP) { \
426 i386_address_byte(2, (dreg), ESP); \
427 i386_address_byte(0, ESP, ESP); \
428 i386_emit_imm32((disp)); \
430 i386_address_byte(2, (dreg), (basereg)); \
431 i386_emit_imm32((disp)); \
436 #define i386_emit_memindex(reg,disp,basereg,indexreg,scale) \
438 if ((basereg) == -1) { \
439 i386_address_byte(0, (reg), 4); \
440 i386_address_byte((scale), (indexreg), 5); \
441 i386_emit_imm32((disp)); \
443 } else if ((disp) == 0 && (basereg) != EBP) { \
444 i386_address_byte(0, (reg), 4); \
445 i386_address_byte((scale), (indexreg), (basereg)); \
447 } else if (i386_is_imm8((disp))) { \
448 i386_address_byte(1, (reg), 4); \
449 i386_address_byte((scale), (indexreg), (basereg)); \
450 i386_emit_imm8 ((disp)); \
453 i386_address_byte(2, (reg), 4); \
454 i386_address_byte((scale), (indexreg), (basereg)); \
455 i386_emit_imm32((disp)); \
460 /* macros to create code ******************************************************/
462 #define M_ILD(a,b,disp) i386_mov_membase_reg(cd, (b), (disp), (a))
463 #define M_ALD(a,b,disp) M_ILD(a,b,disp)
465 #define M_IST(a,b,disp) i386_mov_reg_membase(cd, (a), (b), (disp))
466 #define M_IST_IMM(a,b,disp) i386_mov_imm_membase(cd, (a), (b), (disp))
467 #define M_AST(a,b,disp) M_IST(a,b,disp)
468 #define M_AST_IMM(a,b,disp) M_IST_IMM(a,b,disp)
470 #define M_IADD_IMM(a,b) i386_alu_imm_reg(cd, ALU_ADD, (a), (b))
471 #define M_IADD_IMM32(a,b) i386_alu_imm32_reg(cd, ALU_ADD, (a), (b))
472 #define M_ISUB_IMM(a,b) i386_alu_imm_reg(cd, ALU_SUB, (a), (b))
474 #define M_AADD_IMM(a,b) M_IADD_IMM(a,b)
475 #define M_AADD_IMM32(a,b) M_IADD_IMM32(a,b)
476 #define M_ASUB_IMM(a,b) M_ISUB_IMM(a,b)
478 #define M_OR_MEMBASE(a,b,c) i386_alu_membase_reg(cd, ALU_OR, (a), (b), (c))
479 #define M_XOR(a,b) i386_alu_reg_reg(cd, ALU_XOR, (a), (b))
480 #define M_CLR(a) M_XOR(a,a)
482 #define M_PUSH(a) i386_push_reg(cd, (a))
483 #define M_PUSH_IMM(a) i386_push_imm(cd, (a))
484 #define M_POP(a) i386_pop_reg(cd, (a))
486 #define M_MOV(a,b) i386_mov_reg_reg(cd, (a), (b))
487 #define M_MOV_IMM(a,b) i386_mov_imm_reg(cd, (a), (b))
489 #define M_TEST(a) i386_test_reg_reg(cd, (a), (a))
491 #define M_CALL(a) i386_call_reg(cd, (a))
492 #define M_CALL_IMM(a) i386_call_imm(cd, (a))
493 #define M_RET i386_ret(cd)
495 #define M_BEQ(a) i386_jcc(cd, I386_CC_E, (a))
496 #define M_BNE(a) i386_jcc(cd, I386_CC_NE, (a))
498 #define M_JMP(a) i386_jmp_reg(cd, (a))
499 #define M_JMP_IMM(a) i386_jmp_imm(cd, (a))
501 #define M_NOP i386_nop(cd)
504 /* function gen_resolvebranch **************************************************
506 backpatches a branch instruction
508 parameters: ip ... pointer to instruction after branch (void*)
509 so ... offset of instruction after branch (s4)
510 to ... offset of branch target (s4)
512 *******************************************************************************/
514 #define gen_resolvebranch(ip,so,to) \
515 *((void **) ((ip) - 4)) = (void **) ((to) - (so));
518 /* function prototypes */
520 void thread_restartcriticalsection(ucontext_t *);
522 #endif /* _CODEGEN_H */
526 * These are local overrides for various environment variables in Emacs.
527 * Please do not remove this and leave it at the end of the file, where
528 * Emacs will automagically detect them.
529 * ---------------------------------------------------------------------
532 * indent-tabs-mode: t