1 /* src/vm/jit/i386/codegen.h - code generation macros and definitions for i386
3 Copyright (C) 1996-2005, 2006 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 Contact: cacao@cacaojvm.org
27 Authors: Andreas Krall
32 $Id: codegen.h 5632 2006-10-02 13:43:15Z edwin $
43 #include "vm/jit/jit.h"
46 #if defined(ENABLE_LSRA)
47 /* let LSRA allocate reserved registers (REG_ITMP[1|2|3]) */
48 # define LSRA_USES_REG_RES
51 /* some defines ***************************************************************/
53 #define PATCHER_CALL_SIZE 5 /* size in bytes of a patcher call */
56 /* additional functions and macros to generate code ***************************/
58 #define CALCOFFSETBYTES(var, reg, val) \
59 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
60 else if ((s4) (val) != 0) (var) += 1; \
61 else if ((reg) == EBP) (var) += 1;
64 #define CALCIMMEDIATEBYTES(var, val) \
65 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
69 #define ALIGNCODENOP \
71 for (s1 = 0; s1 < (s4) (((ptrint) cd->mcodeptr) & 7); s1++) \
76 /* gen_nullptr_check(objreg) */
78 #define gen_nullptr_check(objreg) \
82 codegen_add_nullpointerexception_ref(cd); \
85 #define gen_bound_check \
87 M_ILD(REG_ITMP3, s1, OFFSET(java_arrayheader, size)); \
88 M_CMP(REG_ITMP3, s2); \
90 codegen_add_arrayindexoutofboundsexception_ref(cd, s2); \
94 /* MCODECHECK(icnt) */
96 #define MCODECHECK(icnt) \
98 if ((cd->mcodeptr + (icnt)) > (u1 *) cd->mcodeend) \
99 codegen_increase(cd); \
104 generates an integer-move from register a to b.
105 if a and b are the same int-register, no code will be generated.
108 #define M_INTMOVE(a,b) \
114 #define M_LNGMOVE(a,b) \
116 if (GET_HIGH_REG(a) == GET_LOW_REG(b)) { \
117 assert((GET_LOW_REG(a) != GET_HIGH_REG(b))); \
118 M_INTMOVE(GET_HIGH_REG(a), GET_HIGH_REG(b)); \
119 M_INTMOVE(GET_LOW_REG(a), GET_LOW_REG(b)); \
121 M_INTMOVE(GET_LOW_REG(a), GET_LOW_REG(b)); \
122 M_INTMOVE(GET_HIGH_REG(a), GET_HIGH_REG(b)); \
128 generates a floating-point-move from register a to b.
129 if a and b are the same float-register, no code will be generated
132 #define M_FLTMOVE(reg,dreg) \
134 if ((reg) != (dreg)) { \
135 log_text("M_FLTMOVE"); \
141 #define ICONST(d,c) \
150 #define LCONST(d,c) \
153 M_CLR(GET_LOW_REG(d)); \
154 M_CLR(GET_HIGH_REG(d)); \
156 M_MOV_IMM((c), GET_LOW_REG(d)); \
157 M_MOV_IMM((c) >> 32, GET_HIGH_REG(d)); \
162 /* macros to create code ******************************************************/
164 #define M_ILD(a,b,disp) emit_mov_membase_reg(cd, (b), (disp), (a))
165 #define M_ILD32(a,b,disp) emit_mov_membase32_reg(cd, (b), (disp), (a))
167 #define M_ALD(a,b,disp) M_ILD(a,b,disp)
168 #define M_ALD32(a,b,disp) M_ILD32(a,b,disp)
170 #define M_LLD(a,b,disp) \
172 M_ILD(GET_LOW_REG(a),b,disp); \
173 M_ILD(GET_HIGH_REG(a),b,disp + 4); \
176 #define M_LLD32(a,b,disp) \
178 M_ILD32(GET_LOW_REG(a),b,disp); \
179 M_ILD32(GET_HIGH_REG(a),b,disp + 4); \
182 #define M_IST(a,b,disp) emit_mov_reg_membase(cd, (a), (b), (disp))
183 #define M_IST_IMM(a,b,disp) emit_mov_imm_membase(cd, (u4) (a), (b), (disp))
184 #define M_AST(a,b,disp) M_IST(a,b,disp)
185 #define M_AST_IMM(a,b,disp) M_IST_IMM(a,b,disp)
187 #define M_IST32(a,b,disp) emit_mov_reg_membase32(cd, (a), (b), (disp))
188 #define M_IST32_IMM(a,b,disp) emit_mov_imm_membase32(cd, (u4) (a), (b), (disp))
190 #define M_LST(a,b,disp) \
192 M_IST(GET_LOW_REG(a),b,disp); \
193 M_IST(GET_HIGH_REG(a),b,disp + 4); \
196 #define M_LST32(a,b,disp) \
198 M_IST32(GET_LOW_REG(a),b,disp); \
199 M_IST32(GET_HIGH_REG(a),b,disp + 4); \
202 #define M_LST_IMM(a,b,disp) \
204 M_IST_IMM(a,b,disp); \
205 M_IST_IMM(a >> 32,b,disp + 4); \
208 #define M_LST32_IMM(a,b,disp) \
210 M_IST32_IMM(a,b,disp); \
211 M_IST32_IMM(a >> 32,b,disp + 4); \
214 #define M_IADD(a,b) emit_alu_reg_reg(cd, ALU_ADD, (a), (b))
215 #define M_ISUB(a,b) emit_alu_reg_reg(cd, ALU_SUB, (a), (b))
216 #define M_IMUL(a,b) emit_imul_reg_reg(cd, (a), (b))
217 #define M_IDIV(a) emit_idiv_reg(cd, (a))
219 #define M_MUL(a) emit_mul_reg(cd, (a))
221 #define M_IADD_IMM(a,b) emit_alu_imm_reg(cd, ALU_ADD, (a), (b))
222 #define M_ISUB_IMM(a,b) emit_alu_imm_reg(cd, ALU_SUB, (a), (b))
223 #define M_IMUL_IMM(a,b,c) emit_imul_imm_reg_reg(cd, (b), (a), (c))
225 #define M_IADD_IMM32(a,b) emit_alu_imm32_reg(cd, ALU_ADD, (a), (b))
226 #define M_ISUB_IMM32(a,b) emit_alu_imm32_reg(cd, ALU_SUB, (a), (b))
228 #define M_IADD_IMM_MEMBASE(a,b,c) emit_alu_imm_membase(cd, ALU_ADD, (a), (b), (c))
230 #define M_IADDC(a,b) emit_alu_reg_reg(cd, ALU_ADC, (a), (b))
231 #define M_ISUBB(a,b) emit_alu_reg_reg(cd, ALU_SBB, (a), (b))
233 #define M_IADDC_IMM(a,b) emit_alu_imm_reg(cd, ALU_ADC, (a), (b))
234 #define M_ISUBB_IMM(a,b) emit_alu_imm_reg(cd, ALU_SBB, (a), (b))
236 #define M_AADD_IMM(a,b) M_IADD_IMM(a,b)
237 #define M_AADD_IMM32(a,b) M_IADD_IMM32(a,b)
238 #define M_ASUB_IMM(a,b) M_ISUB_IMM(a,b)
240 #define M_NEG(a) emit_neg_reg(cd, (a))
242 #define M_AND(a,b) emit_alu_reg_reg(cd, ALU_AND, (a), (b))
243 #define M_OR(a,b) emit_alu_reg_reg(cd, ALU_OR, (a), (b))
244 #define M_XOR(a,b) emit_alu_reg_reg(cd, ALU_XOR, (a), (b))
246 #define M_AND_IMM(a,b) emit_alu_imm_reg(cd, ALU_AND, (a), (b))
247 #define M_OR_IMM(a,b) emit_alu_imm_reg(cd, ALU_OR, (a), (b))
248 #define M_XOR_IMM(a,b) emit_alu_imm_reg(cd, ALU_XOR, (a), (b))
250 #define M_AND_IMM32(a,b) emit_alu_imm32_reg(cd, ALU_AND, (a), (b))
252 #define M_CLR(a) M_XOR(a,a)
254 #define M_PUSH(a) emit_push_reg(cd, (a))
255 #define M_PUSH_IMM(a) emit_push_imm(cd, (s4) (a))
256 #define M_POP(a) emit_pop_reg(cd, (a))
258 #define M_MOV(a,b) emit_mov_reg_reg(cd, (a), (b))
259 #define M_MOV_IMM(a,b) emit_mov_imm_reg(cd, (u4) (a), (b))
261 #define M_TEST(a) emit_test_reg_reg(cd, (a), (a))
262 #define M_TEST_IMM(a,b) emit_test_imm_reg(cd, (a), (b))
264 #define M_CMP(a,b) emit_alu_reg_reg(cd, ALU_CMP, (a), (b))
265 #define M_CMP_MEMBASE(a,b,c) emit_alu_membase_reg(cd, ALU_CMP, (a), (b), (c))
267 #define M_CMP_IMM(a,b) emit_alu_imm_reg(cd, ALU_CMP, (a), (b))
268 #define M_CMP_IMM_MEMBASE(a,b,c) emit_alu_imm_membase(cd, ALU_CMP, (a), (b), (c))
270 #define M_CMP_IMM32(a,b) emit_alu_imm32_reg(cd, ALU_CMP, (a), (b))
272 #define M_BSEXT(a,b) /* XXX does not work, because of nibbles */
273 #define M_SSEXT(a,b) emit_movswl_reg_reg(cd, (a), (b))
275 #define M_CZEXT(a,b) emit_movzwl_reg_reg(cd, (a), (b))
277 #define M_CLTD emit_cltd(cd)
279 #define M_SLL(a) emit_shift_reg(cd, SHIFT_SHL, (a))
280 #define M_SRA(a) emit_shift_reg(cd, SHIFT_SAR, (a))
281 #define M_SRL(a) emit_shift_reg(cd, SHIFT_SHR, (a))
283 #define M_SLL_IMM(a,b) emit_shift_imm_reg(cd, SHIFT_SHL, (a), (b))
284 #define M_SRA_IMM(a,b) emit_shift_imm_reg(cd, SHIFT_SAR, (a), (b))
285 #define M_SRL_IMM(a,b) emit_shift_imm_reg(cd, SHIFT_SHR, (a), (b))
287 #define M_SLLD(a,b) emit_shld_reg_reg(cd, (a), (b))
288 #define M_SRLD(a,b) emit_shrd_reg_reg(cd, (a), (b))
290 #define M_SLLD_IMM(a,b,c) emit_shld_imm_reg_reg(cd, (a), (b), (c))
291 #define M_SRLD_IMM(a,b,c) emit_shrd_imm_reg_reg(cd, (a), (b), (c))
293 #define M_CALL(a) emit_call_reg(cd, (a))
294 #define M_CALL_IMM(a) emit_call_imm(cd, (a))
295 #define M_RET emit_ret(cd)
297 #define M_BEQ(a) emit_jcc(cd, CC_E, (a))
298 #define M_BNE(a) emit_jcc(cd, CC_NE, (a))
299 #define M_BLT(a) emit_jcc(cd, CC_L, (a))
300 #define M_BLE(a) emit_jcc(cd, CC_LE, (a))
301 #define M_BGE(a) emit_jcc(cd, CC_GE, (a))
302 #define M_BGT(a) emit_jcc(cd, CC_G, (a))
304 #define M_BB(a) emit_jcc(cd, CC_B, (a))
305 #define M_BBE(a) emit_jcc(cd, CC_BE, (a))
306 #define M_BAE(a) emit_jcc(cd, CC_AE, (a))
307 #define M_BA(a) emit_jcc(cd, CC_A, (a))
308 #define M_BNS(a) emit_jcc(cd, CC_NS, (a))
310 #define M_JMP(a) emit_jmp_reg(cd, (a))
311 #define M_JMP_IMM(a) emit_jmp_imm(cd, (a))
313 #define M_NOP emit_nop(cd)
316 #define M_FLD(a,b,disp) emit_flds_membase(cd, (b), (disp))
317 #define M_DLD(a,b,disp) emit_fldl_membase(cd, (b), (disp))
319 #define M_FLD32(a,b,disp) emit_flds_membase32(cd, (b), (disp))
320 #define M_DLD32(a,b,disp) emit_fldl_membase32(cd, (b), (disp))
322 #define M_FST(a,b,disp) emit_fstps_membase(cd, (b), (disp))
323 #define M_DST(a,b,disp) emit_fstpl_membase(cd, (b), (disp))
325 #define M_FSTNP(a,b,disp) emit_fsts_membase(cd, (b), (disp))
326 #define M_DSTNP(a,b,disp) emit_fstl_membase(cd, (b), (disp))
329 /* function gen_resolvebranch **************************************************
331 backpatches a branch instruction
333 parameters: ip ... pointer to instruction after branch (void*)
334 so ... offset of instruction after branch (s4)
335 to ... offset of branch target (s4)
337 *******************************************************************************/
339 #define gen_resolvebranch(ip,so,to) \
340 *((void **) ((ip) - 4)) = (void **) ((to) - (so));
343 #endif /* _CODEGEN_H */
347 * These are local overrides for various environment variables in Emacs.
348 * Please do not remove this and leave it at the end of the file, where
349 * Emacs will automagically detect them.
350 * ---------------------------------------------------------------------
353 * indent-tabs-mode: t