src/vm/jit/alpha/codegen.c

   1 /* src/vm/jit/alpha/codegen.c - machine code generator for Alpha
   2
   3    Copyright (C) 1996-2005 R. Grafl, A. Krall, C. Kruegel, C. Oates,
   4    R. Obermaisser, M. Platter, M. Probst, S. Ring, E. Steiner,
   5    C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich, J. Wenninger,
   6    Institut f. Computersprachen - TU Wien
   7
   8    This file is part of CACAO.
   9
  10    This program is free software; you can redistribute it and/or
  11    modify it under the terms of the GNU General Public License as
  12    published by the Free Software Foundation; either version 2, or (at
  13    your option) any later version.
  14
  15    This program is distributed in the hope that it will be useful, but
  16    WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18    General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program; if not, write to the Free Software
  22    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
  23    02111-1307, USA.
  24
  25    Contact: cacao@complang.tuwien.ac.at
  26
  27    Authors: Andreas Krall
  28             Reinhard Grafl
  29
  30    Changes: Joseph Wenninger
  31             Christian Thalinger
  32
  33    $Id: codegen.c 2496 2005-05-23 08:06:06Z twisti $
  34
  35 */
  36
  37
  38 #include <stdio.h>
  39 #include <signal.h>
  40
  41 #include "config.h"
  42 #include "cacao/cacao.h"
  43 #include "native/native.h"
  44 #include "vm/builtin.h"
  45 #include "vm/global.h"
  46 #include "vm/loader.h"
  47 #include "vm/stringlocal.h"
  48 #include "vm/tables.h"
  49 #include "vm/jit/asmpart.h"
  50 #include "vm/jit/jit.h"
  51 #ifdef LSRA
  52 #include "vm/jit/lsra.h"
  53 #endif
  54 #include "vm/jit/parse.h"
  55 #include "vm/jit/patcher.h"
  56 #include "vm/jit/reg.h"
  57 #include "vm/jit/alpha/arch.h"
  58 #include "vm/jit/alpha/codegen.h"
  59 #include "vm/jit/alpha/types.h"
  60 #include "vm/jit/alpha/asmoffsets.h"
  61
  62
  63 /* *****************************************************************************
  64
  65 Datatypes and Register Allocations:
  66 -----------------------------------
  67
  68 On 64-bit-machines (like the Alpha) all operands are stored in the
  69 registers in a 64-bit form, even when the correspondig JavaVM  operands
  70 only need 32 bits. This is done by a canonical representation:
  71
  72 32-bit integers are allways stored as sign-extended 64-bit values (this
  73 approach is directly supported by the Alpha architecture and is very easy
  74 to implement).
  75
  76 32-bit-floats are stored in a 64-bit doubleprecision register by simply
  77 expanding the exponent and mantissa with zeroes. (also supported by the
  78 architecture)
  79
  80
  81 Stackframes:
  82
  83 The calling conventions and the layout of the stack is  explained in detail
  84 in the documention file: calling.doc
  85
  86 *******************************************************************************/
  87
  88
  89 /* register descripton - array ************************************************/
  90
  91 /* #define REG_RES   0         reserved register for OS or code generator     */
  92 /* #define REG_RET   1         return value register                          */
  93 /* #define REG_EXC   2         exception value register (only old jit)        */
  94 /* #define REG_SAV   3         (callee) saved register                        */
  95 /* #define REG_TMP   4         scratch temporary register (caller saved)      */
  96 /* #define REG_ARG   5         argument register (caller saved)               */
  97
  98 /* #define REG_END   -1        last entry in tables */
  99
 100 int nregdescint[] = {
 101         REG_RET, REG_TMP, REG_TMP, REG_TMP, REG_TMP, REG_TMP, REG_TMP, REG_TMP,
 102         REG_TMP, REG_SAV, REG_SAV, REG_SAV, REG_SAV, REG_SAV, REG_SAV, REG_SAV,
 103         REG_ARG, REG_ARG, REG_ARG, REG_ARG, REG_ARG, REG_ARG, REG_TMP, REG_TMP,
 104         REG_TMP, REG_RES, REG_RES, REG_RES, REG_RES, REG_RES, REG_RES, REG_RES,
 105         REG_END };
 106
 107 /* for use of reserved registers, see comment above */
 108
 109 int nregdescfloat[] = {
 110         REG_RET, REG_TMP, REG_SAV, REG_SAV, REG_SAV, REG_SAV, REG_SAV, REG_SAV,
 111         REG_SAV, REG_SAV, REG_TMP, REG_TMP, REG_TMP, REG_TMP, REG_TMP, REG_TMP,
 112         REG_ARG, REG_ARG, REG_ARG, REG_ARG, REG_ARG, REG_ARG, REG_TMP, REG_TMP,
 113         REG_TMP, REG_TMP, REG_TMP, REG_TMP, REG_RES, REG_RES, REG_RES, REG_RES,
 114         REG_END };
 115
 116
 117 /* Include independent code generation stuff -- include after register        */
 118 /* descriptions to avoid extern definitions.                                  */
 119
 120 #include "vm/jit/codegen.inc"
 121 #include "vm/jit/reg.inc"
 122 #ifdef LSRA
 123 #include "vm/jit/lsra.inc"
 124 #endif
 125
 126
 127 /* NullPointerException handlers and exception handling initialisation        */
 128
 129 typedef struct sigctx_struct {
 130         long          sc_onstack;           /* sigstack state to restore          */
 131         long          sc_mask;              /* signal mask to restore             */
 132         long          sc_pc;                /* pc at time of signal               */
 133         long          sc_ps;                /* psl to retore                      */
 134         long          sc_regs[32];          /* processor regs 0 to 31             */
 135         long          sc_ownedfp;           /* fp has been used                   */
 136         long          sc_fpregs[32];        /* fp regs 0 to 31                    */
 137         unsigned long sc_fpcr;              /* floating point control register    */
 138         unsigned long sc_fp_control;        /* software fpcr                      */
 139                                             /* rest is unused                     */
 140         unsigned long sc_reserved1, sc_reserved2;
 141         unsigned long sc_ssize;
 142         char          *sc_sbase;
 143         unsigned long sc_traparg_a0;
 144         unsigned long sc_traparg_a1;
 145         unsigned long sc_traparg_a2;
 146         unsigned long sc_fp_trap_pc;
 147         unsigned long sc_fp_trigger_sum;
 148         unsigned long sc_fp_trigger_inst;
 149         unsigned long sc_retcode[2];
 150 } sigctx_struct;
 151
 152
 153 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
 154 void thread_restartcriticalsection(ucontext_t *uc)
 155 {
 156         void *critical;
 157         if ((critical = thread_checkcritical((void*) uc->uc_mcontext.sc_pc)) != NULL)
 158                 uc->uc_mcontext.sc_pc = (u8) critical;
 159 }
 160 #endif
 161
 162
 163 /* NullPointerException signal handler for hardware null pointer check */
 164
 165 void catch_NullPointerException(int sig, siginfo_t *siginfo, void *_p)
 166 {
 167         struct sigaction act;
 168         sigset_t         nsig;
 169         int              instr;
 170         long             faultaddr;
 171
 172         ucontext_t *_uc = (ucontext_t *) _p;
 173         mcontext_t *sigctx = &_uc->uc_mcontext;
 174
 175         instr = *((s4 *) (sigctx->sc_pc));
 176         faultaddr = sigctx->sc_regs[(instr >> 16) & 0x1f];
 177
 178         if (faultaddr == 0) {
 179                 /* Reset signal handler - necessary for SysV, does no harm for BSD */
 180                 act.sa_sigaction = catch_NullPointerException;
 181                 act.sa_flags = SA_SIGINFO;
 182                 sigaction(sig, &act, NULL);
 183
 184                 sigemptyset(&nsig);
 185                 sigaddset(&nsig, sig);
 186                 sigprocmask(SIG_UNBLOCK, &nsig, NULL);           /* unblock signal    */
 187
 188                 sigctx->sc_regs[REG_ITMP1_XPTR] = (u8) string_java_lang_NullPointerException;
 189                 sigctx->sc_regs[REG_ITMP2_XPC] = sigctx->sc_pc;
 190                 sigctx->sc_pc = (u8) asm_throw_and_handle_exception;
 191                 return;
 192
 193         } else {
 194                 faultaddr += (long) ((instr << 16) >> 16);
 195
 196                 throw_cacao_exception_exit(string_java_lang_InternalError,
 197                                                                    "faulting address: 0x%016lx\n", faultaddr);
 198         }
 199 }
 200
 201
 202 #ifdef __osf__
 203
 204 void init_exceptions(void)
 205 {
 206
 207 #else /* Linux */
 208
 209 /* Linux on Digital Alpha needs an initialisation of the ieee floating point
 210         control for IEEE compliant arithmetic (option -mieee of GCC). Under
 211         Digital Unix this is done automatically.
 212 */
 213
 214 #include <asm/fpu.h>
 215
 216 extern unsigned long ieee_get_fp_control();
 217 extern void ieee_set_fp_control(unsigned long fp_control);
 218
 219 void init_exceptions(void)
 220 {
 221         struct sigaction act;
 222
 223         /* initialize floating point control */
 224
 225         ieee_set_fp_control(ieee_get_fp_control()
 226                                                 & ~IEEE_TRAP_ENABLE_INV
 227                                                 & ~IEEE_TRAP_ENABLE_DZE
 228 /*                                              & ~IEEE_TRAP_ENABLE_UNF   we dont want underflow */
 229                                                 & ~IEEE_TRAP_ENABLE_OVF);
 230 #endif
 231
 232         /* install signal handlers we need to convert to exceptions */
 233
 234         if (!checknull) {
 235                 act.sa_sigaction = catch_NullPointerException;
 236                 act.sa_flags = SA_SIGINFO;
 237
 238 #if defined(SIGSEGV)
 239                 sigaction(SIGSEGV, &act, NULL);
 240 #endif
 241
 242 #if defined(SIGBUS)
 243                 sigaction(SIGBUS, &act, NULL);
 244 #endif
 245         }
 246 }
 247
 248
 249 /* function gen_mcode **********************************************************
 250
 251         generates machine code
 252
 253 *******************************************************************************/
 254
 255 void codegen(methodinfo *m, codegendata *cd, registerdata *rd)
 256 {
 257         s4     len, s1, s2, s3, d;
 258         ptrint a;
 259         s4 parentargs_base;
 260         s4             *mcodeptr;
 261         stackptr        src;
 262         varinfo        *var;
 263         basicblock     *bptr;
 264         instruction    *iptr;
 265         exceptiontable *ex;
 266         u2 currentline=0;
 267         {
 268         s4 i, p, pa, t, l;
 269         s4 savedregs_num;
 270
 271         savedregs_num = (m->isleafmethod) ? 0 : 1;        /* space to save the RA */
 272
 273         /* space to save used callee saved registers */
 274
 275         savedregs_num += (rd->savintregcnt - rd->maxsavintreguse);
 276         savedregs_num += (rd->savfltregcnt - rd->maxsavfltreguse);
 277
 278         parentargs_base = rd->maxmemuse + savedregs_num;
 279
 280 #if defined(USE_THREADS)           /* space to save argument of monitor_enter */
 281
 282         if (checksync && (m->flags & ACC_SYNCHRONIZED))
 283                 parentargs_base++;
 284
 285 #endif
 286
 287         /* create method header */
 288
 289         (void) dseg_addaddress(cd, m);                          /* MethodPointer  */
 290         (void) dseg_adds4(cd, parentargs_base * 8);             /* FrameSize      */
 291
 292 #if defined(USE_THREADS)
 293
 294         /* IsSync contains the offset relative to the stack pointer for the
 295            argument of monitor_exit used in the exception handler. Since the
 296            offset could be zero and give a wrong meaning of the flag it is
 297            offset by one.
 298         */
 299
 300         if (checksync && (m->flags & ACC_SYNCHRONIZED))
 301                 (void) dseg_adds4(cd, (rd->maxmemuse + 1) * 8);     /* IsSync         */
 302         else
 303
 304 #endif
 305
 306         (void) dseg_adds4(cd, 0);                               /* IsSync         */
 307
 308         (void) dseg_adds4(cd, m->isleafmethod);                 /* IsLeaf         */
 309         (void) dseg_adds4(cd, rd->savintregcnt - rd->maxsavintreguse);/* IntSave  */
 310         (void) dseg_adds4(cd, rd->savfltregcnt - rd->maxsavfltreguse);/* FltSave  */
 311
 312         dseg_addlinenumbertablesize(cd);
 313
 314         (void) dseg_adds4(cd, cd->exceptiontablelength);        /* ExTableSize    */
 315
 316         /* create exception table */
 317
 318         for (ex = cd->exceptiontable; ex != NULL; ex = ex->down) {
 319                 dseg_addtarget(cd, ex->start);
 320                 dseg_addtarget(cd, ex->end);
 321                 dseg_addtarget(cd, ex->handler);
 322                 (void) dseg_addaddress(cd, ex->catchtype.cls);
 323         }
 324
 325         /* initialize mcode variables */
 326
 327         mcodeptr = (s4 *) cd->mcodebase;
 328         cd->mcodeend = (s4 *) (cd->mcodebase + cd->mcodesize);
 329         MCODECHECK(128 + m->paramcount);
 330
 331         /* create stack frame (if necessary) */
 332
 333         if (parentargs_base) {
 334                 M_LDA(REG_SP, REG_SP, -parentargs_base * 8);
 335         }
 336
 337         /* save return address and used callee saved registers */
 338
 339         p = parentargs_base;
 340         if (!m->isleafmethod) {
 341                 p--; M_AST(REG_RA, REG_SP, p * 8);
 342         }
 343         for (i = rd->savintregcnt - 1; i >= rd->maxsavintreguse; i--) {
 344                 p--; M_LST(rd->savintregs[i], REG_SP, p * 8);
 345         }
 346         for (i = rd->savfltregcnt - 1; i >= rd->maxsavfltreguse; i--) {
 347                 p--; M_DST(rd->savfltregs[i], REG_SP, p * 8);
 348         }
 349
 350         /* copy argument registers to stack and call trace function with pointer
 351            to arguments on stack.
 352         */
 353
 354         if (runverbose) {
 355                 s4 disp;
 356                 M_LDA(REG_SP, REG_SP, -((INT_ARG_CNT + FLT_ARG_CNT + 2) * 8));
 357                 M_AST(REG_RA, REG_SP, 1 * 8);
 358
 359                 /* save integer argument registers */
 360                 for (p = 0; p < m->paramcount && p < INT_ARG_CNT; p++) {
 361                         M_LST(rd->argintregs[p], REG_SP,  (2 + p) * 8);
 362                 }
 363
 364                 /* save and copy float arguments into integer registers */
 365                 for (p = 0; p < m->paramcount && p < FLT_ARG_CNT; p++) {
 366                         t = m->paramtypes[p];
 367
 368                         if (IS_FLT_DBL_TYPE(t)) {
 369                                 if (IS_2_WORD_TYPE(t)) {
 370                                         M_DST(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 371
 372                                 } else {
 373                                         M_FST(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 374                                 }
 375
 376                                 M_LLD(rd->argintregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 377
 378                         } else {
 379                                 M_DST(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 380                         }
 381                 }
 382
 383                 p = dseg_addaddress(cd, m);
 384                 M_ALD(REG_ITMP1, REG_PV, p);
 385                 M_AST(REG_ITMP1, REG_SP, 0 * 8);
 386                 p = dseg_addaddress(cd, (void *) builtin_trace_args);
 387                 M_ALD(REG_PV, REG_PV, p);
 388                 M_JSR(REG_RA, REG_PV);
 389                 disp = -(s4) ((u1 *) mcodeptr - cd->mcodebase);
 390                 M_LDA(REG_PV, REG_RA, disp);
 391                 M_ALD(REG_RA, REG_SP, 1 * 8);
 392
 393                 for (p = 0; p < m->paramcount && p < INT_ARG_CNT; p++) {
 394                         M_LLD(rd->argintregs[p], REG_SP,  (2 + p) * 8);
 395                 }
 396
 397                 for (p = 0; p < m->paramcount && p < FLT_ARG_CNT; p++) {
 398                         t = m->paramtypes[p];
 399
 400                         if (IS_FLT_DBL_TYPE(t)) {
 401                                 if (IS_2_WORD_TYPE(t)) {
 402                                         M_DLD(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 403
 404                                 } else {
 405                                         M_FLD(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 406                                 }
 407
 408                         } else {
 409                                 M_DLD(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 410                         }
 411                 }
 412
 413                 M_LDA(REG_SP, REG_SP, (INT_ARG_CNT + FLT_ARG_CNT + 2) * 8);
 414         }
 415
 416         /* take arguments out of register or stack frame */
 417
 418         for (p = 0, l = 0; p < m->paramcount; p++) {
 419                 t = m->paramtypes[p];
 420                 var = &(rd->locals[l][t]);
 421                 l++;
 422                 if (IS_2_WORD_TYPE(t))    /* increment local counter for 2 word types */
 423                         l++;
 424                 if (var->type < 0)
 425                         continue;
 426                 if (IS_INT_LNG_TYPE(t)) {                    /* integer args          */
 427                         if (p < INT_ARG_CNT) {                   /* register arguments    */
 428                                 if (!(var->flags & INMEMORY)) {      /* reg arg -> register   */
 429                                         M_INTMOVE(rd->argintregs[p], var->regoff);
 430                                 } else {                             /* reg arg -> spilled    */
 431                                         M_LST(rd->argintregs[p], REG_SP, 8 * var->regoff);
 432                                 }
 433
 434                         } else {                                 /* stack arguments       */
 435                                 pa = p - INT_ARG_CNT;
 436                                 if (!(var->flags & INMEMORY)) {      /* stack arg -> register */
 437                                         M_LLD(var->regoff, REG_SP, 8 * (parentargs_base + pa));
 438
 439                                 } else {                             /* stack arg -> spilled  */
 440 /*                                      M_LLD(REG_ITMP1, REG_SP, 8 * (parentargs_base + pa)); */
 441 /*                                      M_LST(REG_ITMP1, REG_SP, 8 * var->regoff); */
 442                                         var->regoff = parentargs_base + pa;
 443                                 }
 444                         }
 445
 446                 } else {                                     /* floating args         */
 447                         if (p < FLT_ARG_CNT) {                   /* register arguments    */
 448                                 if (!(var->flags & INMEMORY)) {      /* reg arg -> register   */
 449                                         M_FLTMOVE(rd->argfltregs[p], var->regoff);
 450
 451                                 } else {                                         /* reg arg -> spilled    */
 452                                         M_DST(rd->argfltregs[p], REG_SP, 8 * var->regoff);
 453                                 }
 454
 455                         } else {                                 /* stack arguments       */
 456                                 pa = p - FLT_ARG_CNT;
 457                                 if (!(var->flags & INMEMORY)) {      /* stack-arg -> register */
 458                                         M_DLD(var->regoff, REG_SP, 8 * (parentargs_base + pa) );
 459
 460                                 } else {                             /* stack-arg -> spilled  */
 461 /*                                      M_DLD(REG_FTMP1, REG_SP, 8 * (parentargs_base + pa)); */
 462 /*                                      M_DST(REG_FTMP1, REG_SP, 8 * var->regoff); */
 463                                         var->regoff = parentargs_base + pa;
 464                                 }
 465                         }
 466                 }
 467         } /* end for */
 468
 469         /* call monitorenter function */
 470
 471 #if defined(USE_THREADS)
 472         if (checksync && (m->flags & ACC_SYNCHRONIZED)) {
 473                 s4 disp;
 474
 475                 if (m->flags & ACC_STATIC) {
 476                         p = dseg_addaddress(cd, m->class);
 477                         M_ALD(REG_ITMP1, REG_PV, p);
 478                         M_AST(REG_ITMP1, REG_SP, rd->maxmemuse * 8);
 479                         M_INTMOVE(REG_ITMP1, rd->argintregs[0]);
 480                         p = dseg_addaddress(cd, BUILTIN_staticmonitorenter);
 481                         M_ALD(REG_PV, REG_PV, p);
 482                         M_JSR(REG_RA, REG_PV);
 483                         disp = -(s4) ((u1 *) mcodeptr - cd->mcodebase);
 484                         M_LDA(REG_PV, REG_RA, disp);
 485
 486                 } else {
 487                         M_BEQZ(rd->argintregs[0], 0);
 488                         codegen_addxnullrefs(cd, mcodeptr);
 489                         M_AST(rd->argintregs[0], REG_SP, rd->maxmemuse * 8);
 490                         p = dseg_addaddress(cd, BUILTIN_monitorenter);
 491                         M_ALD(REG_PV, REG_PV, p);
 492                         M_JSR(REG_RA, REG_PV);
 493                         disp = -(s4) ((u1 *) mcodeptr - cd->mcodebase);
 494                         M_LDA(REG_PV, REG_RA, disp);
 495                 }
 496         }
 497 #endif
 498
 499         }
 500
 501         /* end of header generation */
 502
 503         /* walk through all basic blocks */
 504         for (bptr = m->basicblocks; bptr != NULL; bptr = bptr->next) {
 505
 506                 bptr->mpc = (s4) ((u1 *) mcodeptr - cd->mcodebase);
 507
 508                 if (bptr->flags >= BBREACHED) {
 509
 510                 /* branch resolving */
 511
 512                 {
 513                 branchref *brefs;
 514                 for (brefs = bptr->branchrefs; brefs != NULL; brefs = brefs->next) {
 515                         gen_resolvebranch((u1*) cd->mcodebase + brefs->branchpos,
 516                                           brefs->branchpos, bptr->mpc);
 517                         }
 518                 }
 519
 520                 /* copy interface registers to their destination */
 521
 522                 src = bptr->instack;
 523                 len = bptr->indepth;
 524                 MCODECHECK(64+len);
 525 #ifdef LSRA
 526                 if (opt_lsra) {
 527                 while (src != NULL) {
 528                         len--;
 529                         if ((len == 0) && (bptr->type != BBTYPE_STD)) {
 530                                         /*                              d = reg_of_var(m, src, REG_ITMP1); */
 531                                         if (!(src->flags & INMEMORY))
 532                                                 d= src->regoff;
 533                                         else
 534                                                 d=REG_ITMP1;
 535                                         M_INTMOVE(REG_ITMP1, d);
 536                                         store_reg_to_var_int(src, d);
 537                                 }
 538                                 src = src->prev;
 539                         }
 540                 } else {
 541 #endif
 542                         while (src != NULL) {
 543                                 len--;
 544                                 if ((len == 0) && (bptr->type != BBTYPE_STD)) {
 545                                 d = reg_of_var(rd, src, REG_ITMP1);
 546                                 M_INTMOVE(REG_ITMP1, d);
 547                                 store_reg_to_var_int(src, d);
 548                                 }
 549                         else {
 550                                 d = reg_of_var(rd, src, REG_IFTMP);
 551                                 if ((src->varkind != STACKVAR)) {
 552                                         s2 = src->type;
 553                                         if (IS_FLT_DBL_TYPE(s2)) {
 554                                                 if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
 555                                                         s1 = rd->interfaces[len][s2].regoff;
 556                                                         M_FLTMOVE(s1,d);
 557                                                         }
 558                                                 else {
 559                                                         M_DLD(d, REG_SP, 8 * rd->interfaces[len][s2].regoff);
 560                                                         }
 561                                                 store_reg_to_var_flt(src, d);
 562                                                 }
 563                                         else {
 564                                                 if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
 565                                                         s1 = rd->interfaces[len][s2].regoff;
 566                                                         M_INTMOVE(s1,d);
 567                                                         }
 568                                                 else {
 569                                                         M_LLD(d, REG_SP, 8 * rd->interfaces[len][s2].regoff);
 570                                                         }
 571                                                 store_reg_to_var_int(src, d);
 572                                                 }
 573                                         }
 574                                 }
 575                         src = src->prev;
 576                         }
 577 #ifdef LSRA
 578                 }
 579 #endif
 580
 581                 /* walk through all instructions */
 582
 583                 src = bptr->instack;
 584                 len = bptr->icount;
 585
 586                 for (iptr = bptr->iinstr; len > 0; src = iptr->dst, len--, iptr++) {
 587                         if (iptr->line != currentline) {
 588                                 dseg_addlinenumber(cd, iptr->line, mcodeptr);
 589                                 currentline = iptr->line;
 590                         }
 591
 592                 MCODECHECK(64);       /* an instruction usually needs < 64 words      */
 593                 switch (iptr->opc) {
 594
 595                 case ICMD_INLINE_START:
 596                 case ICMD_INLINE_END:
 597                         break;
 598
 599                 case ICMD_NOP:        /* ...  ==> ...                                 */
 600                         break;
 601
 602                 case ICMD_CHECKNULL:  /* ..., objectref  ==> ..., objectref           */
 603
 604                         var_to_reg_int(s1, src, REG_ITMP1);
 605                         M_BEQZ(s1, 0);
 606                         codegen_addxnullrefs(cd, mcodeptr);
 607                         break;
 608
 609                 /* constant operations ************************************************/
 610
 611                 case ICMD_ICONST:     /* ...  ==> ..., constant                       */
 612                                       /* op1 = 0, val.i = constant                    */
 613
 614                         d = reg_of_var(rd, iptr->dst, REG_ITMP1);
 615                         ICONST(d, iptr->val.i);
 616                         store_reg_to_var_int(iptr->dst, d);
 617                         break;
 618
 619                 case ICMD_LCONST:     /* ...  ==> ..., constant                       */
 620                                       /* op1 = 0, val.l = constant                    */
 621
 622                         d = reg_of_var(rd, iptr->dst, REG_ITMP1);
 623                         LCONST(d, iptr->val.l);
 624                         store_reg_to_var_int(iptr->dst, d);
 625                         break;
 626
 627                 case ICMD_FCONST:     /* ...  ==> ..., constant                       */
 628                                       /* op1 = 0, val.f = constant                    */
 629
 630                         d = reg_of_var(rd, iptr->dst, REG_FTMP1);
 631                         a = dseg_addfloat(cd, iptr->val.f);
 632                         M_FLD(d, REG_PV, a);
 633                         store_reg_to_var_flt(iptr->dst, d);
 634                         break;
 635
 636                 case ICMD_DCONST:     /* ...  ==> ..., constant                       */
 637                                       /* op1 = 0, val.d = constant                    */
 638
 639                         d = reg_of_var(rd, iptr->dst, REG_FTMP1);
 640                         a = dseg_adddouble(cd, iptr->val.d);
 641                         M_DLD(d, REG_PV, a);
 642                         store_reg_to_var_flt(iptr->dst, d);
 643                         break;
 644
 645                 case ICMD_ACONST:     /* ...  ==> ..., constant                       */
 646                                       /* op1 = 0, val.a = constant                    */
 647
 648                         d = reg_of_var(rd, iptr->dst, REG_ITMP1);
 649                         if (iptr->val.a) {
 650                                 a = dseg_addaddress(cd, iptr->val.a);
 651                                 M_ALD(d, REG_PV, a);
 652                         } else {
 653                                 M_INTMOVE(REG_ZERO, d);
 654                         }
 655                         store_reg_to_var_int(iptr->dst, d);
 656                         break;
 657
 658
 659                 /* load/store operations **********************************************/
 660
 661                 case ICMD_ILOAD:      /* ...  ==> ..., content of local variable      */
 662                 case ICMD_LLOAD:      /* op1 = local variable                         */
 663                 case ICMD_ALOAD:
 664
 665                         d = reg_of_var(rd, iptr->dst, REG_ITMP1);
 666                         if ((iptr->dst->varkind == LOCALVAR) &&
 667                             (iptr->dst->varnum == iptr->op1))
 668                                 break;
 669                         var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
 670                         if (var->flags & INMEMORY)
 671                                 M_LLD(d, REG_SP, 8 * var->regoff);
 672                         else
 673                                 {M_INTMOVE(var->regoff,d);}
 674                         store_reg_to_var_int(iptr->dst, d);
 675                         break;
 676
 677                 case ICMD_FLOAD:      /* ...  ==> ..., content of local variable      */
 678                 case ICMD_DLOAD:      /* op1 = local variable                         */
 679
 680                         d = reg_of_var(rd, iptr->dst, REG_FTMP1);
 681                         if ((iptr->dst->varkind == LOCALVAR) &&
 682                             (iptr->dst->varnum == iptr->op1))
 683                                 break;
 684                         var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
 685                         if (var->flags & INMEMORY)
 686                                 M_DLD(d, REG_SP, 8 * var->regoff);
 687                         else
 688                                 {M_FLTMOVE(var->regoff,d);}
 689                         store_reg_to_var_flt(iptr->dst, d);
 690                         break;
 691
 692
 693                 case ICMD_ISTORE:     /* ..., value  ==> ...                          */
 694                 case ICMD_LSTORE:     /* op1 = local variable                         */
 695                 case ICMD_ASTORE:
 696
 697                         if ((src->varkind == LOCALVAR) &&
 698                             (src->varnum == iptr->op1))
 699                                 break;
 700                         var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
 701                         if (var->flags & INMEMORY) {
 702                                 var_to_reg_int(s1, src, REG_ITMP1);
 703                                 M_LST(s1, REG_SP, 8 * var->regoff);
 704                                 }
 705                         else {
 706                                 var_to_reg_int(s1, src, var->regoff);
 707                                 M_INTMOVE(s1, var->regoff);
 708                                 }
 709                         break;
 710
 711                 case ICMD_FSTORE:     /* ..., value  ==> ...                          */
 712                 case ICMD_DSTORE:     /* op1 = local variable                         */
 713
 714                         if ((src->varkind == LOCALVAR) &&
 715                             (src->varnum == iptr->op1))
 716                                 break;
 717                         var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
 718                         if (var->flags & INMEMORY) {
 719                                 var_to_reg_flt(s1, src, REG_FTMP1);
 720                                 M_DST(s1, REG_SP, 8 * var->regoff);
 721                                 }
 722                         else {
 723                                 var_to_reg_flt(s1, src, var->regoff);
 724                                 M_FLTMOVE(s1, var->regoff);
 725                                 }
 726                         break;
 727
 728
 729                 /* pop/dup/swap operations ********************************************/
 730
 731                 /* attention: double and longs are only one entry in CACAO ICMDs      */
 732
 733                 case ICMD_POP:        /* ..., value  ==> ...                          */
 734                 case ICMD_POP2:       /* ..., value, value  ==> ...                   */
 735                         break;
 736
 737                 case ICMD_DUP:        /* ..., a ==> ..., a, a                         */
 738                         M_COPY(src, iptr->dst);
 739                         break;
 740
 741                 case ICMD_DUP_X1:     /* ..., a, b ==> ..., b, a, b                   */
 742
 743                         M_COPY(src,       iptr->dst);
 744                         M_COPY(src->prev, iptr->dst->prev);
 745                         M_COPY(iptr->dst, iptr->dst->prev->prev);
 746                         break;
 747
 748                 case ICMD_DUP_X2:     /* ..., a, b, c ==> ..., c, a, b, c             */
 749
 750                         M_COPY(src,             iptr->dst);
 751                         M_COPY(src->prev,       iptr->dst->prev);
 752                         M_COPY(src->prev->prev, iptr->dst->prev->prev);
 753                         M_COPY(iptr->dst,       iptr->dst->prev->prev->prev);
 754                         break;
 755
 756                 case ICMD_DUP2:       /* ..., a, b ==> ..., a, b, a, b                */
 757
 758                         M_COPY(src,       iptr->dst);
 759                         M_COPY(src->prev, iptr->dst->prev);
 760                         break;
 761
 762                 case ICMD_DUP2_X1:    /* ..., a, b, c ==> ..., b, c, a, b, c          */
 763
 764                         M_COPY(src,             iptr->dst);
 765                         M_COPY(src->prev,       iptr->dst->prev);
 766                         M_COPY(src->prev->prev, iptr->dst->prev->prev);
 767                         M_COPY(iptr->dst,       iptr->dst->prev->prev->prev);
 768                         M_COPY(iptr->dst->prev, iptr->dst->prev->prev->prev->prev);
 769                         break;
 770
 771                 case ICMD_DUP2_X2:    /* ..., a, b, c, d ==> ..., c, d, a, b, c, d    */
 772
 773                         M_COPY(src,                   iptr->dst);
 774                         M_COPY(src->prev,             iptr->dst->prev);
 775                         M_COPY(src->prev->prev,       iptr->dst->prev->prev);
 776                         M_COPY(src->prev->prev->prev, iptr->dst->prev->prev->prev);
 777                         M_COPY(iptr->dst,             iptr->dst->prev->prev->prev->prev);
 778                         M_COPY(iptr->dst->prev,       iptr->dst->prev->prev->prev->prev->prev);
 779                         break;
 780
 781                 case ICMD_SWAP:       /* ..., a, b ==> ..., b, a                      */
 782
 783                         M_COPY(src,       iptr->dst->prev);
 784                         M_COPY(src->prev, iptr->dst);
 785                         break;
 786
 787
 788                 /* integer operations *************************************************/
 789
 790                 case ICMD_INEG:       /* ..., value  ==> ..., - value                 */
 791
 792                         var_to_reg_int(s1, src, REG_ITMP1);
 793                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 794                         M_ISUB(REG_ZERO, s1, d);
 795                         store_reg_to_var_int(iptr->dst, d);
 796                         break;
 797
 798                 case ICMD_LNEG:       /* ..., value  ==> ..., - value                 */
 799
 800                         var_to_reg_int(s1, src, REG_ITMP1);
 801                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 802                         M_LSUB(REG_ZERO, s1, d);
 803                         store_reg_to_var_int(iptr->dst, d);
 804                         break;
 805
 806                 case ICMD_I2L:        /* ..., value  ==> ..., value                   */
 807
 808                         var_to_reg_int(s1, src, REG_ITMP1);
 809                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 810                         M_INTMOVE(s1, d);
 811                         store_reg_to_var_int(iptr->dst, d);
 812                         break;
 813
 814                 case ICMD_L2I:        /* ..., value  ==> ..., value                   */
 815
 816                         var_to_reg_int(s1, src, REG_ITMP1);
 817                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 818                         M_IADD(s1, REG_ZERO, d );
 819                         store_reg_to_var_int(iptr->dst, d);
 820                         break;
 821
 822                 case ICMD_INT2BYTE:   /* ..., value  ==> ..., value                   */
 823
 824                         var_to_reg_int(s1, src, REG_ITMP1);
 825                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 826                         if (has_ext_instr_set) {
 827                                 M_BSEXT(s1, d);
 828                                 }
 829                         else {
 830                                 M_SLL_IMM(s1, 56, d);
 831                                 M_SRA_IMM( d, 56, d);
 832                                 }
 833                         store_reg_to_var_int(iptr->dst, d);
 834                         break;
 835
 836                 case ICMD_INT2CHAR:   /* ..., value  ==> ..., value                   */
 837
 838                         var_to_reg_int(s1, src, REG_ITMP1);
 839                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 840             M_CZEXT(s1, d);
 841                         store_reg_to_var_int(iptr->dst, d);
 842                         break;
 843
 844                 case ICMD_INT2SHORT:  /* ..., value  ==> ..., value                   */
 845
 846                         var_to_reg_int(s1, src, REG_ITMP1);
 847                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 848                         if (has_ext_instr_set) {
 849                                 M_SSEXT(s1, d);
 850                                 }
 851                         else {
 852                                 M_SLL_IMM(s1, 48, d);
 853                                 M_SRA_IMM( d, 48, d);
 854                                 }
 855                         store_reg_to_var_int(iptr->dst, d);
 856                         break;
 857
 858
 859                 case ICMD_IADD:       /* ..., val1, val2  ==> ..., val1 + val2        */
 860
 861                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 862                         var_to_reg_int(s2, src, REG_ITMP2);
 863                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 864                         M_IADD(s1, s2, d);
 865                         store_reg_to_var_int(iptr->dst, d);
 866                         break;
 867
 868                 case ICMD_IADDCONST:  /* ..., value  ==> ..., value + constant        */
 869                                       /* val.i = constant                             */
 870
 871                         var_to_reg_int(s1, src, REG_ITMP1);
 872                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 873                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
 874                                 M_IADD_IMM(s1, iptr->val.i, d);
 875                                 }
 876                         else {
 877                                 ICONST(REG_ITMP2, iptr->val.i);
 878                                 M_IADD(s1, REG_ITMP2, d);
 879                                 }
 880                         store_reg_to_var_int(iptr->dst, d);
 881                         break;
 882
 883                 case ICMD_LADD:       /* ..., val1, val2  ==> ..., val1 + val2        */
 884
 885                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 886                         var_to_reg_int(s2, src, REG_ITMP2);
 887                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 888                         M_LADD(s1, s2, d);
 889                         store_reg_to_var_int(iptr->dst, d);
 890                         break;
 891
 892                 case ICMD_LADDCONST:  /* ..., value  ==> ..., value + constant        */
 893                                       /* val.l = constant                             */
 894
 895                         var_to_reg_int(s1, src, REG_ITMP1);
 896                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 897                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
 898                                 M_LADD_IMM(s1, iptr->val.l, d);
 899                                 }
 900                         else {
 901                                 LCONST(REG_ITMP2, iptr->val.l);
 902                                 M_LADD(s1, REG_ITMP2, d);
 903                                 }
 904                         store_reg_to_var_int(iptr->dst, d);
 905                         break;
 906
 907                 case ICMD_ISUB:       /* ..., val1, val2  ==> ..., val1 - val2        */
 908
 909                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 910                         var_to_reg_int(s2, src, REG_ITMP2);
 911                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 912                         M_ISUB(s1, s2, d);
 913                         store_reg_to_var_int(iptr->dst, d);
 914                         break;
 915
 916                 case ICMD_ISUBCONST:  /* ..., value  ==> ..., value + constant        */
 917                                       /* val.i = constant                             */
 918
 919                         var_to_reg_int(s1, src, REG_ITMP1);
 920                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 921                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
 922                                 M_ISUB_IMM(s1, iptr->val.i, d);
 923                                 }
 924                         else {
 925                                 ICONST(REG_ITMP2, iptr->val.i);
 926                                 M_ISUB(s1, REG_ITMP2, d);
 927                                 }
 928                         store_reg_to_var_int(iptr->dst, d);
 929                         break;
 930
 931                 case ICMD_LSUB:       /* ..., val1, val2  ==> ..., val1 - val2        */
 932
 933                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 934                         var_to_reg_int(s2, src, REG_ITMP2);
 935                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 936                         M_LSUB(s1, s2, d);
 937                         store_reg_to_var_int(iptr->dst, d);
 938                         break;
 939
 940                 case ICMD_LSUBCONST:  /* ..., value  ==> ..., value - constant        */
 941                                       /* val.l = constant                             */
 942
 943                         var_to_reg_int(s1, src, REG_ITMP1);
 944                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 945                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
 946                                 M_LSUB_IMM(s1, iptr->val.l, d);
 947                                 }
 948                         else {
 949                                 LCONST(REG_ITMP2, iptr->val.l);
 950                                 M_LSUB(s1, REG_ITMP2, d);
 951                                 }
 952                         store_reg_to_var_int(iptr->dst, d);
 953                         break;
 954
 955                 case ICMD_IMUL:       /* ..., val1, val2  ==> ..., val1 * val2        */
 956
 957                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 958                         var_to_reg_int(s2, src, REG_ITMP2);
 959                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 960                         M_IMUL(s1, s2, d);
 961                         store_reg_to_var_int(iptr->dst, d);
 962                         break;
 963
 964                 case ICMD_IMULCONST:  /* ..., value  ==> ..., value * constant        */
 965                                       /* val.i = constant                             */
 966
 967                         var_to_reg_int(s1, src, REG_ITMP1);
 968                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 969                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
 970                                 M_IMUL_IMM(s1, iptr->val.i, d);
 971                                 }
 972                         else {
 973                                 ICONST(REG_ITMP2, iptr->val.i);
 974                                 M_IMUL(s1, REG_ITMP2, d);
 975                                 }
 976                         store_reg_to_var_int(iptr->dst, d);
 977                         break;
 978
 979                 case ICMD_LMUL:       /* ..., val1, val2  ==> ..., val1 * val2        */
 980
 981                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 982                         var_to_reg_int(s2, src, REG_ITMP2);
 983                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 984                         M_LMUL (s1, s2, d);
 985                         store_reg_to_var_int(iptr->dst, d);
 986                         break;
 987
 988                 case ICMD_LMULCONST:  /* ..., value  ==> ..., value * constant        */
 989                                       /* val.l = constant                             */
 990
 991                         var_to_reg_int(s1, src, REG_ITMP1);
 992                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 993                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
 994                                 M_LMUL_IMM(s1, iptr->val.l, d);
 995                                 }
 996                         else {
 997                                 LCONST(REG_ITMP2, iptr->val.l);
 998                                 M_LMUL(s1, REG_ITMP2, d);
 999                                 }
1000                         store_reg_to_var_int(iptr->dst, d);
1001                         break;
1002
1003                 case ICMD_IDIVPOW2:   /* ..., value  ==> ..., value << constant       */
1004                 case ICMD_LDIVPOW2:   /* val.i = constant                             */
1005
1006                         var_to_reg_int(s1, src, REG_ITMP1);
1007                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1008                         if (iptr->val.i <= 15) {
1009                                 M_LDA(REG_ITMP2, s1, (1 << iptr->val.i) -1);
1010                                 M_CMOVGE(s1, s1, REG_ITMP2);
1011                                 }
1012                         else {
1013                                 M_SRA_IMM(s1, 63, REG_ITMP2);
1014                                 M_SRL_IMM(REG_ITMP2, 64 - iptr->val.i, REG_ITMP2);
1015                                 M_LADD(s1, REG_ITMP2, REG_ITMP2);
1016                                 }
1017                         M_SRA_IMM(REG_ITMP2, iptr->val.i, d);
1018                         store_reg_to_var_int(iptr->dst, d);
1019                         break;
1020
1021                 case ICMD_ISHL:       /* ..., val1, val2  ==> ..., val1 << val2       */
1022
1023                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1024                         var_to_reg_int(s2, src, REG_ITMP2);
1025                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1026                         M_AND_IMM(s2, 0x1f, REG_ITMP3);
1027                         M_SLL(s1, REG_ITMP3, d);
1028                         M_IADD(d, REG_ZERO, d);
1029                         store_reg_to_var_int(iptr->dst, d);
1030                         break;
1031
1032                 case ICMD_ISHLCONST:  /* ..., value  ==> ..., value << constant       */
1033                                       /* val.i = constant                             */
1034
1035                         var_to_reg_int(s1, src, REG_ITMP1);
1036                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1037                         M_SLL_IMM(s1, iptr->val.i & 0x1f, d);
1038                         M_IADD(d, REG_ZERO, d);
1039                         store_reg_to_var_int(iptr->dst, d);
1040                         break;
1041
1042                 case ICMD_ISHR:       /* ..., val1, val2  ==> ..., val1 >> val2       */
1043
1044                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1045                         var_to_reg_int(s2, src, REG_ITMP2);
1046                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1047                         M_AND_IMM(s2, 0x1f, REG_ITMP3);
1048                         M_SRA(s1, REG_ITMP3, d);
1049                         store_reg_to_var_int(iptr->dst, d);
1050                         break;
1051
1052                 case ICMD_ISHRCONST:  /* ..., value  ==> ..., value >> constant       */
1053                                       /* val.i = constant                             */
1054
1055                         var_to_reg_int(s1, src, REG_ITMP1);
1056                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1057                         M_SRA_IMM(s1, iptr->val.i & 0x1f, d);
1058                         store_reg_to_var_int(iptr->dst, d);
1059                         break;
1060
1061                 case ICMD_IUSHR:      /* ..., val1, val2  ==> ..., val1 >>> val2      */
1062
1063                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1064                         var_to_reg_int(s2, src, REG_ITMP2);
1065                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1066                         M_AND_IMM(s2, 0x1f, REG_ITMP2);
1067             M_IZEXT(s1, d);
1068                         M_SRL(d, REG_ITMP2, d);
1069                         M_IADD(d, REG_ZERO, d);
1070                         store_reg_to_var_int(iptr->dst, d);
1071                         break;
1072
1073                 case ICMD_IUSHRCONST: /* ..., value  ==> ..., value >>> constant      */
1074                                       /* val.i = constant                             */
1075
1076                         var_to_reg_int(s1, src, REG_ITMP1);
1077                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1078             M_IZEXT(s1, d);
1079                         M_SRL_IMM(d, iptr->val.i & 0x1f, d);
1080                         M_IADD(d, REG_ZERO, d);
1081                         store_reg_to_var_int(iptr->dst, d);
1082                         break;
1083
1084                 case ICMD_LSHL:       /* ..., val1, val2  ==> ..., val1 << val2       */
1085
1086                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1087                         var_to_reg_int(s2, src, REG_ITMP2);
1088                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1089                         M_SLL(s1, s2, d);
1090                         store_reg_to_var_int(iptr->dst, d);
1091                         break;
1092
1093                 case ICMD_LSHLCONST:  /* ..., value  ==> ..., value << constant       */
1094                                       /* val.i = constant                             */
1095
1096                         var_to_reg_int(s1, src, REG_ITMP1);
1097                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1098                         M_SLL_IMM(s1, iptr->val.i & 0x3f, d);
1099                         store_reg_to_var_int(iptr->dst, d);
1100                         break;
1101
1102                 case ICMD_LSHR:       /* ..., val1, val2  ==> ..., val1 >> val2       */
1103
1104                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1105                         var_to_reg_int(s2, src, REG_ITMP2);
1106                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1107                         M_SRA(s1, s2, d);
1108                         store_reg_to_var_int(iptr->dst, d);
1109                         break;
1110
1111                 case ICMD_LSHRCONST:  /* ..., value  ==> ..., value >> constant       */
1112                                       /* val.i = constant                             */
1113
1114                         var_to_reg_int(s1, src, REG_ITMP1);
1115                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1116                         M_SRA_IMM(s1, iptr->val.i & 0x3f, d);
1117                         store_reg_to_var_int(iptr->dst, d);
1118                         break;
1119
1120                 case ICMD_LUSHR:      /* ..., val1, val2  ==> ..., val1 >>> val2      */
1121
1122                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1123                         var_to_reg_int(s2, src, REG_ITMP2);
1124                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1125                         M_SRL(s1, s2, d);
1126                         store_reg_to_var_int(iptr->dst, d);
1127                         break;
1128
1129                 case ICMD_LUSHRCONST: /* ..., value  ==> ..., value >>> constant      */
1130                                       /* val.i = constant                             */
1131
1132                         var_to_reg_int(s1, src, REG_ITMP1);
1133                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1134                         M_SRL_IMM(s1, iptr->val.i & 0x3f, d);
1135                         store_reg_to_var_int(iptr->dst, d);
1136                         break;
1137
1138                 case ICMD_IAND:       /* ..., val1, val2  ==> ..., val1 & val2        */
1139                 case ICMD_LAND:
1140
1141                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1142                         var_to_reg_int(s2, src, REG_ITMP2);
1143                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1144                         M_AND(s1, s2, d);
1145                         store_reg_to_var_int(iptr->dst, d);
1146                         break;
1147
1148                 case ICMD_IANDCONST:  /* ..., value  ==> ..., value & constant        */
1149                                       /* val.i = constant                             */
1150
1151                         var_to_reg_int(s1, src, REG_ITMP1);
1152                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1153                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
1154                                 M_AND_IMM(s1, iptr->val.i, d);
1155                                 }
1156                         else if (iptr->val.i == 0xffff) {
1157                                 M_CZEXT(s1, d);
1158                                 }
1159                         else if (iptr->val.i == 0xffffff) {
1160                                 M_ZAPNOT_IMM(s1, 0x07, d);
1161                                 }
1162                         else {
1163                                 ICONST(REG_ITMP2, iptr->val.i);
1164                                 M_AND(s1, REG_ITMP2, d);
1165                                 }
1166                         store_reg_to_var_int(iptr->dst, d);
1167                         break;
1168
1169                 case ICMD_IREMPOW2:   /* ..., value  ==> ..., value % constant        */
1170                                       /* val.i = constant                             */
1171
1172                         var_to_reg_int(s1, src, REG_ITMP1);
1173                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1174                         if (s1 == d) {
1175                                 M_MOV(s1, REG_ITMP1);
1176                                 s1 = REG_ITMP1;
1177                                 }
1178                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
1179                                 M_AND_IMM(s1, iptr->val.i, d);
1180                                 M_BGEZ(s1, 3);
1181                                 M_ISUB(REG_ZERO, s1, d);
1182                                 M_AND_IMM(d, iptr->val.i, d);
1183                                 }
1184                         else if (iptr->val.i == 0xffff) {
1185                                 M_CZEXT(s1, d);
1186                                 M_BGEZ(s1, 3);
1187                                 M_ISUB(REG_ZERO, s1, d);
1188                                 M_CZEXT(d, d);
1189                                 }
1190                         else if (iptr->val.i == 0xffffff) {
1191                                 M_ZAPNOT_IMM(s1, 0x07, d);
1192                                 M_BGEZ(s1, 3);
1193                                 M_ISUB(REG_ZERO, s1, d);
1194                                 M_ZAPNOT_IMM(d, 0x07, d);
1195                                 }
1196                         else {
1197                                 ICONST(REG_ITMP2, iptr->val.i);
1198                                 M_AND(s1, REG_ITMP2, d);
1199                                 M_BGEZ(s1, 3);
1200                                 M_ISUB(REG_ZERO, s1, d);
1201                                 M_AND(d, REG_ITMP2, d);
1202                                 }
1203                         M_ISUB(REG_ZERO, d, d);
1204                         store_reg_to_var_int(iptr->dst, d);
1205                         break;
1206
1207                 case ICMD_LANDCONST:  /* ..., value  ==> ..., value & constant        */
1208                                       /* val.l = constant                             */
1209
1210                         var_to_reg_int(s1, src, REG_ITMP1);
1211                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1212                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
1213                                 M_AND_IMM(s1, iptr->val.l, d);
1214                                 }
1215                         else if (iptr->val.l == 0xffffL) {
1216                                 M_CZEXT(s1, d);
1217                                 }
1218                         else if (iptr->val.l == 0xffffffL) {
1219                                 M_ZAPNOT_IMM(s1, 0x07, d);
1220                                 }
1221                         else if (iptr->val.l == 0xffffffffL) {
1222                                 M_IZEXT(s1, d);
1223                                 }
1224                         else if (iptr->val.l == 0xffffffffffL) {
1225                                 M_ZAPNOT_IMM(s1, 0x1f, d);
1226                                 }
1227                         else if (iptr->val.l == 0xffffffffffffL) {
1228                                 M_ZAPNOT_IMM(s1, 0x3f, d);
1229                                 }
1230                         else if (iptr->val.l == 0xffffffffffffffL) {
1231                                 M_ZAPNOT_IMM(s1, 0x7f, d);
1232                                 }
1233                         else {
1234                                 LCONST(REG_ITMP2, iptr->val.l);
1235                                 M_AND(s1, REG_ITMP2, d);
1236                                 }
1237                         store_reg_to_var_int(iptr->dst, d);
1238                         break;
1239
1240                 case ICMD_LREMPOW2:   /* ..., value  ==> ..., value % constant        */
1241                                       /* val.l = constant                             */
1242
1243                         var_to_reg_int(s1, src, REG_ITMP1);
1244                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1245                         if (s1 == d) {
1246                                 M_MOV(s1, REG_ITMP1);
1247                                 s1 = REG_ITMP1;
1248                                 }
1249                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
1250                                 M_AND_IMM(s1, iptr->val.l, d);
1251                                 M_BGEZ(s1, 3);
1252                                 M_LSUB(REG_ZERO, s1, d);
1253                                 M_AND_IMM(d, iptr->val.l, d);
1254                                 }
1255                         else if (iptr->val.l == 0xffffL) {
1256                                 M_CZEXT(s1, d);
1257                                 M_BGEZ(s1, 3);
1258                                 M_LSUB(REG_ZERO, s1, d);
1259                                 M_CZEXT(d, d);
1260                                 }
1261                         else if (iptr->val.l == 0xffffffL) {
1262                                 M_ZAPNOT_IMM(s1, 0x07, d);
1263                                 M_BGEZ(s1, 3);
1264                                 M_LSUB(REG_ZERO, s1, d);
1265                                 M_ZAPNOT_IMM(d, 0x07, d);
1266                                 }
1267                         else if (iptr->val.l == 0xffffffffL) {
1268                                 M_IZEXT(s1, d);
1269                                 M_BGEZ(s1, 3);
1270                                 M_LSUB(REG_ZERO, s1, d);
1271                                 M_IZEXT(d, d);
1272                                 }
1273                         else if (iptr->val.l == 0xffffffffffL) {
1274                                 M_ZAPNOT_IMM(s1, 0x1f, d);
1275                                 M_BGEZ(s1, 3);
1276                                 M_LSUB(REG_ZERO, s1, d);
1277                                 M_ZAPNOT_IMM(d, 0x1f, d);
1278                                 }
1279                         else if (iptr->val.l == 0xffffffffffffL) {
1280                                 M_ZAPNOT_IMM(s1, 0x3f, d);
1281                                 M_BGEZ(s1, 3);
1282                                 M_LSUB(REG_ZERO, s1, d);
1283                                 M_ZAPNOT_IMM(d, 0x3f, d);
1284                                 }
1285                         else if (iptr->val.l == 0xffffffffffffffL) {
1286                                 M_ZAPNOT_IMM(s1, 0x7f, d);
1287                                 M_BGEZ(s1, 3);
1288                                 M_LSUB(REG_ZERO, s1, d);
1289                                 M_ZAPNOT_IMM(d, 0x7f, d);
1290                                 }
1291                         else {
1292                                 LCONST(REG_ITMP2, iptr->val.l);
1293                                 M_AND(s1, REG_ITMP2, d);
1294                                 M_BGEZ(s1, 3);
1295                                 M_LSUB(REG_ZERO, s1, d);
1296                                 M_AND(d, REG_ITMP2, d);
1297                                 }
1298                         M_LSUB(REG_ZERO, d, d);
1299                         store_reg_to_var_int(iptr->dst, d);
1300                         break;
1301
1302                 case ICMD_IOR:        /* ..., val1, val2  ==> ..., val1 | val2        */
1303                 case ICMD_LOR:
1304
1305                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1306                         var_to_reg_int(s2, src, REG_ITMP2);
1307                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1308                         M_OR( s1,s2, d);
1309                         store_reg_to_var_int(iptr->dst, d);
1310                         break;
1311
1312                 case ICMD_IORCONST:   /* ..., value  ==> ..., value | constant        */
1313                                       /* val.i = constant                             */
1314
1315                         var_to_reg_int(s1, src, REG_ITMP1);
1316                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1317                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
1318                                 M_OR_IMM(s1, iptr->val.i, d);
1319                                 }
1320                         else {
1321                                 ICONST(REG_ITMP2, iptr->val.i);
1322                                 M_OR(s1, REG_ITMP2, d);
1323                                 }
1324                         store_reg_to_var_int(iptr->dst, d);
1325                         break;
1326
1327                 case ICMD_LORCONST:   /* ..., value  ==> ..., value | constant        */
1328                                       /* val.l = constant                             */
1329
1330                         var_to_reg_int(s1, src, REG_ITMP1);
1331                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1332                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
1333                                 M_OR_IMM(s1, iptr->val.l, d);
1334                                 }
1335                         else {
1336                                 LCONST(REG_ITMP2, iptr->val.l);
1337                                 M_OR(s1, REG_ITMP2, d);
1338                                 }
1339                         store_reg_to_var_int(iptr->dst, d);
1340                         break;
1341
1342                 case ICMD_IXOR:       /* ..., val1, val2  ==> ..., val1 ^ val2        */
1343                 case ICMD_LXOR:
1344
1345                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1346                         var_to_reg_int(s2, src, REG_ITMP2);
1347                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1348                         M_XOR(s1, s2, d);
1349                         store_reg_to_var_int(iptr->dst, d);
1350                         break;
1351
1352                 case ICMD_IXORCONST:  /* ..., value  ==> ..., value ^ constant        */
1353                                       /* val.i = constant                             */
1354
1355                         var_to_reg_int(s1, src, REG_ITMP1);
1356                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1357                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
1358                                 M_XOR_IMM(s1, iptr->val.i, d);
1359                                 }
1360                         else {
1361                                 ICONST(REG_ITMP2, iptr->val.i);
1362                                 M_XOR(s1, REG_ITMP2, d);
1363                                 }
1364                         store_reg_to_var_int(iptr->dst, d);
1365                         break;
1366
1367                 case ICMD_LXORCONST:  /* ..., value  ==> ..., value ^ constant        */
1368                                       /* val.l = constant                             */
1369
1370                         var_to_reg_int(s1, src, REG_ITMP1);
1371                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1372                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
1373                                 M_XOR_IMM(s1, iptr->val.l, d);
1374                                 }
1375                         else {
1376                                 LCONST(REG_ITMP2, iptr->val.l);
1377                                 M_XOR(s1, REG_ITMP2, d);
1378                                 }
1379                         store_reg_to_var_int(iptr->dst, d);
1380                         break;
1381
1382
1383                 case ICMD_LCMP:       /* ..., val1, val2  ==> ..., val1 cmp val2      */
1384
1385                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1386                         var_to_reg_int(s2, src, REG_ITMP2);
1387                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1388                         M_CMPLT(s1, s2, REG_ITMP3);
1389                         M_CMPLT(s2, s1, REG_ITMP1);
1390                         M_LSUB (REG_ITMP1, REG_ITMP3, d);
1391                         store_reg_to_var_int(iptr->dst, d);
1392                         break;
1393
1394
1395                 case ICMD_IINC:       /* ..., value  ==> ..., value + constant        */
1396                                       /* op1 = variable, val.i = constant             */
1397
1398                         var = &(rd->locals[iptr->op1][TYPE_INT]);
1399                         if (var->flags & INMEMORY) {
1400                                 s1 = REG_ITMP1;
1401                                 M_LLD(s1, REG_SP, 8 * var->regoff);
1402                                 }
1403                         else
1404                                 s1 = var->regoff;
1405                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
1406                                 M_IADD_IMM(s1, iptr->val.i, s1);
1407                                 }
1408                         else if ((iptr->val.i > -256) && (iptr->val.i < 0)) {
1409                                 M_ISUB_IMM(s1, (-iptr->val.i), s1);
1410                                 }
1411                         else {
1412                                 M_LDA (s1, s1, iptr->val.i);
1413                                 M_IADD(s1, REG_ZERO, s1);
1414                                 }
1415                         if (var->flags & INMEMORY)
1416                                 M_LST(s1, REG_SP, 8 * var->regoff);
1417                         break;
1418
1419
1420                 /* floating operations ************************************************/
1421
1422                 case ICMD_FNEG:       /* ..., value  ==> ..., - value                 */
1423
1424                         var_to_reg_flt(s1, src, REG_FTMP1);
1425                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1426                         M_FMOVN(s1, d);
1427                         store_reg_to_var_flt(iptr->dst, d);
1428                         break;
1429
1430                 case ICMD_DNEG:       /* ..., value  ==> ..., - value                 */
1431
1432                         var_to_reg_flt(s1, src, REG_FTMP1);
1433                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1434                         M_FMOVN(s1, d);
1435                         store_reg_to_var_flt(iptr->dst, d);
1436                         break;
1437
1438                 case ICMD_FADD:       /* ..., val1, val2  ==> ..., val1 + val2        */
1439
1440                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1441                         var_to_reg_flt(s2, src, REG_FTMP2);
1442                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1443                         if (opt_noieee) {
1444                                 M_FADD(s1, s2, d);
1445                                 }
1446                         else {
1447                                 if (d == s1 || d == s2) {
1448                                         M_FADDS(s1, s2, REG_FTMP3);
1449                                         M_TRAPB;
1450                                         M_FMOV(REG_FTMP3, d);
1451                                         }
1452                                 else {
1453                                         M_FADDS(s1, s2, d);
1454                                         M_TRAPB;
1455                                         }
1456                                 }
1457                         store_reg_to_var_flt(iptr->dst, d);
1458                         break;
1459
1460                 case ICMD_DADD:       /* ..., val1, val2  ==> ..., val1 + val2        */
1461
1462                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1463                         var_to_reg_flt(s2, src, REG_FTMP2);
1464                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1465                         if (opt_noieee) {
1466                                 M_DADD(s1, s2, d);
1467                                 }
1468                         else {
1469                                 if (d == s1 || d == s2) {
1470                                         M_DADDS(s1, s2, REG_FTMP3);
1471                                         M_TRAPB;
1472                                         M_FMOV(REG_FTMP3, d);
1473                                         }
1474                                 else {
1475                                         M_DADDS(s1, s2, d);
1476                                         M_TRAPB;
1477                                         }
1478                                 }
1479                         store_reg_to_var_flt(iptr->dst, d);
1480                         break;
1481
1482                 case ICMD_FSUB:       /* ..., val1, val2  ==> ..., val1 - val2        */
1483
1484                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1485                         var_to_reg_flt(s2, src, REG_FTMP2);
1486                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1487                         if (opt_noieee) {
1488                                 M_FSUB(s1, s2, d);
1489                                 }
1490                         else {
1491                                 if (d == s1 || d == s2) {
1492                                         M_FSUBS(s1, s2, REG_FTMP3);
1493                                         M_TRAPB;
1494                                         M_FMOV(REG_FTMP3, d);
1495                                         }
1496                                 else {
1497                                         M_FSUBS(s1, s2, d);
1498                                         M_TRAPB;
1499                                         }
1500                                 }
1501                         store_reg_to_var_flt(iptr->dst, d);
1502                         break;
1503
1504                 case ICMD_DSUB:       /* ..., val1, val2  ==> ..., val1 - val2        */
1505
1506                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1507                         var_to_reg_flt(s2, src, REG_FTMP2);
1508                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1509                         if (opt_noieee) {
1510                                 M_DSUB(s1, s2, d);
1511                                 }
1512                         else {
1513                                 if (d == s1 || d == s2) {
1514                                         M_DSUBS(s1, s2, REG_FTMP3);
1515                                         M_TRAPB;
1516                                         M_FMOV(REG_FTMP3, d);
1517                                         }
1518                                 else {
1519                                         M_DSUBS(s1, s2, d);
1520                                         M_TRAPB;
1521                                         }
1522                                 }
1523                         store_reg_to_var_flt(iptr->dst, d);
1524                         break;
1525
1526                 case ICMD_FMUL:       /* ..., val1, val2  ==> ..., val1 * val2        */
1527
1528                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1529                         var_to_reg_flt(s2, src, REG_FTMP2);
1530                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1531                         if (opt_noieee) {
1532                                 M_FMUL(s1, s2, d);
1533                                 }
1534                         else {
1535                                 if (d == s1 || d == s2) {
1536                                         M_FMULS(s1, s2, REG_FTMP3);
1537                                         M_TRAPB;
1538                                         M_FMOV(REG_FTMP3, d);
1539                                         }
1540                                 else {
1541                                         M_FMULS(s1, s2, d);
1542                                         M_TRAPB;
1543                                         }
1544                                 }
1545                         store_reg_to_var_flt(iptr->dst, d);
1546                         break;
1547
1548                 case ICMD_DMUL:       /* ..., val1, val2  ==> ..., val1 *** val2        */
1549
1550                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1551                         var_to_reg_flt(s2, src, REG_FTMP2);
1552                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1553                         if (opt_noieee) {
1554                                 M_DMUL(s1, s2, d);
1555                                 }
1556                         else {
1557                                 if (d == s1 || d == s2) {
1558                                         M_DMULS(s1, s2, REG_FTMP3);
1559                                         M_TRAPB;
1560                                         M_FMOV(REG_FTMP3, d);
1561                                         }
1562                                 else {
1563                                         M_DMULS(s1, s2, d);
1564                                         M_TRAPB;
1565                                         }
1566                                 }
1567                         store_reg_to_var_flt(iptr->dst, d);
1568                         break;
1569
1570                 case ICMD_FDIV:       /* ..., val1, val2  ==> ..., val1 / val2        */
1571
1572                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1573                         var_to_reg_flt(s2, src, REG_FTMP2);
1574                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1575                         if (opt_noieee) {
1576                                 M_FDIV(s1, s2, d);
1577                                 }
1578                         else {
1579                                 if (d == s1 || d == s2) {
1580                                         M_FDIVS(s1, s2, REG_FTMP3);
1581                                         M_TRAPB;
1582                                         M_FMOV(REG_FTMP3, d);
1583                                         }
1584                                 else {
1585                                         M_FDIVS(s1, s2, d);
1586                                         M_TRAPB;
1587                                         }
1588                                 }
1589                         store_reg_to_var_flt(iptr->dst, d);
1590                         break;
1591
1592                 case ICMD_DDIV:       /* ..., val1, val2  ==> ..., val1 / val2        */
1593
1594                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1595                         var_to_reg_flt(s2, src, REG_FTMP2);
1596                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1597                         if (opt_noieee) {
1598                                 M_DDIV(s1, s2, d);
1599                                 }
1600                         else {
1601                                 if (d == s1 || d == s2) {
1602                                         M_DDIVS(s1, s2, REG_FTMP3);
1603                                         M_TRAPB;
1604                                         M_FMOV(REG_FTMP3, d);
1605                                         }
1606                                 else {
1607                                         M_DDIVS(s1, s2, d);
1608                                         M_TRAPB;
1609                                         }
1610                                 }
1611                         store_reg_to_var_flt(iptr->dst, d);
1612                         break;
1613
1614                 case ICMD_I2F:       /* ..., value  ==> ..., (float) value            */
1615                 case ICMD_L2F:
1616                         var_to_reg_int(s1, src, REG_ITMP1);
1617                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1618                         a = dseg_adddouble(cd, 0.0);
1619                         M_LST (s1, REG_PV, a);
1620                         M_DLD (d, REG_PV, a);
1621                         M_CVTLF(d, d);
1622                         store_reg_to_var_flt(iptr->dst, d);
1623                         break;
1624
1625                 case ICMD_I2D:       /* ..., value  ==> ..., (double) value           */
1626                 case ICMD_L2D:
1627                         var_to_reg_int(s1, src, REG_ITMP1);
1628                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1629                         a = dseg_adddouble(cd, 0.0);
1630                         M_LST (s1, REG_PV, a);
1631                         M_DLD (d, REG_PV, a);
1632                         M_CVTLD(d, d);
1633                         store_reg_to_var_flt(iptr->dst, d);
1634                         break;
1635
1636                 case ICMD_F2I:       /* ..., value  ==> ..., (int) value              */
1637                 case ICMD_D2I:
1638                         var_to_reg_flt(s1, src, REG_FTMP1);
1639                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1640                         a = dseg_adddouble(cd, 0.0);
1641                         M_CVTDL_C(s1, REG_FTMP2);
1642                         M_CVTLI(REG_FTMP2, REG_FTMP3);
1643                         M_DST (REG_FTMP3, REG_PV, a);
1644                         M_ILD (d, REG_PV, a);
1645                         store_reg_to_var_int(iptr->dst, d);
1646                         break;
1647
1648                 case ICMD_F2L:       /* ..., value  ==> ..., (long) value             */
1649                 case ICMD_D2L:
1650                         var_to_reg_flt(s1, src, REG_FTMP1);
1651                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1652                         a = dseg_adddouble(cd, 0.0);
1653                         M_CVTDL_C(s1, REG_FTMP2);
1654                         M_DST (REG_FTMP2, REG_PV, a);
1655                         M_LLD (d, REG_PV, a);
1656                         store_reg_to_var_int(iptr->dst, d);
1657                         break;
1658
1659                 case ICMD_F2D:       /* ..., value  ==> ..., (double) value           */
1660
1661                         var_to_reg_flt(s1, src, REG_FTMP1);
1662                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1663                         M_CVTFDS(s1, d);
1664                         M_TRAPB;
1665                         store_reg_to_var_flt(iptr->dst, d);
1666                         break;
1667
1668                 case ICMD_D2F:       /* ..., value  ==> ..., (float) value            */
1669
1670                         var_to_reg_flt(s1, src, REG_FTMP1);
1671                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1672                         if (opt_noieee) {
1673                                 M_CVTDF(s1, d);
1674                                 }
1675                         else {
1676                                 M_CVTDFS(s1, d);
1677                                 M_TRAPB;
1678                                 }
1679                         store_reg_to_var_flt(iptr->dst, d);
1680                         break;
1681
1682                 case ICMD_FCMPL:      /* ..., val1, val2  ==> ..., val1 fcmpl val2    */
1683                 case ICMD_DCMPL:
1684                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1685                         var_to_reg_flt(s2, src, REG_FTMP2);
1686                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1687                         if (opt_noieee) {
1688                                 M_LSUB_IMM(REG_ZERO, 1, d);
1689                                 M_FCMPEQ(s1, s2, REG_FTMP3);
1690                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instructions */
1691                                 M_CLR   (d);
1692                                 M_FCMPLT(s2, s1, REG_FTMP3);
1693                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instruction  */
1694                                 M_LADD_IMM(REG_ZERO, 1, d);
1695                                 }
1696                         else {
1697                                 M_LSUB_IMM(REG_ZERO, 1, d);
1698                                 M_FCMPEQS(s1, s2, REG_FTMP3);
1699                                 M_TRAPB;
1700                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instructions */
1701                                 M_CLR   (d);
1702                                 M_FCMPLTS(s2, s1, REG_FTMP3);
1703                                 M_TRAPB;
1704                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instruction  */
1705                                 M_LADD_IMM(REG_ZERO, 1, d);
1706                                 }
1707                         store_reg_to_var_int(iptr->dst, d);
1708                         break;
1709
1710                 case ICMD_FCMPG:      /* ..., val1, val2  ==> ..., val1 fcmpg val2    */
1711                 case ICMD_DCMPG:
1712                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1713                         var_to_reg_flt(s2, src, REG_FTMP2);
1714                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1715                         if (opt_noieee) {
1716                                 M_LADD_IMM(REG_ZERO, 1, d);
1717                                 M_FCMPEQ(s1, s2, REG_FTMP3);
1718                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instruction  */
1719                                 M_CLR   (d);
1720                                 M_FCMPLT(s1, s2, REG_FTMP3);
1721                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instruction  */
1722                                 M_LSUB_IMM(REG_ZERO, 1, d);
1723                                 }
1724                         else {
1725                                 M_LADD_IMM(REG_ZERO, 1, d);
1726                                 M_FCMPEQS(s1, s2, REG_FTMP3);
1727                                 M_TRAPB;
1728                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instruction  */
1729                                 M_CLR   (d);
1730                                 M_FCMPLTS(s1, s2, REG_FTMP3);
1731                                 M_TRAPB;
1732                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instruction  */
1733                                 M_LSUB_IMM(REG_ZERO, 1, d);
1734                                 }
1735                         store_reg_to_var_int(iptr->dst, d);
1736                         break;
1737
1738
1739                 /* memory operations **************************************************/
1740
1741                 case ICMD_ARRAYLENGTH: /* ..., arrayref  ==> ..., length              */
1742
1743                         var_to_reg_int(s1, src, REG_ITMP1);
1744                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1745                         gen_nullptr_check(s1);
1746                         M_ILD(d, s1, OFFSET(java_arrayheader, size));
1747                         store_reg_to_var_int(iptr->dst, d);
1748                         break;
1749
1750                 case ICMD_AALOAD:     /* ..., arrayref, index  ==> ..., value         */
1751
1752                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1753                         var_to_reg_int(s2, src, REG_ITMP2);
1754                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1755                         if (iptr->op1 == 0) {
1756                                 gen_nullptr_check(s1);
1757                                 gen_bound_check;
1758                                 }
1759                         M_SAADDQ(s2, s1, REG_ITMP1);
1760                         M_ALD( d, REG_ITMP1, OFFSET(java_objectarray, data[0]));
1761                         store_reg_to_var_int(iptr->dst, d);
1762                         break;
1763
1764                 case ICMD_LALOAD:     /* ..., arrayref, index  ==> ..., value         */
1765
1766                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1767                         var_to_reg_int(s2, src, REG_ITMP2);
1768                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1769                         if (iptr->op1 == 0) {
1770                                 gen_nullptr_check(s1);
1771                                 gen_bound_check;
1772                                 }
1773                         M_S8ADDQ(s2, s1, REG_ITMP1);
1774                         M_LLD(d, REG_ITMP1, OFFSET(java_longarray, data[0]));
1775                         store_reg_to_var_int(iptr->dst, d);
1776                         break;
1777
1778                 case ICMD_IALOAD:     /* ..., arrayref, index  ==> ..., value         */
1779
1780                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1781                         var_to_reg_int(s2, src, REG_ITMP2);
1782                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1783                         if (iptr->op1 == 0) {
1784                                 gen_nullptr_check(s1);
1785                                 gen_bound_check;
1786                                 }
1787
1788                         M_S4ADDQ(s2, s1, REG_ITMP1);
1789                         M_ILD(d, REG_ITMP1, OFFSET(java_intarray, data[0]));
1790                         store_reg_to_var_int(iptr->dst, d);
1791                         break;
1792
1793                 case ICMD_FALOAD:     /* ..., arrayref, index  ==> ..., value         */
1794
1795                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1796                         var_to_reg_int(s2, src, REG_ITMP2);
1797                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1798                         if (iptr->op1 == 0) {
1799                                 gen_nullptr_check(s1);
1800                                 gen_bound_check;
1801                                 }
1802                         M_S4ADDQ(s2, s1, REG_ITMP1);
1803                         M_FLD(d, REG_ITMP1, OFFSET(java_floatarray, data[0]));
1804                         store_reg_to_var_flt(iptr->dst, d);
1805                         break;
1806
1807                 case ICMD_DALOAD:     /* ..., arrayref, index  ==> ..., value         */
1808
1809                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1810                         var_to_reg_int(s2, src, REG_ITMP2);
1811                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1812                         if (iptr->op1 == 0) {
1813                                 gen_nullptr_check(s1);
1814                                 gen_bound_check;
1815                                 }
1816                         M_S8ADDQ(s2, s1, REG_ITMP1);
1817                         M_DLD(d, REG_ITMP1, OFFSET(java_doublearray, data[0]));
1818                         store_reg_to_var_flt(iptr->dst, d);
1819                         break;
1820
1821                 case ICMD_CALOAD:     /* ..., arrayref, index  ==> ..., value         */
1822
1823                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1824                         var_to_reg_int(s2, src, REG_ITMP2);
1825                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1826                         if (iptr->op1 == 0) {
1827                                 gen_nullptr_check(s1);
1828                                 gen_bound_check;
1829                                 }
1830                         if (has_ext_instr_set) {
1831                                 M_LADD(s2, s1, REG_ITMP1);
1832                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1833                                 M_SLDU(d, REG_ITMP1, OFFSET(java_chararray, data[0]));
1834                                 }
1835                         else {
1836                                 M_LADD (s2, s1, REG_ITMP1);
1837                                 M_LADD (s2, REG_ITMP1, REG_ITMP1);
1838                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_chararray, data[0]));
1839                                 M_LDA  (REG_ITMP1, REG_ITMP1, OFFSET(java_chararray, data[0]));
1840                                 M_EXTWL(REG_ITMP2, REG_ITMP1, d);
1841                                 }
1842                         store_reg_to_var_int(iptr->dst, d);
1843                         break;
1844
1845                 case ICMD_SALOAD:     /* ..., arrayref, index  ==> ..., value         */
1846
1847                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1848                         var_to_reg_int(s2, src, REG_ITMP2);
1849                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1850                         if (iptr->op1 == 0) {
1851                                 gen_nullptr_check(s1);
1852                                 gen_bound_check;
1853                                 }
1854                         if (has_ext_instr_set) {
1855                                 M_LADD(s2, s1, REG_ITMP1);
1856                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1857                                 M_SLDU( d, REG_ITMP1, OFFSET (java_shortarray, data[0]));
1858                                 M_SSEXT(d, d);
1859                                 }
1860                         else {
1861                                 M_LADD(s2, s1, REG_ITMP1);
1862                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1863                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_shortarray, data[0]));
1864                                 M_LDA(REG_ITMP1, REG_ITMP1, OFFSET(java_shortarray, data[0])+2);
1865                                 M_EXTQH(REG_ITMP2, REG_ITMP1, d);
1866                                 M_SRA_IMM(d, 48, d);
1867                                 }
1868                         store_reg_to_var_int(iptr->dst, d);
1869                         break;
1870
1871                 case ICMD_BALOAD:     /* ..., arrayref, index  ==> ..., value         */
1872
1873                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1874                         var_to_reg_int(s2, src, REG_ITMP2);
1875                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1876                         if (iptr->op1 == 0) {
1877                                 gen_nullptr_check(s1);
1878                                 gen_bound_check;
1879                                 }
1880                         if (has_ext_instr_set) {
1881                                 M_LADD   (s2, s1, REG_ITMP1);
1882                                 M_BLDU   (d, REG_ITMP1, OFFSET (java_bytearray, data[0]));
1883                                 M_BSEXT  (d, d);
1884                                 }
1885                         else {
1886                                 M_LADD(s2, s1, REG_ITMP1);
1887                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_bytearray, data[0]));
1888                                 M_LDA(REG_ITMP1, REG_ITMP1, OFFSET(java_bytearray, data[0])+1);
1889                                 M_EXTQH(REG_ITMP2, REG_ITMP1, d);
1890                                 M_SRA_IMM(d, 56, d);
1891                                 }
1892                         store_reg_to_var_int(iptr->dst, d);
1893                         break;
1894
1895
1896                 case ICMD_AASTORE:    /* ..., arrayref, index, value  ==> ...         */
1897
1898                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1899                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1900                         if (iptr->op1 == 0) {
1901                                 gen_nullptr_check(s1);
1902                                 gen_bound_check;
1903                                 }
1904                         var_to_reg_int(s3, src, REG_ITMP3);
1905                         M_SAADDQ(s2, s1, REG_ITMP1);
1906                         M_AST   (s3, REG_ITMP1, OFFSET(java_objectarray, data[0]));
1907                         break;
1908
1909                 case ICMD_LASTORE:    /* ..., arrayref, index, value  ==> ...         */
1910
1911                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1912                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1913                         if (iptr->op1 == 0) {
1914                                 gen_nullptr_check(s1);
1915                                 gen_bound_check;
1916                                 }
1917                         var_to_reg_int(s3, src, REG_ITMP3);
1918                         M_S8ADDQ(s2, s1, REG_ITMP1);
1919                         M_LST   (s3, REG_ITMP1, OFFSET(java_longarray, data[0]));
1920                         break;
1921
1922                 case ICMD_IASTORE:    /* ..., arrayref, index, value  ==> ...         */
1923
1924                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1925                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1926                         if (iptr->op1 == 0) {
1927                                 gen_nullptr_check(s1);
1928                                 gen_bound_check;
1929                                 }
1930
1931                         var_to_reg_int(s3, src, REG_ITMP3);
1932                         M_S4ADDQ(s2, s1, REG_ITMP1);
1933                         M_IST   (s3, REG_ITMP1, OFFSET(java_intarray, data[0]));
1934                         break;
1935
1936                 case ICMD_FASTORE:    /* ..., arrayref, index, value  ==> ...         */
1937
1938                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1939                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1940                         if (iptr->op1 == 0) {
1941                                 gen_nullptr_check(s1);
1942                                 gen_bound_check;
1943                                 }
1944                         var_to_reg_flt(s3, src, REG_FTMP3);
1945                         M_S4ADDQ(s2, s1, REG_ITMP1);
1946                         M_FST   (s3, REG_ITMP1, OFFSET(java_floatarray, data[0]));
1947                         break;
1948
1949                 case ICMD_DASTORE:    /* ..., arrayref, index, value  ==> ...         */
1950
1951                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1952                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1953                         if (iptr->op1 == 0) {
1954                                 gen_nullptr_check(s1);
1955                                 gen_bound_check;
1956                                 }
1957                         var_to_reg_flt(s3, src, REG_FTMP3);
1958                         M_S8ADDQ(s2, s1, REG_ITMP1);
1959                         M_DST   (s3, REG_ITMP1, OFFSET(java_doublearray, data[0]));
1960                         break;
1961
1962                 case ICMD_CASTORE:    /* ..., arrayref, index, value  ==> ...         */
1963
1964                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1965                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1966                         if (iptr->op1 == 0) {
1967                                 gen_nullptr_check(s1);
1968                                 gen_bound_check;
1969                                 }
1970                         var_to_reg_int(s3, src, REG_ITMP3);
1971                         if (has_ext_instr_set) {
1972                                 M_LADD(s2, s1, REG_ITMP1);
1973                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1974                                 M_SST (s3, REG_ITMP1, OFFSET(java_chararray, data[0]));
1975                                 }
1976                         else {
1977                                 M_LADD (s2, s1, REG_ITMP1);
1978                                 M_LADD (s2, REG_ITMP1, REG_ITMP1);
1979                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_chararray, data[0]));
1980                                 M_LDA  (REG_ITMP1, REG_ITMP1, OFFSET(java_chararray, data[0]));
1981                                 M_INSWL(s3, REG_ITMP1, REG_ITMP3);
1982                                 M_MSKWL(REG_ITMP2, REG_ITMP1, REG_ITMP2);
1983                                 M_OR   (REG_ITMP2, REG_ITMP3, REG_ITMP2);
1984                                 M_LST_U(REG_ITMP2, REG_ITMP1, 0);
1985                                 }
1986                         break;
1987
1988                 case ICMD_SASTORE:    /* ..., arrayref, index, value  ==> ...         */
1989
1990                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1991                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1992                         if (iptr->op1 == 0) {
1993                                 gen_nullptr_check(s1);
1994                                 gen_bound_check;
1995                                 }
1996                         var_to_reg_int(s3, src, REG_ITMP3);
1997                         if (has_ext_instr_set) {
1998                                 M_LADD(s2, s1, REG_ITMP1);
1999                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
2000                                 M_SST (s3, REG_ITMP1, OFFSET(java_shortarray, data[0]));
2001                                 }
2002                         else {
2003                                 M_LADD (s2, s1, REG_ITMP1);
2004                                 M_LADD (s2, REG_ITMP1, REG_ITMP1);
2005                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_shortarray, data[0]));
2006                                 M_LDA  (REG_ITMP1, REG_ITMP1, OFFSET(java_shortarray, data[0]));
2007                                 M_INSWL(s3, REG_ITMP1, REG_ITMP3);
2008                                 M_MSKWL(REG_ITMP2, REG_ITMP1, REG_ITMP2);
2009                                 M_OR   (REG_ITMP2, REG_ITMP3, REG_ITMP2);
2010                                 M_LST_U(REG_ITMP2, REG_ITMP1, 0);
2011                                 }
2012                         break;
2013
2014                 case ICMD_BASTORE:    /* ..., arrayref, index, value  ==> ...         */
2015
2016                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
2017                         var_to_reg_int(s2, src->prev, REG_ITMP2);
2018                         if (iptr->op1 == 0) {
2019                                 gen_nullptr_check(s1);
2020                                 gen_bound_check;
2021                                 }
2022                         var_to_reg_int(s3, src, REG_ITMP3);
2023                         if (has_ext_instr_set) {
2024                                 M_LADD(s2, s1, REG_ITMP1);
2025                                 M_BST (s3, REG_ITMP1, OFFSET(java_bytearray, data[0]));
2026                                 }
2027                         else {
2028                                 M_LADD (s2, s1, REG_ITMP1);
2029                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_bytearray, data[0]));
2030                                 M_LDA  (REG_ITMP1, REG_ITMP1, OFFSET(java_bytearray, data[0]));
2031                                 M_INSBL(s3, REG_ITMP1, REG_ITMP3);
2032                                 M_MSKBL(REG_ITMP2, REG_ITMP1, REG_ITMP2);
2033                                 M_OR   (REG_ITMP2, REG_ITMP3, REG_ITMP2);
2034                                 M_LST_U(REG_ITMP2, REG_ITMP1, 0);
2035                                 }
2036                         break;
2037
2038
2039                 case ICMD_IASTORECONST:   /* ..., arrayref, index  ==> ...            */
2040
2041                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2042                         var_to_reg_int(s2, src, REG_ITMP2);
2043                         if (iptr->op1 == 0) {
2044                                 gen_nullptr_check(s1);
2045                                 gen_bound_check;
2046                         }
2047                         M_S4ADDQ(s2, s1, REG_ITMP1);
2048                         M_IST(REG_ZERO, REG_ITMP1, OFFSET(java_intarray, data[0]));
2049                         break;
2050
2051                 case ICMD_LASTORECONST:   /* ..., arrayref, index  ==> ...            */
2052
2053                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2054                         var_to_reg_int(s2, src, REG_ITMP2);
2055                         if (iptr->op1 == 0) {
2056                                 gen_nullptr_check(s1);
2057                                 gen_bound_check;
2058                         }
2059                         M_S8ADDQ(s2, s1, REG_ITMP1);
2060                         M_LST(REG_ZERO, REG_ITMP1, OFFSET(java_longarray, data[0]));
2061                         break;
2062
2063                 case ICMD_AASTORECONST:   /* ..., arrayref, index  ==> ...            */
2064
2065                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2066                         var_to_reg_int(s2, src, REG_ITMP2);
2067                         if (iptr->op1 == 0) {
2068                                 gen_nullptr_check(s1);
2069                                 gen_bound_check;
2070                         }
2071                         M_SAADDQ(s2, s1, REG_ITMP1);
2072                         M_AST(REG_ZERO, REG_ITMP1, OFFSET(java_objectarray, data[0]));
2073                         break;
2074
2075                 case ICMD_BASTORECONST:   /* ..., arrayref, index  ==> ...            */
2076
2077                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2078                         var_to_reg_int(s2, src, REG_ITMP2);
2079                         if (iptr->op1 == 0) {
2080                                 gen_nullptr_check(s1);
2081                                 gen_bound_check;
2082                         }
2083                         if (has_ext_instr_set) {
2084                                 M_LADD(s2, s1, REG_ITMP1);
2085                                 M_BST(REG_ZERO, REG_ITMP1, OFFSET(java_bytearray, data[0]));
2086
2087                         } else {
2088                                 M_LADD(s2, s1, REG_ITMP1);
2089                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_bytearray, data[0]));
2090                                 M_LDA(REG_ITMP1, REG_ITMP1, OFFSET(java_bytearray, data[0]));
2091                                 M_INSBL(REG_ZERO, REG_ITMP1, REG_ITMP3);
2092                                 M_MSKBL(REG_ITMP2, REG_ITMP1, REG_ITMP2);
2093                                 M_OR(REG_ITMP2, REG_ITMP3, REG_ITMP2);
2094                                 M_LST_U(REG_ITMP2, REG_ITMP1, 0);
2095                         }
2096                         break;
2097
2098                 case ICMD_CASTORECONST:   /* ..., arrayref, index  ==> ...            */
2099
2100                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2101                         var_to_reg_int(s2, src, REG_ITMP2);
2102                         if (iptr->op1 == 0) {
2103                                 gen_nullptr_check(s1);
2104                                 gen_bound_check;
2105                         }
2106                         if (has_ext_instr_set) {
2107                                 M_LADD(s2, s1, REG_ITMP1);
2108                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
2109                                 M_SST(REG_ZERO, REG_ITMP1, OFFSET(java_chararray, data[0]));
2110
2111                         } else {
2112                                 M_LADD(s2, s1, REG_ITMP1);
2113                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
2114                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_chararray, data[0]));
2115                                 M_LDA(REG_ITMP1, REG_ITMP1, OFFSET(java_chararray, data[0]));
2116                                 M_INSWL(REG_ZERO, REG_ITMP1, REG_ITMP3);
2117                                 M_MSKWL(REG_ITMP2, REG_ITMP1, REG_ITMP2);
2118                                 M_OR(REG_ITMP2, REG_ITMP3, REG_ITMP2);
2119                                 M_LST_U(REG_ITMP2, REG_ITMP1, 0);
2120                         }
2121                         break;
2122
2123                 case ICMD_SASTORECONST:   /* ..., arrayref, index  ==> ...            */
2124
2125                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2126                         var_to_reg_int(s2, src, REG_ITMP2);
2127                         if (iptr->op1 == 0) {
2128                                 gen_nullptr_check(s1);
2129                                 gen_bound_check;
2130                         }
2131                         if (has_ext_instr_set) {
2132                                 M_LADD(s2, s1, REG_ITMP1);
2133                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
2134                                 M_SST(REG_ZERO, REG_ITMP1, OFFSET(java_shortarray, data[0]));
2135
2136                         } else {
2137                                 M_LADD(s2, s1, REG_ITMP1);
2138                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
2139                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_shortarray, data[0]));
2140                                 M_LDA(REG_ITMP1, REG_ITMP1, OFFSET(java_shortarray, data[0]));
2141                                 M_INSWL(REG_ZERO, REG_ITMP1, REG_ITMP3);
2142                                 M_MSKWL(REG_ITMP2, REG_ITMP1, REG_ITMP2);
2143                                 M_OR(REG_ITMP2, REG_ITMP3, REG_ITMP2);
2144                                 M_LST_U(REG_ITMP2, REG_ITMP1, 0);
2145                         }
2146                         break;
2147
2148
2149                 case ICMD_GETSTATIC:  /* ...  ==> ..., value                          */
2150                                       /* op1 = type, val.a = field address            */
2151
2152                         if (!iptr->val.a) {
2153                                 codegen_addpatchref(cd, mcodeptr,
2154                                                                         PATCHER_get_putstatic,
2155                                                                         (unresolved_field *) iptr->target);
2156
2157                                 if (showdisassemble)
2158                                         M_NOP;
2159
2160                                 a = 0;
2161
2162                         } else {
2163                                 fieldinfo *fi = iptr->val.a;
2164
2165                                 if (!fi->class->initialized) {
2166                                         codegen_addpatchref(cd, mcodeptr,
2167                                                                                 PATCHER_clinit, fi->class);
2168
2169                                         if (showdisassemble)
2170                                                 M_NOP;
2171                                 }
2172
2173                                 a = (ptrint) &(fi->value);
2174                         }
2175
2176                         a = dseg_addaddress(cd, a);
2177                         M_ALD(REG_ITMP1, REG_PV, a);
2178                         switch (iptr->op1) {
2179                         case TYPE_INT:
2180                                 d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2181                                 M_ILD(d, REG_ITMP1, 0);
2182                                 store_reg_to_var_int(iptr->dst, d);
2183                                 break;
2184                         case TYPE_LNG:
2185                                 d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2186                                 M_LLD(d, REG_ITMP1, 0);
2187                                 store_reg_to_var_int(iptr->dst, d);
2188                                 break;
2189                         case TYPE_ADR:
2190                                 d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2191                                 M_ALD(d, REG_ITMP1, 0);
2192                                 store_reg_to_var_int(iptr->dst, d);
2193                                 break;
2194                         case TYPE_FLT:
2195                                 d = reg_of_var(rd, iptr->dst, REG_FTMP1);
2196                                 M_FLD(d, REG_ITMP1, 0);
2197                                 store_reg_to_var_flt(iptr->dst, d);
2198                                 break;
2199                         case TYPE_DBL:
2200                                 d = reg_of_var(rd, iptr->dst, REG_FTMP1);
2201                                 M_DLD(d, REG_ITMP1, 0);
2202                                 store_reg_to_var_flt(iptr->dst, d);
2203                                 break;
2204                         }
2205                         break;
2206
2207                 case ICMD_PUTSTATIC:  /* ..., value  ==> ...                          */
2208                                       /* op1 = type, val.a = field address            */
2209
2210                         if (!iptr->val.a) {
2211                                 codegen_addpatchref(cd, mcodeptr,
2212                                                                         PATCHER_get_putstatic,
2213                                                                         (unresolved_field *) iptr->target);
2214
2215                                 if (showdisassemble)
2216                                         M_NOP;
2217
2218                                 a = 0;
2219
2220                         } else {
2221                                 fieldinfo *fi = iptr->val.a;
2222
2223                                 if (!fi->class->initialized) {
2224                                         codegen_addpatchref(cd, mcodeptr,
2225                                                                                 PATCHER_clinit, fi->class);
2226
2227                                         if (showdisassemble)
2228                                                 M_NOP;
2229                                 }
2230
2231                                 a = (ptrint) &(fi->value);
2232                         }
2233
2234                         a = dseg_addaddress(cd, a);
2235                         M_ALD(REG_ITMP1, REG_PV, a);
2236                         switch (iptr->op1) {
2237                         case TYPE_INT:
2238                                 var_to_reg_int(s2, src, REG_ITMP2);
2239                                 M_IST(s2, REG_ITMP1, 0);
2240                                 break;
2241                         case TYPE_LNG:
2242                                 var_to_reg_int(s2, src, REG_ITMP2);
2243                                 M_LST(s2, REG_ITMP1, 0);
2244                                 break;
2245                         case TYPE_ADR:
2246                                 var_to_reg_int(s2, src, REG_ITMP2);
2247                                 M_AST(s2, REG_ITMP1, 0);
2248                                 break;
2249                         case TYPE_FLT:
2250                                 var_to_reg_flt(s2, src, REG_FTMP2);
2251                                 M_FST(s2, REG_ITMP1, 0);
2252                                 break;
2253                         case TYPE_DBL:
2254                                 var_to_reg_flt(s2, src, REG_FTMP2);
2255                                 M_DST(s2, REG_ITMP1, 0);
2256                                 break;
2257                         }
2258                         break;
2259
2260                 case ICMD_PUTSTATICCONST: /* ...  ==> ...                             */
2261                                           /* val = value (in current instruction)     */
2262                                           /* op1 = type, val.a = field address (in    */
2263                                           /* following NOP)                           */
2264
2265                         if (!iptr[1].val.a) {
2266                                 codegen_addpatchref(cd, mcodeptr,
2267                                                                         PATCHER_get_putstatic,
2268                                                                         (unresolved_field *) iptr[1].target);
2269
2270                                 if (showdisassemble)
2271                                         M_NOP;
2272
2273                                 a = 0;
2274
2275                         } else {
2276                                 fieldinfo *fi = iptr[1].val.a;
2277
2278                                 if (!fi->class->initialized) {
2279                                         codegen_addpatchref(cd, mcodeptr,
2280                                                                                 PATCHER_clinit, fi->class);
2281
2282                                         if (showdisassemble)
2283                                                 M_NOP;
2284                                 }
2285
2286                                 a = (ptrint) &(fi->value);
2287                         }
2288
2289                         a = dseg_addaddress(cd, a);
2290                         M_ALD(REG_ITMP1, REG_PV, a);
2291                         switch (iptr->op1) {
2292                         case TYPE_INT:
2293                                 M_IST(REG_ZERO, REG_ITMP1, 0);
2294                                 break;
2295                         case TYPE_LNG:
2296                                 M_LST(REG_ZERO, REG_ITMP1, 0);
2297                                 break;
2298                         case TYPE_ADR:
2299                                 M_AST(REG_ZERO, REG_ITMP1, 0);
2300                                 break;
2301                         case TYPE_FLT:
2302                                 M_FST(REG_ZERO, REG_ITMP1, 0);
2303                                 break;
2304                         case TYPE_DBL:
2305                                 M_DST(REG_ZERO, REG_ITMP1, 0);
2306                                 break;
2307                         }
2308                         break;
2309
2310
2311                 case ICMD_GETFIELD:   /* ...  ==> ..., value                          */
2312                                       /* op1 = type, val.i = field offset             */
2313
2314                         var_to_reg_int(s1, src, REG_ITMP1);
2315                         gen_nullptr_check(s1);
2316
2317                         if (!iptr->val.a) {
2318                                 codegen_addpatchref(cd, mcodeptr,
2319                                                                         PATCHER_get_putfield,
2320                                                                         (unresolved_field *) iptr->target);
2321
2322                                 if (showdisassemble)
2323                                         M_NOP;
2324
2325                                 a = 0;
2326
2327                         } else {
2328                                 a = ((fieldinfo *) (iptr->val.a))->offset;
2329                         }
2330
2331                         switch (iptr->op1) {
2332                         case TYPE_INT:
2333                                 d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2334                                 M_ILD(d, s1, a);
2335                                 store_reg_to_var_int(iptr->dst, d);
2336                                 break;
2337                         case TYPE_LNG:
2338                                 d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2339                                 M_LLD(d, s1, a);
2340                                 store_reg_to_var_int(iptr->dst, d);
2341                                 break;
2342                         case TYPE_ADR:
2343                                 d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2344                                 M_ALD(d, s1, a);
2345                                 store_reg_to_var_int(iptr->dst, d);
2346                                 break;
2347                         case TYPE_FLT:
2348                                 d = reg_of_var(rd, iptr->dst, REG_FTMP3);
2349                                 M_FLD(d, s1, a);
2350                                 store_reg_to_var_flt(iptr->dst, d);
2351                                 break;
2352                         case TYPE_DBL:
2353                                 d = reg_of_var(rd, iptr->dst, REG_FTMP3);
2354                                 M_DLD(d, s1, a);
2355                                 store_reg_to_var_flt(iptr->dst, d);
2356                                 break;
2357                         }
2358                         break;
2359
2360                 case ICMD_PUTFIELD:   /* ..., objectref, value  ==> ...               */
2361                                       /* op1 = type, val.a = field address            */
2362
2363                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2364                         gen_nullptr_check(s1);
2365
2366                         if (!IS_FLT_DBL_TYPE(iptr->op1)) {
2367                                 var_to_reg_int(s2, src, REG_ITMP2);
2368                         } else {
2369                                 var_to_reg_flt(s2, src, REG_FTMP2);
2370                         }
2371
2372                         if (!iptr->val.a) {
2373                                 codegen_addpatchref(cd, mcodeptr,
2374                                                                         PATCHER_get_putfield,
2375                                                                         (unresolved_field *) iptr->target);
2376
2377                                 if (showdisassemble)
2378                                         M_NOP;
2379
2380                                 a = 0;
2381
2382                         } else {
2383                                 a = ((fieldinfo *) (iptr->val.a))->offset;
2384                         }
2385
2386                         switch (iptr->op1) {
2387                         case TYPE_INT:
2388                                 M_IST(s2, s1, a);
2389                                 break;
2390                         case TYPE_LNG:
2391                                 M_LST(s2, s1, a);
2392                                 break;
2393                         case TYPE_ADR:
2394                                 M_AST(s2, s1, a);
2395                                 break;
2396                         case TYPE_FLT:
2397                                 M_FST(s2, s1, a);
2398                                 break;
2399                         case TYPE_DBL:
2400                                 M_DST(s2, s1, a);
2401                                 break;
2402                         }
2403                         break;
2404
2405                 case ICMD_PUTFIELDCONST:  /* ..., objectref  ==> ...                  */
2406                                           /* val = value (in current instruction)     */
2407                                           /* op1 = type, val.a = field address (in    */
2408                                           /* following NOP)                           */
2409
2410                         var_to_reg_int(s1, src, REG_ITMP1);
2411                         gen_nullptr_check(s1);
2412
2413                         if (!iptr[1].val.a) {
2414                                 codegen_addpatchref(cd, mcodeptr,
2415                                                                         PATCHER_get_putfield,
2416                                                                         (unresolved_field *) iptr[1].target);
2417
2418                                 if (showdisassemble)
2419                                         M_NOP;
2420
2421                                 a = 0;
2422
2423                         } else {
2424                                 a = ((fieldinfo *) (iptr[1].val.a))->offset;
2425                         }
2426
2427                         switch (iptr[1].op1) {
2428                         case TYPE_INT:
2429                                 M_IST(REG_ZERO, s1, a);
2430                                 break;
2431                         case TYPE_LNG:
2432                                 M_LST(REG_ZERO, s1, a);
2433                                 break;
2434                         case TYPE_ADR:
2435                                 M_AST(REG_ZERO, s1, a);
2436                                 break;
2437                         case TYPE_FLT:
2438                                 M_FST(REG_ZERO, s1, a);
2439                                 break;
2440                         case TYPE_DBL:
2441                                 M_DST(REG_ZERO, s1, a);
2442                                 break;
2443                         }
2444                         break;
2445
2446
2447                 /* branch operations **************************************************/
2448
2449                 case ICMD_ATHROW:       /* ..., objectref ==> ... (, objectref)       */
2450
2451                         var_to_reg_int(s1, src, REG_ITMP1);
2452                         M_INTMOVE(s1, REG_ITMP1_XPTR);
2453                         a = dseg_addaddress(cd, asm_handle_exception);
2454                         M_ALD(REG_ITMP2, REG_PV, a);
2455                         M_JMP(REG_ITMP2_XPC, REG_ITMP2);
2456                         M_NOP;              /* nop ensures that XPC is less than the end */
2457                                             /* of basic block                            */
2458                         ALIGNCODENOP;
2459                         break;
2460
2461                 case ICMD_GOTO:         /* ... ==> ...                                */
2462                                         /* op1 = target JavaVM pc                     */
2463                         M_BR(0);
2464                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2465                         ALIGNCODENOP;
2466                         break;
2467
2468                 case ICMD_JSR:          /* ... ==> ...                                */
2469                                         /* op1 = target JavaVM pc                     */
2470
2471                         M_BSR(REG_ITMP1, 0);
2472                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2473                         break;
2474
2475                 case ICMD_RET:          /* ... ==> ...                                */
2476                                         /* op1 = local variable                       */
2477
2478                         var = &(rd->locals[iptr->op1][TYPE_ADR]);
2479                         if (var->flags & INMEMORY) {
2480                                 M_ALD(REG_ITMP1, REG_SP, 8 * var->regoff);
2481                                 M_RET(REG_ZERO, REG_ITMP1);
2482                                 }
2483                         else
2484                                 M_RET(REG_ZERO, var->regoff);
2485                         ALIGNCODENOP;
2486                         break;
2487
2488                 case ICMD_IFNULL:       /* ..., value ==> ...                         */
2489                                         /* op1 = target JavaVM pc                     */
2490
2491                         var_to_reg_int(s1, src, REG_ITMP1);
2492                         M_BEQZ(s1, 0);
2493                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2494                         break;
2495
2496                 case ICMD_IFNONNULL:    /* ..., value ==> ...                         */
2497                                         /* op1 = target JavaVM pc                     */
2498
2499                         var_to_reg_int(s1, src, REG_ITMP1);
2500                         M_BNEZ(s1, 0);
2501                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2502                         break;
2503
2504                 case ICMD_IFEQ:         /* ..., value ==> ...                         */
2505                                         /* op1 = target JavaVM pc, val.i = constant   */
2506
2507                         var_to_reg_int(s1, src, REG_ITMP1);
2508                         if (iptr->val.i == 0) {
2509                                 M_BEQZ(s1, 0);
2510                                 }
2511                         else {
2512                                 if ((iptr->val.i > 0) && (iptr->val.i <= 255)) {
2513                                         M_CMPEQ_IMM(s1, iptr->val.i, REG_ITMP1);
2514                                         }
2515                                 else {
2516                                         ICONST(REG_ITMP2, iptr->val.i);
2517                                         M_CMPEQ(s1, REG_ITMP2, REG_ITMP1);
2518                                         }
2519                                 M_BNEZ(REG_ITMP1, 0);
2520                                 }
2521                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2522                         break;
2523
2524                 case ICMD_IFLT:         /* ..., value ==> ...                         */
2525                                         /* op1 = target JavaVM pc, val.i = constant   */
2526
2527                         var_to_reg_int(s1, src, REG_ITMP1);
2528                         if (iptr->val.i == 0) {
2529                                 M_BLTZ(s1, 0);
2530                                 }
2531                         else {
2532                                 if ((iptr->val.i > 0) && (iptr->val.i <= 255)) {
2533                                         M_CMPLT_IMM(s1, iptr->val.i, REG_ITMP1);
2534                                         }
2535                                 else {
2536                                         ICONST(REG_ITMP2, iptr->val.i);
2537                                         M_CMPLT(s1, REG_ITMP2, REG_ITMP1);
2538                                         }
2539                                 M_BNEZ(REG_ITMP1, 0);
2540                                 }
2541                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2542                         break;
2543
2544                 case ICMD_IFLE:         /* ..., value ==> ...                         */
2545                                         /* op1 = target JavaVM pc, val.i = constant   */
2546
2547                         var_to_reg_int(s1, src, REG_ITMP1);
2548                         if (iptr->val.i == 0) {
2549                                 M_BLEZ(s1, 0);
2550                                 }
2551                         else {
2552                                 if ((iptr->val.i > 0) && (iptr->val.i <= 255)) {
2553                                         M_CMPLE_IMM(s1, iptr->val.i, REG_ITMP1);
2554                                         }
2555                                 else {
2556                                         ICONST(REG_ITMP2, iptr->val.i);
2557                                         M_CMPLE(s1, REG_ITMP2, REG_ITMP1);
2558                                         }
2559                                 M_BNEZ(REG_ITMP1, 0);
2560                                 }
2561                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2562                         break;
2563
2564                 case ICMD_IFNE:         /* ..., value ==> ...                         */
2565                                         /* op1 = target JavaVM pc, val.i = constant   */
2566
2567                         var_to_reg_int(s1, src, REG_ITMP1);
2568                         if (iptr->val.i == 0) {
2569                                 M_BNEZ(s1, 0);
2570                                 }
2571                         else {
2572                                 if ((iptr->val.i > 0) && (iptr->val.i <= 255)) {
2573                                         M_CMPEQ_IMM(s1, iptr->val.i, REG_ITMP1);
2574                                         }
2575                                 else {
2576                                         ICONST(REG_ITMP2, iptr->val.i);
2577                                         M_CMPEQ(s1, REG_ITMP2, REG_ITMP1);
2578                                         }
2579                                 M_BEQZ(REG_ITMP1, 0);
2580                                 }
2581                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2582                         break;
2583
2584                 case ICMD_IFGT:         /* ..., value ==> ...                         */
2585                                         /* op1 = target JavaVM pc, val.i = constant   */
2586
2587                         var_to_reg_int(s1, src, REG_ITMP1);
2588                         if (iptr->val.i == 0) {
2589                                 M_BGTZ(s1, 0);
2590                                 }
2591                         else {
2592                                 if ((iptr->val.i > 0) && (iptr->val.i <= 255)) {
2593                                         M_CMPLE_IMM(s1, iptr->val.i, REG_ITMP1);
2594                                         }
2595                                 else {
2596                                         ICONST(REG_ITMP2, iptr->val.i);
2597                                         M_CMPLE(s1, REG_ITMP2, REG_ITMP1);
2598                                         }
2599                                 M_BEQZ(REG_ITMP1, 0);
2600                                 }
2601                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2602                         break;
2603
2604                 case ICMD_IFGE:         /* ..., value ==> ...                         */
2605                                         /* op1 = target JavaVM pc, val.i = constant   */
2606
2607                         var_to_reg_int(s1, src, REG_ITMP1);
2608                         if (iptr->val.i == 0) {
2609                                 M_BGEZ(s1, 0);
2610                                 }
2611                         else {
2612                                 if ((iptr->val.i > 0) && (iptr->val.i <= 255)) {
2613                                         M_CMPLT_IMM(s1, iptr->val.i, REG_ITMP1);
2614                                         }
2615                                 else {
2616                                         ICONST(REG_ITMP2, iptr->val.i);
2617                                         M_CMPLT(s1, REG_ITMP2, REG_ITMP1);
2618                                         }
2619                                 M_BEQZ(REG_ITMP1, 0);
2620                                 }
2621                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2622                         break;
2623
2624                 case ICMD_IF_LEQ:       /* ..., value ==> ...                         */
2625                                         /* op1 = target JavaVM pc, val.l = constant   */
2626
2627                         var_to_reg_int(s1, src, REG_ITMP1);
2628                         if (iptr->val.l == 0) {
2629                                 M_BEQZ(s1, 0);
2630                                 }
2631                         else {
2632                                 if ((iptr->val.l > 0) && (iptr->val.l <= 255)) {
2633                                         M_CMPEQ_IMM(s1, iptr->val.l, REG_ITMP1);
2634                                         }
2635                                 else {
2636                                         LCONST(REG_ITMP2, iptr->val.l);
2637                                         M_CMPEQ(s1, REG_ITMP2, REG_ITMP1);
2638                                         }
2639                                 M_BNEZ(REG_ITMP1, 0);
2640                                 }
2641                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2642                         break;
2643
2644                 case ICMD_IF_LLT:       /* ..., value ==> ...                         */
2645                                         /* op1 = target JavaVM pc, val.l = constant   */
2646
2647                         var_to_reg_int(s1, src, REG_ITMP1);
2648                         if (iptr->val.l == 0) {
2649                                 M_BLTZ(s1, 0);
2650                                 }
2651                         else {
2652                                 if ((iptr->val.l > 0) && (iptr->val.l <= 255)) {
2653                                         M_CMPLT_IMM(s1, iptr->val.l, REG_ITMP1);
2654                                         }
2655                                 else {
2656                                         LCONST(REG_ITMP2, iptr->val.l);
2657                                         M_CMPLT(s1, REG_ITMP2, REG_ITMP1);
2658                                         }
2659                                 M_BNEZ(REG_ITMP1, 0);
2660                                 }
2661                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2662                         break;
2663
2664                 case ICMD_IF_LLE:       /* ..., value ==> ...                         */
2665                                         /* op1 = target JavaVM pc, val.l = constant   */
2666
2667                         var_to_reg_int(s1, src, REG_ITMP1);
2668                         if (iptr->val.l == 0) {
2669                                 M_BLEZ(s1, 0);
2670                                 }
2671                         else {
2672                                 if ((iptr->val.l > 0) && (iptr->val.l <= 255)) {
2673                                         M_CMPLE_IMM(s1, iptr->val.l, REG_ITMP1);
2674                                         }
2675                                 else {
2676                                         LCONST(REG_ITMP2, iptr->val.l);
2677                                         M_CMPLE(s1, REG_ITMP2, REG_ITMP1);
2678                                         }
2679                                 M_BNEZ(REG_ITMP1, 0);
2680                                 }
2681                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2682                         break;
2683
2684                 case ICMD_IF_LNE:       /* ..., value ==> ...                         */
2685                                         /* op1 = target JavaVM pc, val.l = constant   */
2686
2687                         var_to_reg_int(s1, src, REG_ITMP1);
2688                         if (iptr->val.l == 0) {
2689                                 M_BNEZ(s1, 0);
2690                                 }
2691                         else {
2692                                 if ((iptr->val.l > 0) && (iptr->val.l <= 255)) {
2693                                         M_CMPEQ_IMM(s1, iptr->val.l, REG_ITMP1);
2694                                         }
2695                                 else {
2696                                         LCONST(REG_ITMP2, iptr->val.l);
2697                                         M_CMPEQ(s1, REG_ITMP2, REG_ITMP1);
2698                                         }
2699                                 M_BEQZ(REG_ITMP1, 0);
2700                                 }
2701                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2702                         break;
2703
2704                 case ICMD_IF_LGT:       /* ..., value ==> ...                         */
2705                                         /* op1 = target JavaVM pc, val.l = constant   */
2706
2707                         var_to_reg_int(s1, src, REG_ITMP1);
2708                         if (iptr->val.l == 0) {
2709                                 M_BGTZ(s1, 0);
2710                                 }
2711                         else {
2712                                 if ((iptr->val.l > 0) && (iptr->val.l <= 255)) {
2713                                         M_CMPLE_IMM(s1, iptr->val.l, REG_ITMP1);
2714                                         }
2715                                 else {
2716                                         LCONST(REG_ITMP2, iptr->val.l);
2717                                         M_CMPLE(s1, REG_ITMP2, REG_ITMP1);
2718                                         }
2719                                 M_BEQZ(REG_ITMP1, 0);
2720                                 }
2721                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2722                         break;
2723
2724                 case ICMD_IF_LGE:       /* ..., value ==> ...                         */
2725                                         /* op1 = target JavaVM pc, val.l = constant   */
2726
2727                         var_to_reg_int(s1, src, REG_ITMP1);
2728                         if (iptr->val.l == 0) {
2729                                 M_BGEZ(s1, 0);
2730                                 }
2731                         else {
2732                                 if ((iptr->val.l > 0) && (iptr->val.l <= 255)) {
2733                                         M_CMPLT_IMM(s1, iptr->val.l, REG_ITMP1);
2734                                         }
2735                                 else {
2736                                         LCONST(REG_ITMP2, iptr->val.l);
2737                                         M_CMPLT(s1, REG_ITMP2, REG_ITMP1);
2738                                         }
2739                                 M_BEQZ(REG_ITMP1, 0);
2740                                 }
2741                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2742                         break;
2743
2744                 case ICMD_IF_ICMPEQ:    /* ..., value, value ==> ...                  */
2745                 case ICMD_IF_LCMPEQ:    /* op1 = target JavaVM pc                     */
2746                 case ICMD_IF_ACMPEQ:
2747
2748                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2749                         var_to_reg_int(s2, src, REG_ITMP2);
2750                         M_CMPEQ(s1, s2, REG_ITMP1);
2751                         M_BNEZ(REG_ITMP1, 0);
2752                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2753                         break;
2754
2755                 case ICMD_IF_ICMPNE:    /* ..., value, value ==> ...                  */
2756                 case ICMD_IF_LCMPNE:    /* op1 = target JavaVM pc                     */
2757                 case ICMD_IF_ACMPNE:
2758
2759                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2760                         var_to_reg_int(s2, src, REG_ITMP2);
2761                         M_CMPEQ(s1, s2, REG_ITMP1);
2762                         M_BEQZ(REG_ITMP1, 0);
2763                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2764                         break;
2765
2766                 case ICMD_IF_ICMPLT:    /* ..., value, value ==> ...                  */
2767                 case ICMD_IF_LCMPLT:    /* op1 = target JavaVM pc                     */
2768
2769                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2770                         var_to_reg_int(s2, src, REG_ITMP2);
2771                         M_CMPLT(s1, s2, REG_ITMP1);
2772                         M_BNEZ(REG_ITMP1, 0);
2773                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2774                         break;
2775
2776                 case ICMD_IF_ICMPGT:    /* ..., value, value ==> ...                  */
2777                 case ICMD_IF_LCMPGT:    /* op1 = target JavaVM pc                     */
2778
2779                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2780                         var_to_reg_int(s2, src, REG_ITMP2);
2781                         M_CMPLE(s1, s2, REG_ITMP1);
2782                         M_BEQZ(REG_ITMP1, 0);
2783                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2784                         break;
2785
2786                 case ICMD_IF_ICMPLE:    /* ..., value, value ==> ...                  */
2787                 case ICMD_IF_LCMPLE:    /* op1 = target JavaVM pc                     */
2788
2789                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2790                         var_to_reg_int(s2, src, REG_ITMP2);
2791                         M_CMPLE(s1, s2, REG_ITMP1);
2792                         M_BNEZ(REG_ITMP1, 0);
2793                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2794                         break;
2795
2796                 case ICMD_IF_ICMPGE:    /* ..., value, value ==> ...                  */
2797                 case ICMD_IF_LCMPGE:    /* op1 = target JavaVM pc                     */
2798
2799                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2800                         var_to_reg_int(s2, src, REG_ITMP2);
2801                         M_CMPLT(s1, s2, REG_ITMP1);
2802                         M_BEQZ(REG_ITMP1, 0);
2803                         codegen_addreference(cd, BlockPtrOfPC(iptr->op1), mcodeptr);
2804                         break;
2805
2806                 /* (value xx 0) ? IFxx_ICONST : ELSE_ICONST                           */
2807
2808                 case ICMD_ELSE_ICONST:  /* handled by IFxx_ICONST                     */
2809                         break;
2810
2811                 case ICMD_IFEQ_ICONST:  /* ..., value ==> ..., constant               */
2812                                         /* val.i = constant                           */
2813
2814                         var_to_reg_int(s1, src, REG_ITMP1);
2815                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2816                         s3 = iptr->val.i;
2817                         if (iptr[1].opc == ICMD_ELSE_ICONST) {
2818                                 if ((s3 == 1) && (iptr[1].val.i == 0)) {
2819                                         M_CMPEQ(s1, REG_ZERO, d);
2820                                         store_reg_to_var_int(iptr->dst, d);
2821                                         break;
2822                                         }
2823                                 if ((s3 == 0) && (iptr[1].val.i == 1)) {
2824                                         M_CMPEQ(s1, REG_ZERO, d);
2825                                         M_XOR_IMM(d, 1, d);
2826                                         store_reg_to_var_int(iptr->dst, d);
2827                                         break;
2828                                         }
2829                                 if (s1 == d) {
2830                                         M_MOV(s1, REG_ITMP1);
2831                                         s1 = REG_ITMP1;
2832                                         }
2833                                 ICONST(d, iptr[1].val.i);
2834                                 }
2835                         if ((s3 >= 0) && (s3 <= 255)) {
2836                                 M_CMOVEQ_IMM(s1, s3, d);
2837                                 }
2838                         else {
2839                                 ICONST(REG_ITMP2, s3);
2840                                 M_CMOVEQ(s1, REG_ITMP2, d);
2841                                 }
2842                         store_reg_to_var_int(iptr->dst, d);
2843                         break;
2844
2845                 case ICMD_IFNE_ICONST:  /* ..., value ==> ..., constant               */
2846                                         /* val.i = constant                           */
2847
2848                         var_to_reg_int(s1, src, REG_ITMP1);
2849                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2850                         s3 = iptr->val.i;
2851                         if (iptr[1].opc == ICMD_ELSE_ICONST) {
2852                                 if ((s3 == 0) && (iptr[1].val.i == 1)) {
2853                                         M_CMPEQ(s1, REG_ZERO, d);
2854                                         store_reg_to_var_int(iptr->dst, d);
2855                                         break;
2856                                         }
2857                                 if ((s3 == 1) && (iptr[1].val.i == 0)) {
2858                                         M_CMPEQ(s1, REG_ZERO, d);
2859                                         M_XOR_IMM(d, 1, d);
2860                                         store_reg_to_var_int(iptr->dst, d);
2861                                         break;
2862                                         }
2863                                 if (s1 == d) {
2864                                         M_MOV(s1, REG_ITMP1);
2865                                         s1 = REG_ITMP1;
2866                                         }
2867                                 ICONST(d, iptr[1].val.i);
2868                                 }
2869                         if ((s3 >= 0) && (s3 <= 255)) {
2870                                 M_CMOVNE_IMM(s1, s3, d);
2871                                 }
2872                         else {
2873                                 ICONST(REG_ITMP2, s3);
2874                                 M_CMOVNE(s1, REG_ITMP2, d);
2875                                 }
2876                         store_reg_to_var_int(iptr->dst, d);
2877                         break;
2878
2879                 case ICMD_IFLT_ICONST:  /* ..., value ==> ..., constant               */
2880                                         /* val.i = constant                           */
2881
2882                         var_to_reg_int(s1, src, REG_ITMP1);
2883                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2884                         s3 = iptr->val.i;
2885                         if ((iptr[1].opc == ICMD_ELSE_ICONST)) {
2886                                 if ((s3 == 1) && (iptr[1].val.i == 0)) {
2887                                         M_CMPLT(s1, REG_ZERO, d);
2888                                         store_reg_to_var_int(iptr->dst, d);
2889                                         break;
2890                                         }
2891                                 if ((s3 == 0) && (iptr[1].val.i == 1)) {
2892                                         M_CMPLE(REG_ZERO, s1, d);
2893                                         store_reg_to_var_int(iptr->dst, d);
2894                                         break;
2895                                         }
2896                                 if (s1 == d) {
2897                                         M_MOV(s1, REG_ITMP1);
2898                                         s1 = REG_ITMP1;
2899                                         }
2900                                 ICONST(d, iptr[1].val.i);
2901                                 }
2902                         if ((s3 >= 0) && (s3 <= 255)) {
2903                                 M_CMOVLT_IMM(s1, s3, d);
2904                                 }
2905                         else {
2906                                 ICONST(REG_ITMP2, s3);
2907                                 M_CMOVLT(s1, REG_ITMP2, d);
2908                                 }
2909                         store_reg_to_var_int(iptr->dst, d);
2910                         break;
2911
2912                 case ICMD_IFGE_ICONST:  /* ..., value ==> ..., constant               */
2913                                         /* val.i = constant                           */
2914
2915                         var_to_reg_int(s1, src, REG_ITMP1);
2916                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2917                         s3 = iptr->val.i;
2918                         if ((iptr[1].opc == ICMD_ELSE_ICONST)) {
2919                                 if ((s3 == 1) && (iptr[1].val.i == 0)) {
2920                                         M_CMPLE(REG_ZERO, s1, d);
2921                                         store_reg_to_var_int(iptr->dst, d);
2922                                         break;
2923                                         }
2924                                 if ((s3 == 0) && (iptr[1].val.i == 1)) {
2925                                         M_CMPLT(s1, REG_ZERO, d);
2926                                         store_reg_to_var_int(iptr->dst, d);
2927                                         break;
2928                                         }
2929                                 if (s1 == d) {
2930                                         M_MOV(s1, REG_ITMP1);
2931                                         s1 = REG_ITMP1;
2932                                         }
2933                                 ICONST(d, iptr[1].val.i);
2934                                 }
2935                         if ((s3 >= 0) && (s3 <= 255)) {
2936                                 M_CMOVGE_IMM(s1, s3, d);
2937                                 }
2938                         else {
2939                                 ICONST(REG_ITMP2, s3);
2940                                 M_CMOVGE(s1, REG_ITMP2, d);
2941                                 }
2942                         store_reg_to_var_int(iptr->dst, d);
2943                         break;
2944
2945                 case ICMD_IFGT_ICONST:  /* ..., value ==> ..., constant               */
2946                                         /* val.i = constant                           */
2947
2948                         var_to_reg_int(s1, src, REG_ITMP1);
2949                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2950                         s3 = iptr->val.i;
2951                         if ((iptr[1].opc == ICMD_ELSE_ICONST)) {
2952                                 if ((s3 == 1) && (iptr[1].val.i == 0)) {
2953                                         M_CMPLT(REG_ZERO, s1, d);
2954                                         store_reg_to_var_int(iptr->dst, d);
2955                                         break;
2956                                         }
2957                                 if ((s3 == 0) && (iptr[1].val.i == 1)) {
2958                                         M_CMPLE(s1, REG_ZERO, d);
2959                                         store_reg_to_var_int(iptr->dst, d);
2960                                         break;
2961                                         }
2962                                 if (s1 == d) {
2963                                         M_MOV(s1, REG_ITMP1);
2964                                         s1 = REG_ITMP1;
2965                                         }
2966                                 ICONST(d, iptr[1].val.i);
2967                                 }
2968                         if ((s3 >= 0) && (s3 <= 255)) {
2969                                 M_CMOVGT_IMM(s1, s3, d);
2970                                 }
2971                         else {
2972                                 ICONST(REG_ITMP2, s3);
2973                                 M_CMOVGT(s1, REG_ITMP2, d);
2974                                 }
2975                         store_reg_to_var_int(iptr->dst, d);
2976                         break;
2977
2978                 case ICMD_IFLE_ICONST:  /* ..., value ==> ..., constant               */
2979                                         /* val.i = constant                           */
2980
2981                         var_to_reg_int(s1, src, REG_ITMP1);
2982                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2983                         s3 = iptr->val.i;
2984                         if ((iptr[1].opc == ICMD_ELSE_ICONST)) {
2985                                 if ((s3 == 1) && (iptr[1].val.i == 0)) {
2986                                         M_CMPLE(s1, REG_ZERO, d);
2987                                         store_reg_to_var_int(iptr->dst, d);
2988                                         break;
2989                                         }
2990                                 if ((s3 == 0) && (iptr[1].val.i == 1)) {
2991                                         M_CMPLT(REG_ZERO, s1, d);
2992                                         store_reg_to_var_int(iptr->dst, d);
2993                                         break;
2994                                         }
2995                                 if (s1 == d) {
2996                                         M_MOV(s1, REG_ITMP1);
2997                                         s1 = REG_ITMP1;
2998                                         }
2999                                 ICONST(d, iptr[1].val.i);
3000                                 }
3001                         if ((s3 >= 0) && (s3 <= 255)) {
3002                                 M_CMOVLE_IMM(s1, s3, d);
3003                                 }
3004                         else {
3005                                 ICONST(REG_ITMP2, s3);
3006                                 M_CMOVLE(s1, REG_ITMP2, d);
3007                                 }
3008                         store_reg_to_var_int(iptr->dst, d);
3009                         break;
3010
3011
3012                 case ICMD_IRETURN:      /* ..., retvalue ==> ...                      */
3013                 case ICMD_LRETURN:
3014                 case ICMD_ARETURN:
3015
3016                         var_to_reg_int(s1, src, REG_RESULT);
3017                         M_INTMOVE(s1, REG_RESULT);
3018
3019                         goto nowperformreturn;
3020
3021                 case ICMD_FRETURN:      /* ..., retvalue ==> ...                      */
3022                 case ICMD_DRETURN:
3023
3024                         var_to_reg_flt(s1, src, REG_FRESULT);
3025                         M_FLTMOVE(s1, REG_FRESULT);
3026
3027                         goto nowperformreturn;
3028
3029                 case ICMD_RETURN:       /* ...  ==> ...                               */
3030
3031 nowperformreturn:
3032                         {
3033                         s4 i, p;
3034
3035                         p = parentargs_base;
3036
3037                         /* call trace function */
3038
3039                         if (runverbose) {
3040                                 M_LDA(REG_SP, REG_SP, -3 * 8);
3041                                 M_AST(REG_RA, REG_SP, 0 * 8);
3042                                 M_LST(REG_RESULT, REG_SP, 1 * 8);
3043                                 M_DST(REG_FRESULT, REG_SP, 2 * 8);
3044                                 a = dseg_addaddress(cd, m);
3045                                 M_ALD(rd->argintregs[0], REG_PV, a);
3046                                 M_MOV(REG_RESULT, rd->argintregs[1]);
3047                                 M_FLTMOVE(REG_FRESULT, rd->argfltregs[2]);
3048                                 M_FLTMOVE(REG_FRESULT, rd->argfltregs[3]);
3049                                 a = dseg_addaddress(cd, (void *) builtin_displaymethodstop);
3050                                 M_ALD(REG_PV, REG_PV, a);
3051                                 M_JSR(REG_RA, REG_PV);
3052                                 s1 = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3053                                 if (s1 <= 32768) M_LDA(REG_PV, REG_RA, -s1);
3054                                 else {
3055                                         s4 ml = -s1, mh = 0;
3056                                         while (ml < -32768) { ml += 65536; mh--; }
3057                                         M_LDA(REG_PV, REG_RA, ml);
3058                                         M_LDAH(REG_PV, REG_PV, mh);
3059                                 }
3060                                 M_DLD(REG_FRESULT, REG_SP, 2 * 8);
3061                                 M_LLD(REG_RESULT, REG_SP, 1 * 8);
3062                                 M_ALD(REG_RA, REG_SP, 0 * 8);
3063                                 M_LDA(REG_SP, REG_SP, 3 * 8);
3064                         }
3065
3066 #if defined(USE_THREADS)
3067                         if (checksync && (m->flags & ACC_SYNCHRONIZED)) {
3068                                 s4 disp;
3069
3070                                 M_ALD(rd->argintregs[0], REG_SP, rd->maxmemuse * 8);
3071
3072                                 switch (iptr->opc) {
3073                                 case ICMD_IRETURN:
3074                                 case ICMD_LRETURN:
3075                                 case ICMD_ARETURN:
3076                                         M_LST(REG_RESULT, REG_SP, rd->maxmemuse * 8);
3077                                         break;
3078                                 case ICMD_FRETURN:
3079                                 case ICMD_DRETURN:
3080                                         M_DST(REG_FRESULT, REG_SP, rd->maxmemuse * 8);
3081                                         break;
3082                                 }
3083
3084                                 a = dseg_addaddress(cd, BUILTIN_monitorexit);
3085                                 M_ALD(REG_PV, REG_PV, a);
3086                                 M_JSR(REG_RA, REG_PV);
3087                                 disp = -(s4) ((u1 *) mcodeptr - cd->mcodebase);
3088                                 M_LDA(REG_PV, REG_RA, disp);
3089
3090                                 switch (iptr->opc) {
3091                                 case ICMD_IRETURN:
3092                                 case ICMD_LRETURN:
3093                                 case ICMD_ARETURN:
3094                                         M_LLD(REG_RESULT, REG_SP, rd->maxmemuse * 8);
3095                                         break;
3096                                 case ICMD_FRETURN:
3097                                 case ICMD_DRETURN:
3098                                         M_DLD(REG_FRESULT, REG_SP, rd->maxmemuse * 8);
3099                                         break;
3100                                 }
3101                         }
3102 #endif
3103
3104                         /* restore return address                                         */
3105
3106                         if (!m->isleafmethod) {
3107                                 p--; M_LLD(REG_RA, REG_SP, p * 8);
3108                         }
3109
3110                         /* restore saved registers                                        */
3111
3112                         for (i = rd->savintregcnt - 1; i >= rd->maxsavintreguse; i--) {
3113                                 p--; M_LLD(rd->savintregs[i], REG_SP, p * 8);
3114                         }
3115                         for (i = rd->savfltregcnt - 1; i >= rd->maxsavfltreguse; i--) {
3116                                 p--; M_DLD(rd->savfltregs[i], REG_SP, p * 8);
3117                         }
3118
3119                         /* deallocate stack                                               */
3120
3121                         if (parentargs_base) {
3122                                 M_LDA(REG_SP, REG_SP, parentargs_base * 8);
3123                         }
3124
3125                         M_RET(REG_ZERO, REG_RA);
3126                         ALIGNCODENOP;
3127                         }
3128                         break;
3129
3130
3131                 case ICMD_TABLESWITCH:  /* ..., index ==> ...                         */
3132                         {
3133                         s4 i, l, *s4ptr;
3134                         void **tptr;
3135
3136                         tptr = (void **) iptr->target;
3137
3138                         s4ptr = iptr->val.a;
3139                         l = s4ptr[1];                          /* low     */
3140                         i = s4ptr[2];                          /* high    */
3141
3142                         var_to_reg_int(s1, src, REG_ITMP1);
3143                         if (l == 0)
3144                                 {M_INTMOVE(s1, REG_ITMP1);}
3145                         else if (l <= 32768) {
3146                                 M_LDA(REG_ITMP1, s1, -l);
3147                                 }
3148                         else {
3149                                 ICONST(REG_ITMP2, l);
3150                                 M_ISUB(s1, REG_ITMP2, REG_ITMP1);
3151                                 }
3152                         i = i - l + 1;
3153
3154                         /* range check */
3155
3156                         if (i <= 256)
3157                                 M_CMPULE_IMM(REG_ITMP1, i - 1, REG_ITMP2);
3158                         else {
3159                                 M_LDA(REG_ITMP2, REG_ZERO, i - 1);
3160                                 M_CMPULE(REG_ITMP1, REG_ITMP2, REG_ITMP2);
3161                                 }
3162                         M_BEQZ(REG_ITMP2, 0);
3163
3164
3165                         /* codegen_addreference(cd, BlockPtrOfPC(s4ptr[0]), mcodeptr); */
3166                         codegen_addreference(cd, (basicblock *) tptr[0], mcodeptr);
3167
3168                         /* build jump table top down and use address of lowest entry */
3169
3170                         /* s4ptr += 3 + i; */
3171                         tptr += i;
3172
3173                         while (--i >= 0) {
3174                                 /* dseg_addtarget(cd, BlockPtrOfPC(*--s4ptr)); */
3175                                 dseg_addtarget(cd, (basicblock *) tptr[0]);
3176                                 --tptr;
3177                                 }
3178                         }
3179
3180                         /* length of dataseg after last dseg_addtarget is used by load */
3181
3182                         M_SAADDQ(REG_ITMP1, REG_PV, REG_ITMP2);
3183                         M_ALD(REG_ITMP2, REG_ITMP2, -(cd->dseglen));
3184                         M_JMP(REG_ZERO, REG_ITMP2);
3185                         ALIGNCODENOP;
3186                         break;
3187
3188
3189                 case ICMD_LOOKUPSWITCH: /* ..., key ==> ...                           */
3190                         {
3191                         s4 i, l, val, *s4ptr;
3192                         void **tptr;
3193
3194                         tptr = (void **) iptr->target;
3195
3196                         s4ptr = iptr->val.a;
3197                         l = s4ptr[0];                          /* default  */
3198                         i = s4ptr[1];                          /* count    */
3199
3200                         MCODECHECK((i<<2)+8);
3201                         var_to_reg_int(s1, src, REG_ITMP1);
3202                         while (--i >= 0) {
3203                                 s4ptr += 2;
3204                                 ++tptr;
3205
3206                                 val = s4ptr[0];
3207                                 if ((val >= 0) && (val <= 255)) {
3208                                         M_CMPEQ_IMM(s1, val, REG_ITMP2);
3209                                         }
3210                                 else {
3211                                         if ((val >= -32768) && (val <= 32767)) {
3212                                                 M_LDA(REG_ITMP2, REG_ZERO, val);
3213                                                 }
3214                                         else {
3215                                                 a = dseg_adds4(cd, val);
3216                                                 M_ILD(REG_ITMP2, REG_PV, a);
3217                                                 }
3218                                         M_CMPEQ(s1, REG_ITMP2, REG_ITMP2);
3219                                         }
3220                                 M_BNEZ(REG_ITMP2, 0);
3221                                 /* codegen_addreference(cd, BlockPtrOfPC(s4ptr[1]), mcodeptr); */
3222                                 codegen_addreference(cd, (basicblock *) tptr[0], mcodeptr);
3223                                 }
3224
3225                         M_BR(0);
3226                         /* codegen_addreference(cd, BlockPtrOfPC(l), mcodeptr); */
3227
3228                         tptr = (void **) iptr->target;
3229                         codegen_addreference(cd, (basicblock *) tptr[0], mcodeptr);
3230
3231                         ALIGNCODENOP;
3232                         break;
3233                         }
3234
3235
3236                 case ICMD_BUILTIN3:     /* ..., arg1, arg2, arg3 ==> ...              */
3237                                         /* op1 = return type, val.a = function pointer*/
3238                         s3 = 3;
3239                         goto gen_method;
3240
3241                 case ICMD_BUILTIN2:     /* ..., arg1, arg2 ==> ...                    */
3242                                         /* op1 = return type, val.a = function pointer*/
3243                         s3 = 2;
3244                         goto gen_method;
3245
3246                 case ICMD_BUILTIN1:     /* ..., arg1 ==> ...                          */
3247                                         /* op1 = return type, val.a = function pointer*/
3248                         s3 = 1;
3249                         goto gen_method;
3250
3251                 case ICMD_INVOKESTATIC: /* ..., [arg1, [arg2 ...]] ==> ...            */
3252                                         /* op1 = arg count, val.a = method pointer    */
3253
3254                 case ICMD_INVOKESPECIAL:/* ..., objectref, [arg1, [arg2 ...]] ==> ... */
3255                                         /* op1 = arg count, val.a = method pointer    */
3256
3257                 case ICMD_INVOKEVIRTUAL:/* ..., objectref, [arg1, [arg2 ...]] ==> ... */
3258                                         /* op1 = arg count, val.a = method pointer    */
3259
3260                 case ICMD_INVOKEINTERFACE:/*.., objectref, [arg1, [arg2 ...]] ==> ... */
3261                                         /* op1 = arg count, val.a = method pointer    */
3262
3263                         s3 = iptr->op1;
3264
3265 gen_method: {
3266                         methodinfo *lm;
3267
3268                         MCODECHECK((s3 << 1) + 64);
3269
3270                         /* copy arguments to registers or stack location                  */
3271
3272                         for (; --s3 >= 0; src = src->prev) {
3273                                 if (src->varkind == ARGVAR)
3274                                         continue;
3275                                 if (IS_INT_LNG_TYPE(src->type)) {
3276                                         if (s3 < INT_ARG_CNT) {
3277                                                 s1 = rd->argintregs[s3];
3278                                                 var_to_reg_int(d, src, s1);
3279                                                 M_INTMOVE(d, s1);
3280
3281                                         } else {
3282                                                 var_to_reg_int(d, src, REG_ITMP1);
3283                                                 M_LST(d, REG_SP, 8 * (s3 - INT_ARG_CNT));
3284                                         }
3285
3286                                 } else {
3287                                         if (s3 < FLT_ARG_CNT) {
3288                                                 s1 = rd->argfltregs[s3];
3289                                                 var_to_reg_flt(d, src, s1);
3290                                                 M_FLTMOVE(d, s1);
3291
3292                                         } else {
3293                                                 var_to_reg_flt(d, src, REG_FTMP1);
3294                                                 M_DST(d, REG_SP, 8 * (s3 - FLT_ARG_CNT));
3295                                         }
3296                                 }
3297                         } /* end of for */
3298
3299                         lm = iptr->val.a;
3300                         switch (iptr->opc) {
3301                         case ICMD_BUILTIN3:
3302                         case ICMD_BUILTIN2:
3303                         case ICMD_BUILTIN1:
3304                                 if (iptr->target) {
3305                                         codegen_addpatchref(cd, mcodeptr,
3306                                                                                 (functionptr) lm, iptr->target);
3307
3308                                         if (showdisassemble)
3309                                                 M_NOP;
3310
3311                                         a = 0;
3312
3313                                 } else {
3314                                         a = (ptrint) lm;
3315                                 }
3316
3317                                 a = dseg_addaddress(cd, a);
3318                                 d = iptr->op1;
3319
3320                                 M_ALD(REG_PV, REG_PV, a);     /* Pointer to built-in-function */
3321                                 break;
3322
3323                         case ICMD_INVOKESPECIAL:
3324                                 gen_nullptr_check(rd->argintregs[0]);
3325                                 M_ILD(REG_ITMP1, rd->argintregs[0], 0); /* hardware nullptr   */
3326                                 /* fall through */
3327
3328                         case ICMD_INVOKESTATIC:
3329                                 if (!lm) {
3330                                         unresolved_method *um = iptr->target;
3331
3332                                         codegen_addpatchref(cd, mcodeptr,
3333                                                                                 PATCHER_invokestatic_special, um);
3334
3335                                         if (showdisassemble)
3336                                                 M_NOP;
3337
3338                                         a = 0;
3339                                         d = um->methodref->parseddesc.md->returntype.type;
3340
3341                                 } else {
3342                                         a = (ptrint) lm->stubroutine;
3343                                         d = lm->parseddesc->returntype.type;
3344                                 }
3345
3346                                 a = dseg_addaddress(cd, a);
3347                                 M_ALD(REG_PV, REG_PV, a);            /* method pointer in r27 */
3348                                 break;
3349
3350                         case ICMD_INVOKEVIRTUAL:
3351                                 gen_nullptr_check(rd->argintregs[0]);
3352
3353                                 if (!lm) {
3354                                         unresolved_method *um = iptr->target;
3355
3356                                         codegen_addpatchref(cd, mcodeptr,
3357                                                                                 PATCHER_invokevirtual, um);
3358
3359                                         if (showdisassemble)
3360                                                 M_NOP;
3361
3362                                         s1 = 0;
3363                                         d = um->methodref->parseddesc.md->returntype.type;
3364
3365                                 } else {
3366                                         s1 = OFFSET(vftbl_t, table[0]) +
3367                                                 sizeof(methodptr) * lm->vftblindex;
3368                                         d = lm->parseddesc->returntype.type;
3369                                 }
3370
3371                                 M_ALD(REG_METHODPTR, rd->argintregs[0],
3372                                           OFFSET(java_objectheader, vftbl));
3373                                 M_ALD(REG_PV, REG_METHODPTR, s1);
3374                                 break;
3375
3376                         case ICMD_INVOKEINTERFACE:
3377                                 gen_nullptr_check(rd->argintregs[0]);
3378
3379                                 if (!lm) {
3380                                         unresolved_method *um = iptr->target;
3381
3382                                         codegen_addpatchref(cd, mcodeptr,
3383                                                                                 PATCHER_invokeinterface, um);
3384
3385                                         if (showdisassemble)
3386                                                 M_NOP;
3387
3388                                         s1 = 0;
3389                                         s2 = 0;
3390                                         d = um->methodref->parseddesc.md->returntype.type;
3391
3392                                 } else {
3393                                         s1 = OFFSET(vftbl_t, interfacetable[0]) -
3394                                                 sizeof(methodptr*) * lm->class->index;
3395
3396                                         s2 = sizeof(methodptr) * (lm - lm->class->methods);
3397
3398                                         d = lm->parseddesc->returntype.type;
3399                                 }
3400
3401                                 M_ALD(REG_METHODPTR, rd->argintregs[0],
3402                                           OFFSET(java_objectheader, vftbl));
3403                                 M_ALD(REG_METHODPTR, REG_METHODPTR, s1);
3404                                 M_ALD(REG_PV, REG_METHODPTR, s2);
3405                                 break;
3406                         }
3407
3408                         M_JSR(REG_RA, REG_PV);
3409
3410                         /* recompute pv */
3411
3412                         s1 = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3413                         if (s1 <= 32768) M_LDA(REG_PV, REG_RA, -s1);
3414                         else {
3415                                 s4 ml = -s1, mh = 0;
3416                                 while (ml < -32768) { ml += 65536; mh--; }
3417                                 M_LDA(REG_PV, REG_RA, ml);
3418                                 M_LDAH(REG_PV, REG_PV, mh);
3419                         }
3420
3421                         /* d contains return type */
3422
3423                         if (d != TYPE_VOID) {
3424                                 if (IS_INT_LNG_TYPE(iptr->dst->type)) {
3425                                         s1 = reg_of_var(rd, iptr->dst, REG_RESULT);
3426                                         M_INTMOVE(REG_RESULT, s1);
3427                                         store_reg_to_var_int(iptr->dst, s1);
3428
3429                                 } else {
3430                                         s1 = reg_of_var(rd, iptr->dst, REG_FRESULT);
3431                                         M_FLTMOVE(REG_FRESULT, s1);
3432                                         store_reg_to_var_flt(iptr->dst, s1);
3433                                 }
3434                         }
3435                         }
3436                         break;
3437
3438
3439                 case ICMD_CHECKCAST:  /* ..., objectref ==> ..., objectref            */
3440
3441                                       /* op1:   0 == array, 1 == class                */
3442                                       /* val.a: (classinfo*) superclass               */
3443
3444                         /*  superclass is an interface:
3445                          *
3446                          *  OK if ((sub == NULL) ||
3447                          *         (sub->vftbl->interfacetablelength > super->index) &&
3448                          *         (sub->vftbl->interfacetable[-super->index] != NULL));
3449                          *
3450                          *  superclass is a class:
3451                          *
3452                          *  OK if ((sub == NULL) || (0
3453                          *         <= (sub->vftbl->baseval - super->vftbl->baseval) <=
3454                          *         super->vftbl->diffval));
3455                          */
3456
3457                         {
3458                         classinfo *super;
3459                         vftbl_t   *supervftbl;
3460                         s4         superindex;
3461
3462                         super = (classinfo *) iptr->val.a;
3463
3464                         if (!super) {
3465                                 superindex = 0;
3466                                 supervftbl = NULL;
3467
3468                         } else {
3469                                 superindex = super->index;
3470                                 supervftbl = super->vftbl;
3471                         }
3472
3473 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3474                         codegen_threadcritrestart(cd, (u1 *) mcodeptr - cd->mcodebase);
3475 #endif
3476                         var_to_reg_int(s1, src, REG_ITMP1);
3477
3478                         /* calculate interface checkcast code size */
3479
3480                         s2 = 6;
3481                         if (!super)
3482                                 s2 += showdisassemble ? 1 : 0;
3483
3484                         /* calculate class checkcast code size */
3485
3486                         s3 = 9 /* 8 + (s1 == REG_ITMP1) */;
3487                         if (!super)
3488                                 s3 += showdisassemble ? 1 : 0;
3489
3490                         /* if class is not resolved, check which code to call */
3491
3492                         if (!super) {
3493                                 M_BEQZ(s1, 4 + (showdisassemble ? 1 : 0) + s2 + 1 + s3);
3494
3495                                 codegen_addpatchref(cd, mcodeptr,
3496                                                                         PATCHER_checkcast_instanceof_flags,
3497                                                                         (constant_classref *) iptr->target);
3498
3499                                 if (showdisassemble)
3500                                         M_NOP;
3501
3502                                 a = dseg_adds4(cd, 0); /* super->flags */
3503                                 M_ILD(REG_ITMP2, REG_PV, a);
3504                                 a = dseg_adds4(cd, ACC_INTERFACE);
3505                                 M_ILD(REG_ITMP3, REG_PV, a);
3506                                 M_AND(REG_ITMP2, REG_ITMP3, REG_ITMP2);
3507                                 M_BEQZ(REG_ITMP2, s2 + 1);
3508                         }
3509
3510                         /* interface checkcast code */
3511
3512                         if (!super || (super->flags & ACC_INTERFACE)) {
3513                                 if (super) {
3514                                         M_BEQZ(s1, s2);
3515
3516                                 } else {
3517                                         codegen_addpatchref(cd, mcodeptr,
3518                                                                                 PATCHER_checkcast_instanceof_interface,
3519                                                                                 (constant_classref *) iptr->target);
3520
3521                                         if (showdisassemble)
3522                                                 M_NOP;
3523                                 }
3524
3525                                 M_ALD(REG_ITMP2, s1, OFFSET(java_objectheader, vftbl));
3526                                 M_ILD(REG_ITMP3, REG_ITMP2, OFFSET(vftbl_t, interfacetablelength));
3527                                 M_LDA(REG_ITMP3, REG_ITMP3, -superindex);
3528                                 M_BLEZ(REG_ITMP3, 0);
3529                                 codegen_addxcastrefs(cd, mcodeptr);
3530                                 M_ALD(REG_ITMP3, REG_ITMP2,
3531                                           OFFSET(vftbl_t, interfacetable[0]) -
3532                                           superindex * sizeof(methodptr*));
3533                                 M_BEQZ(REG_ITMP3, 0);
3534                                 codegen_addxcastrefs(cd, mcodeptr);
3535
3536                                 if (!super)
3537                                         M_BR(s3);
3538                         }
3539
3540                         /* class checkcast code */
3541
3542                         if (!super || !(super->flags & ACC_INTERFACE)) {
3543                                 if (super) {
3544                                         M_BEQZ(s1, s3);
3545
3546                                 } else {
3547                                         codegen_addpatchref(cd, mcodeptr,
3548                                                                                 PATCHER_checkcast_instanceof_class,
3549                                                                                 (constant_classref *) iptr->target);
3550
3551                                         if (showdisassemble)
3552                                                 M_NOP;
3553                                 }
3554
3555                                 M_ALD(REG_ITMP2, s1, OFFSET(java_objectheader, vftbl));
3556                                 a = dseg_addaddress(cd, supervftbl);
3557                                 M_ALD(REG_ITMP3, REG_PV, a);
3558 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3559                                 codegen_threadcritstart(cd, (u1 *) mcodeptr - cd->mcodebase);
3560 #endif
3561                                 M_ILD(REG_ITMP2, REG_ITMP2, OFFSET(vftbl_t, baseval));
3562 /*                              if (s1 != REG_ITMP1) { */
3563 /*                                      M_ILD(REG_ITMP1, REG_ITMP3, OFFSET(vftbl_t, baseval)); */
3564 /*                                      M_ILD(REG_ITMP3, REG_ITMP3, OFFSET(vftbl_t, diffval)); */
3565 /*  #if defined(USE_THREADS) && defined(NATIVE_THREADS) */
3566 /*                                      codegen_threadcritstop(cd, (u1 *) mcodeptr - cd->mcodebase); */
3567 /*  #endif */
3568 /*                                      M_ISUB(REG_ITMP2, REG_ITMP1, REG_ITMP2); */
3569
3570 /*                              } else { */
3571                                         M_ILD(REG_ITMP3, REG_ITMP3, OFFSET(vftbl_t, baseval));
3572                                         M_ISUB(REG_ITMP2, REG_ITMP3, REG_ITMP2);
3573                                         M_ALD(REG_ITMP3, REG_PV, a);
3574                                         M_ILD(REG_ITMP3, REG_ITMP3, OFFSET(vftbl_t, diffval));
3575 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3576                                         codegen_threadcritstop(cd, (u1 *) mcodeptr - cd->mcodebase);
3577 #endif
3578 /*                              } */
3579                                 M_CMPULE(REG_ITMP2, REG_ITMP3, REG_ITMP3);
3580                                 M_BEQZ(REG_ITMP3, 0);
3581                                 codegen_addxcastrefs(cd, mcodeptr);
3582                         }
3583                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
3584                         M_INTMOVE(s1, d);
3585                         store_reg_to_var_int(iptr->dst, d);
3586                         }
3587                         break;
3588
3589                 case ICMD_INSTANCEOF: /* ..., objectref ==> ..., intresult            */
3590
3591                                       /* op1:   0 == array, 1 == class                */
3592                                       /* val.a: (classinfo*) superclass               */
3593
3594                         /*  superclass is an interface:
3595                          *
3596                          *  return (sub != NULL) &&
3597                          *         (sub->vftbl->interfacetablelength > super->index) &&
3598                          *         (sub->vftbl->interfacetable[-super->index] != NULL);
3599                          *
3600                          *  superclass is a class:
3601                          *
3602                          *  return ((sub != NULL) && (0
3603                          *          <= (sub->vftbl->baseval - super->vftbl->baseval) <=
3604                          *          super->vftbl->diffvall));
3605                          */
3606
3607                         {
3608                         classinfo *super;
3609                         vftbl_t   *supervftbl;
3610                         s4         superindex;
3611
3612                         super = (classinfo *) iptr->val.a;
3613
3614                         if (!super) {
3615                                 superindex = 0;
3616                                 supervftbl = NULL;
3617
3618                         } else {
3619                                 superindex = super->index;
3620                                 supervftbl = super->vftbl;
3621                         }
3622
3623 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3624                         codegen_threadcritrestart(cd, (u1 *) mcodeptr - cd->mcodebase);
3625 #endif
3626                         var_to_reg_int(s1, src, REG_ITMP1);
3627                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
3628                         if (s1 == d) {
3629                                 M_MOV(s1, REG_ITMP1);
3630                                 s1 = REG_ITMP1;
3631                         }
3632
3633                         /* calculate interface instanceof code size */
3634
3635                         s2 = 6;
3636                         if (!super)
3637                                 s2 += (d == REG_ITMP2 ? 1 : 0) + (showdisassemble ? 1 : 0);
3638
3639                         /* calculate class instanceof code size */
3640
3641                         s3 = 7;
3642                         if (!super)
3643                                 s3 += (showdisassemble ? 1 : 0);
3644
3645                         /* if class is not resolved, check which code to call */
3646
3647                         if (!super) {
3648                                 M_CLR(d);
3649                                 M_BEQZ(s1, 4 + (showdisassemble ? 1 : 0) + s2 + 1 + s3);
3650
3651                                 codegen_addpatchref(cd, mcodeptr,
3652                                                                         PATCHER_checkcast_instanceof_flags,
3653                                                                         (constant_classref *) iptr->target);
3654
3655                                 if (showdisassemble)
3656                                         M_NOP;
3657
3658                                 a = dseg_adds4(cd, 0); /* super->flags */
3659                                 M_ILD(REG_ITMP3, REG_PV, a);
3660                                 a = dseg_adds4(cd, ACC_INTERFACE);
3661                                 M_ILD(REG_ITMP2, REG_PV, a);
3662                                 M_AND(REG_ITMP3, REG_ITMP2, REG_ITMP3);
3663                                 M_BEQZ(REG_ITMP3, s2 + 1);
3664                         }
3665
3666                         /* interface instanceof code */
3667
3668                         if (!super || (super->flags & ACC_INTERFACE)) {
3669                                 if (super) {
3670                                         M_CLR(d);
3671                                         M_BEQZ(s1, s2);
3672
3673                                 } else {
3674                                         /* If d == REG_ITMP2, then it's destroyed in check code   */
3675                                         /* above.                                                 */
3676                                         if (d == REG_ITMP2)
3677                                                 M_CLR(d);
3678
3679                                         codegen_addpatchref(cd, mcodeptr,
3680                                                                                 PATCHER_checkcast_instanceof_interface,
3681                                                                                 (constant_classref *) iptr->target);
3682
3683                                         if (showdisassemble)
3684                                                 M_NOP;
3685                                 }
3686
3687                                 M_ALD(REG_ITMP1, s1, OFFSET(java_objectheader, vftbl));
3688                                 M_ILD(REG_ITMP3, REG_ITMP1, OFFSET(vftbl_t, interfacetablelength));
3689                                 M_LDA(REG_ITMP3, REG_ITMP3, -superindex);
3690                                 M_BLEZ(REG_ITMP3, 2);
3691                                 M_ALD(REG_ITMP1, REG_ITMP1,
3692                                           OFFSET(vftbl_t, interfacetable[0]) -
3693                                           superindex * sizeof(methodptr*));
3694                                 M_CMPULT(REG_ZERO, REG_ITMP1, d);      /* REG_ITMP1 != 0  */
3695
3696                                 if (!super)
3697                                         M_BR(s3);
3698                         }
3699
3700                         /* class instanceof code */
3701
3702                         if (!super || !(super->flags & ACC_INTERFACE)) {
3703                                 if (super) {
3704                                         M_CLR(d);
3705                                         M_BEQZ(s1, s3);
3706
3707                                 } else {
3708                                         codegen_addpatchref(cd, mcodeptr,
3709                                                                                 PATCHER_checkcast_instanceof_class,
3710                                                                                 (constant_classref *) iptr->target);
3711
3712                                         if (showdisassemble)
3713                                                 M_NOP;
3714                                 }
3715
3716                                 M_ALD(REG_ITMP1, s1, OFFSET(java_objectheader, vftbl));
3717                                 a = dseg_addaddress(cd, supervftbl);
3718                                 M_ALD(REG_ITMP2, REG_PV, a);
3719 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3720                                 codegen_threadcritstart(cd, (u1 *) mcodeptr - cd->mcodebase);
3721 #endif
3722                                 M_ILD(REG_ITMP1, REG_ITMP1, OFFSET(vftbl_t, baseval));
3723                                 M_ILD(REG_ITMP3, REG_ITMP2, OFFSET(vftbl_t, baseval));
3724                                 M_ILD(REG_ITMP2, REG_ITMP2, OFFSET(vftbl_t, diffval));
3725 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3726                                 codegen_threadcritstop(cd, (u1 *) mcodeptr - cd->mcodebase);
3727 #endif
3728                                 M_ISUB(REG_ITMP1, REG_ITMP3, REG_ITMP1);
3729                                 M_CMPULE(REG_ITMP1, REG_ITMP2, d);
3730                         }
3731                         store_reg_to_var_int(iptr->dst, d);
3732                         }
3733                         break;
3734
3735
3736                 case ICMD_CHECKASIZE:  /* ..., size ==> ..., size                     */
3737
3738                         var_to_reg_int(s1, src, REG_ITMP1);
3739                         M_BLTZ(s1, 0);
3740                         codegen_addxcheckarefs(cd, mcodeptr);
3741                         break;
3742
3743                 case ICMD_CHECKEXCEPTION:    /* ... ==> ...                           */
3744
3745                         M_BEQZ(REG_RESULT, 0);
3746                         codegen_addxexceptionrefs(cd, mcodeptr);
3747                         break;
3748
3749                 case ICMD_MULTIANEWARRAY:/* ..., cnt1, [cnt2, ...] ==> ..., arrayref  */
3750                                       /* op1 = dimension, val.a = array descriptor    */
3751
3752                         /* check for negative sizes and copy sizes to stack if necessary  */
3753
3754                         MCODECHECK((iptr->op1 << 1) + 64);
3755
3756                         for (s1 = iptr->op1; --s1 >= 0; src = src->prev) {
3757                                 var_to_reg_int(s2, src, REG_ITMP1);
3758                                 M_BLTZ(s2, 0);
3759                                 codegen_addxcheckarefs(cd, mcodeptr);
3760
3761                                 /* copy SAVEDVAR sizes to stack */
3762
3763                                 if (src->varkind != ARGVAR) {
3764                                         M_LST(s2, REG_SP, s1 * 8);
3765                                 }
3766                         }
3767
3768                         /* is patcher function set? */
3769
3770                         if (iptr->target) {
3771                                 codegen_addpatchref(cd, mcodeptr,
3772                                                                         (functionptr) iptr->target, iptr->val.a);
3773
3774                                 if (showdisassemble)
3775                                         M_NOP;
3776
3777                                 a = 0;
3778
3779                         } else {
3780                                 a = (ptrint) iptr->val.a;
3781                         }
3782
3783                         /* a0 = dimension count */
3784
3785                         ICONST(rd->argintregs[0], iptr->op1);
3786
3787                         /* a1 = arraydescriptor */
3788
3789                         a = dseg_addaddress(cd, a);
3790                         M_ALD(rd->argintregs[1], REG_PV, a);
3791
3792                         /* a2 = pointer to dimensions = stack pointer */
3793
3794                         M_INTMOVE(REG_SP, rd->argintregs[2]);
3795
3796                         a = dseg_addaddress(cd, (void *) BUILTIN_multianewarray);
3797                         M_ALD(REG_PV, REG_PV, a);
3798                         M_JSR(REG_RA, REG_PV);
3799                         s1 = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3800                         if (s1 <= 32768)
3801                                 M_LDA(REG_PV, REG_RA, -s1);
3802                         else {
3803                                 s4 ml = -s1, mh = 0;
3804                                 while (ml < -32768) { ml += 65536; mh--; }
3805                                 M_LDA(REG_PV, REG_RA, ml);
3806                                 M_LDAH(REG_PV, REG_PV, mh);
3807                         }
3808                         s1 = reg_of_var(rd, iptr->dst, REG_RESULT);
3809                         M_INTMOVE(REG_RESULT, s1);
3810                         store_reg_to_var_int(iptr->dst, s1);
3811                         break;
3812
3813                 default:
3814                         throw_cacao_exception_exit(string_java_lang_InternalError,
3815                                                                            "Unknown ICMD %d", iptr->opc);
3816         } /* switch */
3817
3818         } /* for instruction */
3819
3820         /* copy values to interface registers */
3821
3822         src = bptr->outstack;
3823         len = bptr->outdepth;
3824         MCODECHECK(64+len);
3825 #ifdef LSRA
3826         if (!opt_lsra)
3827 #endif
3828         while (src) {
3829                 len--;
3830                 if ((src->varkind != STACKVAR)) {
3831                         s2 = src->type;
3832                         if (IS_FLT_DBL_TYPE(s2)) {
3833                                 var_to_reg_flt(s1, src, REG_FTMP1);
3834                                 if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
3835                                         M_FLTMOVE(s1,rd->interfaces[len][s2].regoff);
3836                                         }
3837                                 else {
3838                                         M_DST(s1, REG_SP, 8 * rd->interfaces[len][s2].regoff);
3839                                         }
3840                                 }
3841                         else {
3842                                 var_to_reg_int(s1, src, REG_ITMP1);
3843                                 if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
3844                                         M_INTMOVE(s1,rd->interfaces[len][s2].regoff);
3845                                         }
3846                                 else {
3847                                         M_LST(s1, REG_SP, 8 * rd->interfaces[len][s2].regoff);
3848                                         }
3849                                 }
3850                         }
3851                 src = src->prev;
3852                 }
3853         } /* if (bptr -> flags >= BBREACHED) */
3854         } /* for basic block */
3855
3856         codegen_createlinenumbertable(cd);
3857
3858         {
3859         /* generate bound check stubs */
3860
3861         s4 *xcodeptr = NULL;
3862         branchref *bref;
3863
3864         for (bref = cd->xboundrefs; bref != NULL; bref = bref->next) {
3865                 gen_resolvebranch((u1*) cd->mcodebase + bref->branchpos,
3866                                   bref->branchpos,
3867                                                   (u1*) mcodeptr - cd->mcodebase);
3868
3869                 MCODECHECK(8);
3870
3871                 /* move index register into REG_ITMP1 */
3872                 M_MOV(bref->reg, REG_ITMP1);
3873                 M_LDA(REG_ITMP2_XPC, REG_PV, bref->branchpos - 4);
3874
3875                 if (xcodeptr != NULL) {
3876                         M_BR(xcodeptr - mcodeptr - 1);
3877
3878                 } else {
3879                         xcodeptr = mcodeptr;
3880
3881                         a = dseg_addaddress(cd, asm_throw_and_handle_arrayindexoutofbounds_exception);
3882                         M_ALD(REG_PV, REG_PV, a);
3883
3884                         M_JSR(REG_RA, REG_PV);
3885
3886                         /* recompute pv */
3887                         s1 = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3888                         if (s1 <= 32768) M_LDA(REG_PV, REG_RA, -s1);
3889                         else {
3890                                 s4 ml = -s1, mh = 0;
3891                                 while (ml < -32768) { ml += 65536; mh--; }
3892                                 M_LDA(REG_PV, REG_RA, ml);
3893                                 M_LDAH(REG_PV, REG_PV, mh);
3894                         }
3895                 }
3896         }
3897
3898         /* generate negative array size check stubs */
3899
3900         xcodeptr = NULL;
3901
3902         for (bref = cd->xcheckarefs; bref != NULL; bref = bref->next) {
3903                 if ((cd->exceptiontablelength == 0) && (xcodeptr != NULL)) {
3904                         gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
3905                                                           bref->branchpos,
3906                                                           (u1 *) xcodeptr - (u1 *) cd->mcodebase - 4);
3907                         continue;
3908                 }
3909
3910                 gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
3911                                   bref->branchpos,
3912                                                   (u1 *) mcodeptr - cd->mcodebase);
3913
3914                 MCODECHECK(8);
3915
3916                 M_LDA(REG_ITMP2_XPC, REG_PV, bref->branchpos - 4);
3917
3918                 if (xcodeptr != NULL) {
3919                         M_BR(xcodeptr - mcodeptr - 1);
3920
3921                 } else {
3922                         xcodeptr = mcodeptr;
3923
3924
3925                         a = dseg_addaddress(cd, string_java_lang_NegativeArraySizeException);
3926                         M_ALD(REG_ITMP1_XPTR,REG_PV,a);
3927
3928                         a = dseg_addaddress(cd, asm_throw_and_handle_nat_exception);
3929                         M_ALD(REG_PV, REG_PV, a);
3930
3931                         M_JSR(REG_RA, REG_PV);
3932
3933                         /* recompute pv */
3934                         s1 = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3935                         if (s1 <= 32768) M_LDA(REG_PV, REG_RA, -s1);
3936                         else {
3937                                 s4 ml = -s1, mh = 0;
3938                                 while (ml < -32768) { ml += 65536; mh--; }
3939                                 M_LDA(REG_PV, REG_RA, ml);
3940                                 M_LDAH(REG_PV, REG_PV, mh);
3941                         }
3942
3943
3944                 }
3945         }
3946
3947         /* generate cast check stubs */
3948
3949         xcodeptr = NULL;
3950
3951         for (bref = cd->xcastrefs; bref != NULL; bref = bref->next) {
3952                 if ((cd->exceptiontablelength == 0) && (xcodeptr != NULL)) {
3953                         gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
3954                                                           bref->branchpos,
3955                                                           (u1 *) xcodeptr - (u1 *) cd->mcodebase - 4);
3956                         continue;
3957                 }
3958
3959                 gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
3960                                   bref->branchpos,
3961                                                   (u1 *) mcodeptr - cd->mcodebase);
3962
3963                 MCODECHECK(8);
3964
3965                 M_LDA(REG_ITMP2_XPC, REG_PV, bref->branchpos - 4);
3966
3967                 if (xcodeptr != NULL) {
3968                         M_BR(xcodeptr - mcodeptr - 1);
3969
3970                 } else {
3971                         xcodeptr = mcodeptr;
3972
3973                         a = dseg_addaddress(cd, string_java_lang_ClassCastException);
3974                         M_ALD(REG_ITMP1_XPTR,REG_PV,a);
3975
3976                         a = dseg_addaddress(cd, asm_throw_and_handle_nat_exception);
3977                         M_ALD(REG_PV, REG_PV, a);
3978
3979                         M_JSR(REG_RA, REG_PV);
3980
3981                         /* recompute pv */
3982                         s1 = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3983                         if (s1 <= 32768) M_LDA(REG_PV, REG_RA, -s1);
3984                         else {
3985                                 s4 ml = -s1, mh = 0;
3986                                 while (ml < -32768) { ml += 65536; mh--; }
3987                                 M_LDA(REG_PV, REG_RA, ml);
3988                                 M_LDAH(REG_PV, REG_PV, mh);
3989                         }
3990
3991                 }
3992         }
3993
3994         /* generate exception check stubs */
3995
3996         xcodeptr = NULL;
3997
3998         for (bref = cd->xexceptionrefs; bref != NULL; bref = bref->next) {
3999                 if ((cd->exceptiontablelength == 0) && (xcodeptr != NULL)) {
4000                         gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
4001                                                           bref->branchpos,
4002                                                           (u1 *) xcodeptr - (u1 *) cd->mcodebase - 4);
4003                         continue;
4004                 }
4005
4006                 gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
4007                                   bref->branchpos,
4008                                                   (u1 *) mcodeptr - cd->mcodebase);
4009
4010                 MCODECHECK(8);
4011
4012                 M_LDA(REG_ITMP2_XPC, REG_PV, bref->branchpos - 4);
4013
4014                 if (xcodeptr != NULL) {
4015                         M_BR(xcodeptr - mcodeptr - 1);
4016
4017                 } else {
4018                         xcodeptr = mcodeptr;
4019
4020 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
4021                         M_LSUB_IMM(REG_SP, 1 * 8, REG_SP);
4022                         M_LST(REG_ITMP2_XPC, REG_SP, 0 * 8);
4023
4024                         a = dseg_addaddress(cd, &builtin_get_exceptionptrptr);
4025                         M_ALD(REG_PV, REG_PV, a);
4026                         M_JSR(REG_RA, REG_PV);
4027
4028                         /* recompute pv */
4029                         s1 = (s4) ((u1 *) mcodeptr - cd->mcodebase);
4030                         if (s1 <= 32768) M_LDA(REG_PV, REG_RA, -s1);
4031                         else {
4032                                 s4 ml = -s1, mh = 0;
4033                                 while (ml < -32768) { ml += 65536; mh--; }
4034                                 M_LDA(REG_PV, REG_RA, ml);
4035                                 M_LDAH(REG_PV, REG_PV, mh);
4036                         }
4037
4038                         M_ALD(REG_ITMP1_XPTR, REG_RESULT, 0);
4039                         M_AST(REG_ZERO, REG_RESULT, 0);
4040
4041                         M_LLD(REG_ITMP2_XPC, REG_SP, 0 * 8);
4042                         M_LADD_IMM(REG_SP, 1 * 8, REG_SP);
4043 #else
4044                         a = dseg_addaddress(cd, &_exceptionptr);
4045                         M_ALD(REG_ITMP3, REG_PV, a);
4046                         M_ALD(REG_ITMP1_XPTR, REG_ITMP3, 0);
4047                         M_AST(REG_ZERO, REG_ITMP3, 0);
4048 #endif
4049
4050                         a = dseg_addaddress(cd, asm_refillin_and_handle_exception);
4051                         M_ALD(REG_PV, REG_PV, a);
4052
4053                         M_JMP(REG_RA, REG_PV);
4054
4055                         /* recompute pv */
4056                         s1 = (s4) ((u1 *) mcodeptr - cd->mcodebase);
4057                         if (s1 <= 32768) M_LDA(REG_PV, REG_RA, -s1);
4058                         else {
4059                                 s4 ml = -s1, mh = 0;
4060                                 while (ml < -32768) { ml += 65536; mh--; }
4061                                 M_LDA(REG_PV, REG_RA, ml);
4062                                 M_LDAH(REG_PV, REG_PV, mh);
4063                         }
4064
4065                 }
4066         }
4067
4068         /* generate null pointer check stubs */
4069
4070         xcodeptr = NULL;
4071
4072         for (bref = cd->xnullrefs; bref != NULL; bref = bref->next) {
4073                 if ((cd->exceptiontablelength == 0) && (xcodeptr != NULL)) {
4074                         gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
4075                                                           bref->branchpos,
4076                                                           (u1 *) xcodeptr - (u1 *) cd->mcodebase - 4);
4077                         continue;
4078                 }
4079
4080                 gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
4081                                   bref->branchpos,
4082                                                   (u1 *) mcodeptr - cd->mcodebase);
4083
4084                 MCODECHECK(8);
4085
4086                 M_LDA(REG_ITMP2_XPC, REG_PV, bref->branchpos - 4);
4087
4088                 if (xcodeptr != NULL) {
4089                         M_BR(xcodeptr - mcodeptr - 1);
4090
4091                 } else {
4092                         xcodeptr = mcodeptr;
4093
4094                         a = dseg_addaddress(cd, string_java_lang_NullPointerException);
4095                         M_ALD(REG_ITMP1_XPTR,REG_PV,a);
4096
4097                         a = dseg_addaddress(cd, asm_throw_and_handle_nat_exception);
4098                         M_ALD(REG_PV, REG_PV, a);
4099
4100                         M_JSR(REG_RA, REG_PV);
4101
4102                         /* recompute pv */
4103                         s1 = (s4) ((u1 *) mcodeptr - cd->mcodebase);
4104                         if (s1 <= 32768) M_LDA(REG_PV, REG_RA, -s1);
4105                         else {
4106                                 s4 ml = -s1, mh = 0;
4107                                 while (ml < -32768) { ml += 65536; mh--; }
4108                                 M_LDA(REG_PV, REG_RA, ml);
4109                                 M_LDAH(REG_PV, REG_PV, mh);
4110                         }
4111
4112                 }
4113         }
4114
4115         /* generate put/getstatic stub call code */
4116
4117         {
4118                 patchref *pref;
4119                 u4        mcode;
4120                 s4       *tmpmcodeptr;
4121
4122                 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
4123                         /* check code segment size */
4124
4125                         MCODECHECK(13 + 4 + 1);
4126
4127                         /* Get machine code which is patched back in later. The call is   */
4128                         /* 1 instruction word long.                                       */
4129
4130                         xcodeptr = (s4 *) (cd->mcodebase + pref->branchpos);
4131                         mcode = *xcodeptr;
4132
4133 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
4134                         /* create a virtual java_objectheader */
4135
4136                         /* align data structure to 8-byte */
4137
4138                         ALIGNCODENOP;
4139
4140                         *((ptrint *) (mcodeptr + 0)) = 0;                        /* vftbl */
4141                         *((ptrint *) (mcodeptr + 2)) = (ptrint) get_dummyLR(); /* monitorPtr */
4142
4143                         mcodeptr += 2 * 2;                 /* mcodeptr is a `u4*' pointer */
4144 #endif
4145
4146                         /* patch in the call to call the following code (done at compile  */
4147                         /* time)                                                          */
4148
4149                         tmpmcodeptr = mcodeptr;         /* save current mcodeptr          */
4150                         mcodeptr = xcodeptr;            /* set mcodeptr to patch position */
4151
4152                         M_BSR(REG_ITMP3, tmpmcodeptr - (xcodeptr + 1));
4153
4154                         mcodeptr = tmpmcodeptr;         /* restore the current mcodeptr   */
4155
4156                         /* create stack frame */
4157
4158                         M_LSUB_IMM(REG_SP, 5 * 8, REG_SP);
4159
4160                         /* move return address onto stack */
4161
4162                         M_AST(REG_ITMP3, REG_SP, 4 * 8);
4163
4164                         /* move pointer to java_objectheader onto stack */
4165
4166 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
4167                         M_BSR(REG_ITMP3, 0);
4168                         M_LSUB_IMM(REG_ITMP3, 3 * 4 + 2 * 8, REG_ITMP3);
4169                         M_AST(REG_ITMP3, REG_SP, 3 * 8);
4170 #else
4171                         M_AST(REG_ZERO, REG_SP, 3 * 8);
4172 #endif
4173
4174                         /* move machine code onto stack */
4175
4176                         a = dseg_adds4(cd, mcode);
4177                         M_ILD(REG_ITMP3, REG_PV, a);
4178                         M_IST(REG_ITMP3, REG_SP, 2 * 8);
4179
4180                         /* move class/method/field reference onto stack */
4181
4182                         a = dseg_addaddress(cd, pref->ref);
4183                         M_ALD(REG_ITMP3, REG_PV, a);
4184                         M_AST(REG_ITMP3, REG_SP, 1 * 8);
4185
4186                         /* move patcher function pointer onto stack */
4187
4188                         a = dseg_addaddress(cd, pref->patcher);
4189                         M_ALD(REG_ITMP3, REG_PV, a);
4190                         M_AST(REG_ITMP3, REG_SP, 0 * 8);
4191
4192                         a = dseg_addaddress(cd, asm_wrapper_patcher);
4193                         M_ALD(REG_ITMP3, REG_PV, a);
4194                         M_JMP(REG_ZERO, REG_ITMP3);
4195                 }
4196         }
4197         }
4198
4199         codegen_finish(m, cd, (s4) ((u1 *) mcodeptr - cd->mcodebase));
4200 }
4201
4202
4203 /* function createcompilerstub *************************************************
4204
4205         creates a stub routine which calls the compiler
4206
4207 *******************************************************************************/
4208
4209 #define COMPSTUBSIZE    3
4210
4211 u1 *createcompilerstub(methodinfo *m)
4212 {
4213         u8 *s = CNEW(u8, COMPSTUBSIZE);     /* memory to hold the stub            */
4214         s4 *mcodeptr = (s4 *) s;            /* code generation pointer            */
4215
4216                                             /* code for the stub                  */
4217         M_ALD(REG_PV, REG_PV, 16);          /* load pointer to the compiler       */
4218         M_JMP(0, REG_PV);                   /* jump to the compiler, return address
4219                                                in reg 0 is used as method pointer */
4220         s[1] = (u8) m;                      /* literals to be adressed            */
4221         s[2] = (u8) asm_call_jit_compiler;  /* jump directly via PV from above    */
4222
4223 #if defined(STATISTICS)
4224         if (opt_stat)
4225                 count_cstub_len += COMPSTUBSIZE * 8;
4226 #endif
4227
4228         return (u1 *) s;
4229 }
4230
4231
4232 /* function removecompilerstub *************************************************
4233
4234      deletes a compilerstub from memory  (simply by freeing it)
4235
4236 *******************************************************************************/
4237
4238 void removecompilerstub(u1 *stub)
4239 {
4240         CFREE(stub, COMPSTUBSIZE * 8);
4241 }
4242
4243
4244 /* function: createnativestub **************************************************
4245
4246         creates a stub routine which calls a native method
4247
4248 *******************************************************************************/
4249
4250
4251 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
4252 #define NATIVESTUB_STACK          8/*ra,native result, oldThreadspecificHeadValue, addressOfThreadspecificHead, method, 0,0,ra*/
4253 #define NATIVESTUB_THREAD_EXTRA    (6 + 20) /*20 for additional frame creation*/
4254 #define NATIVESTUB_STACKTRACE_OFFSET   1
4255 #else
4256 #define NATIVESTUB_STACK          7/*ra,oldThreadspecificHeadValue, addressOfThreadspecificHead, method, 0,0,ra*/
4257 #define NATIVESTUB_THREAD_EXTRA    (1 + 20) /*20 for additional frame creation*/
4258 #define NATIVESTUB_STACKTRACE_OFFSET   0
4259 #endif
4260
4261 #define NATIVESTUB_SIZE            (44 + NATIVESTUB_THREAD_EXTRA - 1)
4262 #define NATIVESTUB_STATIC_SIZE     5
4263 #define NATIVESTUB_VERBOSE_SIZE    (39 + 13)
4264 #define NATIVESTUB_OFFSET          12
4265
4266 #if 0
4267 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
4268 #define NATIVESTUB_STACK           2
4269 #define NATIVESTUB_THREAD_EXTRA    6
4270 #else
4271 #define NATIVESTUB_STACK           1
4272 #define NATIVESTUB_THREAD_EXTRA    1
4273 #endif
4274
4275 #define NATIVESTUB_SIZE            (44 + NATIVESTUB_THREAD_EXTRA - 1)
4276 #define NATIVESTUB_STATIC_SIZE     4
4277 #define NATIVESTUB_VERBOSE_SIZE    (39 + 13)
4278 #define NATIVESTUB_OFFSET          10
4279 #endif
4280
4281 u1 *createnativestub(functionptr f, methodinfo *m)
4282 {
4283         u8 *s;                              /* memory pointer to hold the stub    */
4284         u8 *cs;
4285         s4 *mcodeptr;                       /* code generation pointer            */
4286         s4 stackframesize = 0;              /* size of stackframe if needed       */
4287         s4 disp;
4288         s4 stubsize;
4289         codegendata  *cd;
4290         registerdata *rd;
4291         t_inlining_globals *id;
4292         s4 dumpsize;
4293
4294         /* mark start of dump memory area */
4295
4296         dumpsize = dump_size();
4297
4298         /* setup registers before using it */
4299
4300         cd = DNEW(codegendata);
4301         rd = DNEW(registerdata);
4302         id = DNEW(t_inlining_globals);
4303
4304         inlining_setup(m, id);
4305         reg_setup(m, rd, id);
4306
4307         method_descriptor2types(m);                /* set paramcount and paramtypes      */
4308
4309         stubsize = NATIVESTUB_SIZE;         /* calculate nativestub size          */
4310
4311         if ((m->flags & ACC_STATIC) && !m->class->initialized)
4312                 stubsize += NATIVESTUB_STATIC_SIZE;
4313
4314         if (runverbose)
4315                 stubsize += NATIVESTUB_VERBOSE_SIZE;
4316
4317         s = CNEW(u8, stubsize);             /* memory to hold the stub            */
4318         cs = s + NATIVESTUB_OFFSET;
4319         mcodeptr = (s4 *) cs;               /* code generation pointer            */
4320
4321         /* set some required varibles which are normally set by codegen_setup     */
4322         cd->mcodebase = (u1 *) mcodeptr;
4323         cd->patchrefs = NULL;
4324
4325         *(cs-1)  = (u8) f;                  /* address of native method           */
4326 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
4327         *(cs-2)  = (u8) &builtin_get_exceptionptrptr;
4328 #else
4329         *(cs-2)  = (u8) (&_exceptionptr);   /* address of exceptionptr            */
4330 #endif
4331         *(cs-3)  = (u8) asm_handle_nat_exception; /* addr of asm exception handler*/
4332         *(cs-4)  = (u8) (&env);             /* addr of jni_environement           */
4333         *(cs-5)  = (u8) builtin_trace_args;
4334         *(cs-6)  = (u8) m;
4335         *(cs-7)  = (u8) builtin_displaymethodstop;
4336         *(cs-8)  = (u8) m->class;
4337         *(cs-9)  = (u8) asm_wrapper_patcher;
4338         *(cs-10) = (u8) &builtin_asm_get_stackframeinfo;
4339         *(cs-11) = (u8) NULL;               /* filled with machine code           */
4340         *(cs-12) = (u8) PATCHER_clinit;
4341
4342         M_LDA(REG_SP, REG_SP, -NATIVESTUB_STACK * 8);     /* build up stackframe  */
4343         M_AST(REG_RA, REG_SP, 0 * 8);       /* store return address               */
4344
4345         M_AST(REG_RA, REG_SP, (6+NATIVESTUB_STACKTRACE_OFFSET) * 8);       /* store return address  in stackinfo helper*/
4346
4347         /* if function is static, check for initialized */
4348
4349         if (m->flags & ACC_STATIC) {
4350         /* if class isn't yet initialized, do it */
4351                 if (!m->class->initialized) {
4352                         codegen_addpatchref(cd, mcodeptr, NULL, NULL);
4353                 }
4354         }
4355
4356         /* max. 39 +9 instructions */
4357         {
4358                 s4 p;
4359                 s4 t;
4360                 M_LDA(REG_SP, REG_SP, -((INT_ARG_CNT + FLT_ARG_CNT + 2) * 8));
4361                 M_AST(REG_RA, REG_SP, 1 * 8);
4362
4363                 /* save integer argument registers */
4364                 for (p = 0; p < m->paramcount && p < INT_ARG_CNT; p++) {
4365                         M_LST(rd->argintregs[p], REG_SP, (2 + p) * 8);
4366                 }
4367
4368                 /* save and copy float arguments into integer registers */
4369                 for (p = 0; p < m->paramcount && p < FLT_ARG_CNT; p++) {
4370                         t = m->paramtypes[p];
4371
4372                         if (IS_FLT_DBL_TYPE(t)) {
4373                                 if (IS_2_WORD_TYPE(t)) {
4374                                         M_DST(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
4375                                         M_LLD(rd->argintregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
4376
4377                                 } else {
4378                                         M_FST(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
4379                                         M_ILD(rd->argintregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
4380                                 }
4381
4382                         } else {
4383                                 M_DST(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
4384                         }
4385                 }
4386
4387                 if (runverbose) {
4388                         M_ALD(REG_ITMP1, REG_PV, -6 * 8);
4389                         M_AST(REG_ITMP1, REG_SP, 0 * 8);
4390                         M_ALD(REG_PV, REG_PV, -5 * 8);
4391                         M_JSR(REG_RA, REG_PV);
4392                         disp = -(s4) (mcodeptr - (s4 *) cs) * 4;
4393                         M_LDA(REG_PV, REG_RA, disp);
4394                 }
4395
4396
4397 /*stack info */
4398                 M_ALD(REG_PV, REG_PV, -10 * 8);      /* builtin_asm_get_stackframeinfo        */
4399                 M_JSR(REG_RA, REG_PV);
4400                 disp = -(s4) (mcodeptr - (s4 *) cs) * 4;
4401                 M_LDA(REG_PV, REG_RA, disp);
4402
4403 #if 0
4404                 M_MOV(REG_RESULT,REG_ITMP3);
4405                 M_LST(REG_RESULT,REG_ITMP3,0);
4406 #endif
4407                 M_LST(REG_RESULT,REG_SP, ((INT_ARG_CNT + FLT_ARG_CNT + 2) * 8)+(2+NATIVESTUB_STACKTRACE_OFFSET)*8);/*save adress of pointer*/
4408                 M_LLD(REG_ITMP3,REG_RESULT,0); /* get pointer*/
4409                 M_LST(REG_ITMP3,REG_SP,(1+NATIVESTUB_STACKTRACE_OFFSET)*8+((INT_ARG_CNT + FLT_ARG_CNT + 2) * 8)); /*save old value*/
4410                 M_LDA(REG_ITMP3,REG_SP,(1+NATIVESTUB_STACKTRACE_OFFSET)*8+((INT_ARG_CNT + FLT_ARG_CNT + 2) * 8)); /*calculate new value*/
4411                 M_LLD(REG_ITMP2,REG_ITMP3,8);
4412                 M_LST(REG_ITMP3,REG_ITMP2,0); /*store new value*/
4413                 M_LLD(REG_ITMP2,REG_PV,-6*8);
4414                 M_LST(REG_ITMP2,REG_SP,(3+NATIVESTUB_STACKTRACE_OFFSET)*8+((INT_ARG_CNT + FLT_ARG_CNT + 2) * 8));
4415                 M_LST(REG_ZERO,REG_SP,(4+NATIVESTUB_STACKTRACE_OFFSET)*8+((INT_ARG_CNT + FLT_ARG_CNT + 2) * 8));
4416                 M_LST(REG_ZERO,REG_SP,(5+NATIVESTUB_STACKTRACE_OFFSET)*8+((INT_ARG_CNT + FLT_ARG_CNT + 2) * 8));
4417 /*stack info -end */
4418
4419
4420                 for (p = 0; p < m->paramcount && p < INT_ARG_CNT; p++) {
4421                         M_LLD(rd->argintregs[p], REG_SP, (2 + p) * 8);
4422                 }
4423
4424                 for (p = 0; p < m->paramcount && p < FLT_ARG_CNT; p++) {
4425                         t = m->paramtypes[p];
4426
4427                         if (IS_FLT_DBL_TYPE(t)) {
4428                                 if (IS_2_WORD_TYPE(t)) {
4429                                         M_DLD(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
4430
4431                                 } else {
4432                                         M_FLD(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
4433                                 }
4434
4435                         } else {
4436                                 M_DLD(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
4437                         }
4438                 }
4439
4440                 M_ALD(REG_RA, REG_SP, 1 * 8);
4441                 M_LDA(REG_SP, REG_SP, (INT_ARG_CNT + FLT_ARG_CNT + 2) * 8);
4442         }
4443
4444         /* save argument registers on stack -- if we have to */
4445         if ((m->flags & ACC_STATIC && m->paramcount > (INT_ARG_CNT - 2)) || m->paramcount > (INT_ARG_CNT - 1)) {
4446                 s4 i;
4447                 s4 paramshiftcnt = (m->flags & ACC_STATIC) ? 2 : 1;
4448                 s4 stackparamcnt = (m->paramcount > INT_ARG_CNT) ? m->paramcount - INT_ARG_CNT : 0;
4449
4450                 stackframesize = stackparamcnt + paramshiftcnt;
4451
4452                 M_LDA(REG_SP, REG_SP, -stackframesize * 8);
4453
4454                 /* copy stack arguments into new stack frame -- if any */
4455                 for (i = 0; i < stackparamcnt; i++) {
4456                         M_LLD(REG_ITMP1, REG_SP, (stackparamcnt + 1 + i) * 8);
4457                         M_LST(REG_ITMP1, REG_SP, (paramshiftcnt + i) * 8);
4458                 }
4459
4460                 if (m->flags & ACC_STATIC) {
4461                         if (IS_FLT_DBL_TYPE(m->paramtypes[5])) {
4462                                 M_DST(rd->argfltregs[5], REG_SP, 1 * 8);
4463                         } else {
4464                                 M_LST(rd->argintregs[5], REG_SP, 1 * 8);
4465                         }
4466
4467                         if (IS_FLT_DBL_TYPE(m->paramtypes[4])) {
4468                                 M_DST(rd->argfltregs[4], REG_SP, 0 * 8);
4469                         } else {
4470                                 M_LST(rd->argintregs[4], REG_SP, 0 * 8);
4471                         }
4472
4473                 } else {
4474                         if (IS_FLT_DBL_TYPE(m->paramtypes[5])) {
4475                                 M_DST(rd->argfltregs[5], REG_SP, 0 * 8);
4476                         } else {
4477                                 M_LST(rd->argintregs[5], REG_SP, 0 * 8);
4478                         }
4479                 }
4480         }
4481 #if 1
4482         {
4483                 s4 i;
4484
4485                 if (m->flags & ACC_STATIC) {
4486                         /* shift iargs count if less than INT_ARG_CNT, or all */
4487                         for (i = (m->paramcount < (INT_ARG_CNT - 2)) ? m->paramcount : (INT_ARG_CNT - 2); i >= 0; i--) {
4488                                 M_MOV(rd->argintregs[i], rd->argintregs[i + 2]);
4489                                 M_FMOV(rd->argfltregs[i], rd->argfltregs[i + 2]);
4490                         }
4491
4492                         /* put class into second argument register */
4493                         M_ALD(rd->argintregs[1], REG_PV, -8 * 8);
4494
4495                 } else {
4496                         /* shift iargs count if less than INT_ARG_CNT, or all */
4497                         for (i = (m->paramcount < (INT_ARG_CNT - 1)) ? m->paramcount : (INT_ARG_CNT - 1); i >= 0; i--) {
4498                                 M_MOV(rd->argintregs[i], rd->argintregs[i + 1]);
4499                                 M_FMOV(rd->argfltregs[i], rd->argfltregs[i + 1]);
4500                         }
4501                 }
4502         }
4503 #else
4504         if (m->flags & ACC_STATIC) {
4505                 M_MOV(rd->argintregs[3], rd->argintregs[5]);
4506                 M_MOV(rd->argintregs[2], rd->argintregs[4]);
4507                 M_MOV(rd->argintregs[1], rd->argintregs[3]);
4508                 M_MOV(rd->argintregs[0], rd->argintregs[2]);
4509                 M_FMOV(rd->argfltregs[3], rd->argfltregs[5]);
4510                 M_FMOV(rd->argfltregs[2], rd->argfltregs[4]);
4511                 M_FMOV(rd->argfltregs[1], rd->argfltregs[3]);
4512                 M_FMOV(rd->argfltregs[0], rd->argfltregs[2]);
4513
4514                 /* put class into second argument register */
4515                 M_ALD(rd->argintregs[1], REG_PV, -8 * 8);
4516
4517         } else {
4518                 M_MOV(rd->argintregs[4], rd->argintregs[5]);
4519                 M_MOV(rd->argintregs[3], rd->argintregs[4]);
4520                 M_MOV(rd->argintregs[2], rd->argintregs[3]);
4521                 M_MOV(rd->argintregs[1], rd->argintregs[2]);
4522                 M_MOV(rd->argintregs[0], rd->argintregs[1]);
4523                 M_FMOV(rd->argfltregs[4], rd->argfltregs[5]);
4524                 M_FMOV(rd->argfltregs[3], rd->argfltregs[4]);
4525                 M_FMOV(rd->argfltregs[2], rd->argfltregs[3]);
4526                 M_FMOV(rd->argfltregs[1], rd->argfltregs[2]);
4527                 M_FMOV(rd->argfltregs[0], rd->argfltregs[1]);
4528         }
4529 #endif
4530
4531         /* put env into first argument register */
4532         M_ALD(rd->argintregs[0], REG_PV, -4 * 8);
4533
4534         M_ALD(REG_PV, REG_PV, -1 * 8);      /* load adress of native method       */
4535         M_JSR(REG_RA, REG_PV);              /* call native method                 */
4536         disp = -(s4) (mcodeptr - (s4 *) cs) * 4;
4537         M_LDA(REG_PV, REG_RA, disp);        /* recompute pv from ra               */
4538
4539         /* remove stackframe if there is one */
4540         if (stackframesize) {
4541                 M_LDA(REG_SP, REG_SP, stackframesize * 8);
4542         }
4543
4544         /* 13 instructions */
4545         if (runverbose) {
4546                 M_LDA(REG_SP, REG_SP, -2 * 8);
4547                 M_ALD(rd->argintregs[0], REG_PV, -6 * 8); /* load method adress       */
4548                 M_LST(REG_RESULT, REG_SP, 0 * 8);
4549                 M_DST(REG_FRESULT, REG_SP, 1 * 8);
4550                 M_MOV(REG_RESULT, rd->argintregs[1]);
4551                 M_FMOV(REG_FRESULT, rd->argfltregs[2]);
4552                 M_FMOV(REG_FRESULT, rd->argfltregs[3]);
4553                 M_ALD(REG_PV, REG_PV, -7 * 8);  /* builtin_displaymethodstop          */
4554                 M_JSR(REG_RA, REG_PV);
4555                 disp = -(s4) (mcodeptr - (s4 *) cs) * 4;
4556                 M_LDA(REG_PV, REG_RA, disp);
4557                 M_LLD(REG_RESULT, REG_SP, 0 * 8);
4558                 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
4559                 M_LDA(REG_SP, REG_SP, 2 * 8);
4560         }
4561
4562         M_LLD(REG_ITMP3,REG_SP,(2+NATIVESTUB_STACKTRACE_OFFSET)*8); /*get address of stacktrace helper pointer*/
4563         M_LLD(REG_ITMP1,REG_SP,(1+NATIVESTUB_STACKTRACE_OFFSET)*8); /*get old value*/
4564         M_LST(REG_ITMP1,REG_ITMP3,0); /*set old value*/
4565
4566 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
4567         if (IS_FLT_DBL_TYPE(m->returntype))
4568                 M_DST(REG_FRESULT, REG_SP, 1 * 8);
4569         else
4570                 M_AST(REG_RESULT, REG_SP, 1 * 8);
4571         M_ALD(REG_PV, REG_PV, -2 * 8);      /* builtin_get_exceptionptrptr        */
4572         M_JSR(REG_RA, REG_PV);
4573         disp = -(s4) (mcodeptr - (s4 *) cs) * 4;
4574         M_LDA(REG_PV, REG_RA, disp);
4575         M_MOV(REG_RESULT, REG_ITMP3);
4576         if (IS_FLT_DBL_TYPE(m->returntype))
4577                 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
4578         else
4579                 M_ALD(REG_RESULT, REG_SP, 1 * 8);
4580 #else
4581         M_ALD(REG_ITMP3, REG_PV, -2 * 8);   /* get address of exceptionptr        */
4582 #endif
4583         M_ALD(REG_ITMP1, REG_ITMP3, 0);     /* load exception into reg. itmp1     */
4584         M_BNEZ(REG_ITMP1, 3);               /* if no exception then return        */
4585
4586         M_ALD(REG_RA, REG_SP, 0 * 8);       /* load return address                */
4587         M_LDA(REG_SP, REG_SP, NATIVESTUB_STACK * 8); /* remove stackframe         */
4588         M_RET(REG_ZERO, REG_RA);            /* return to caller                   */
4589
4590         M_AST(REG_ZERO, REG_ITMP3, 0);      /* store NULL into exceptionptr       */
4591
4592         M_ALD(REG_RA, REG_SP, 0 * 8);       /* load return address                */
4593         M_LDA(REG_SP, REG_SP, NATIVESTUB_STACK * 8); /* remove stackframe         */
4594         M_LDA(REG_ITMP2, REG_RA, -4);       /* move fault address into reg. itmp2 */
4595         M_ALD(REG_ITMP3, REG_PV, -3 * 8);   /* load asm exception handler address */
4596         M_JMP(REG_ZERO, REG_ITMP3);         /* jump to asm exception handler      */
4597
4598         /* generate put/getstatic stub call code */
4599
4600         {
4601                 patchref *pref;
4602                 s4       *xcodeptr;
4603                 s4       *tmpmcodeptr;
4604
4605                 /* there can only be one <clinit> ref entry                           */
4606                 pref = cd->patchrefs;
4607
4608                 if (pref) {
4609                         /* Get machine code which is patched back in later. The call is   */
4610                         /* 1 instruction word long.                                       */
4611
4612                         xcodeptr = (s4 *) (cd->mcodebase + pref->branchpos);
4613                         *(cs-11) = (u4) *xcodeptr;
4614
4615 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
4616                         /* create a virtual java_objectheader */
4617
4618                         /* align data structure to 8-byte */
4619
4620                         ALIGNCODENOP;
4621
4622                         *((ptrint *) (mcodeptr + 0)) = 0;                        /* vftbl */
4623                         *((ptrint *) (mcodeptr + 2)) = (ptrint) get_dummyLR(); /* monitorPtr */
4624
4625                         mcodeptr += 2 * 2;                 /* mcodeptr is a `u4*' pointer */
4626 #endif
4627
4628                         /* patch in the call to call the following code (done at compile  */
4629                         /* time)                                                          */
4630
4631                         tmpmcodeptr = mcodeptr;         /* save current mcodeptr          */
4632                         mcodeptr = xcodeptr;            /* set mcodeptr to patch position */
4633
4634                         M_BSR(REG_ITMP3, tmpmcodeptr - (xcodeptr + 1));
4635
4636                         mcodeptr = tmpmcodeptr;         /* restore the current mcodeptr   */
4637
4638                         /* create stack frame                                             */
4639
4640                         M_LSUB_IMM(REG_SP, 5 * 8, REG_SP);
4641
4642                         /* move return address onto stack */
4643
4644                         M_AST(REG_ITMP3, REG_SP, 4 * 8);
4645
4646                         /* move pointer to java_objectheader onto stack */
4647
4648 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
4649                         M_BSR(REG_ITMP3, 0);
4650                         M_LSUB_IMM(REG_ITMP3, 3 * 4 + 2 * 8, REG_ITMP3);
4651                         M_AST(REG_ITMP3, REG_SP, 3 * 8);
4652 #else
4653                         M_AST(REG_ZERO, REG_SP, 3 * 8);
4654 #endif
4655
4656                         /* move machine code onto stack                                   */
4657
4658                         M_ILD(REG_ITMP3, REG_PV, -11 * 8);    /* machine code             */
4659                         M_IST(REG_ITMP3, REG_SP, 2 * 8);
4660
4661                         /* move class reference onto stack                                */
4662
4663                         M_ALD(REG_ITMP3, REG_PV, -8 * 8);     /* class                    */
4664                         M_AST(REG_ITMP3, REG_SP, 1 * 8);
4665
4666                         /* move patcher function pointer onto stack                       */
4667
4668                         M_ALD(REG_ITMP3, REG_PV, -12 * 8);    /* patcher function         */
4669                         M_AST(REG_ITMP3, REG_SP, 0 * 8);
4670
4671                         M_ALD(REG_ITMP3, REG_PV, -9 * 8);     /* asm_wrapper_patcher      */
4672                         M_JMP(REG_ZERO, REG_ITMP3);
4673                 }
4674         }
4675
4676         /* Check if the stub size is big enough to hold the whole stub generated. */
4677         /* If not, this can lead into unpredictable crashes, because of heap      */
4678         /* corruption.                                                            */
4679         if ((s4) ((ptrint) mcodeptr - (ptrint) s) > stubsize * sizeof(u8)) {
4680                 throw_cacao_exception_exit(string_java_lang_InternalError,
4681                                                                    "Native stub size %d is to small for current stub size %d",
4682                                                                    stubsize, (s4) ((ptrint) mcodeptr - (ptrint) s));
4683         }
4684
4685 #if defined(STATISTICS)
4686         if (opt_stat)
4687                 count_nstub_len += NATIVESTUB_SIZE * 8;
4688 #endif
4689
4690         /* release dump area */
4691
4692         dump_release(dumpsize);
4693
4694         return (u1 *) (s + NATIVESTUB_OFFSET);
4695 }
4696
4697
4698 /* function: removenativestub **************************************************
4699
4700     removes a previously created native-stub from memory
4701
4702 *******************************************************************************/
4703
4704 void removenativestub(u1 *stub)
4705 {
4706         CFREE((u8 *) stub - NATIVESTUBOFFSET, NATIVESTUBSIZE * 8);
4707 }
4708
4709
4710 /*
4711  * These are local overrides for various environment variables in Emacs.
4712  * Please do not remove this and leave it at the end of the file, where
4713  * Emacs will automagically detect them.
4714  * ---------------------------------------------------------------------
4715  * Local variables:
4716  * mode: c
4717  * indent-tabs-mode: t
4718  * c-basic-offset: 4
4719  * tab-width: 4
4720  * End:
4721  */