src/vm/jit/alpha/codegen.c

   1 /* src/vm/jit/alpha/codegen.c - machine code generator for Alpha
   2
   3    Copyright (C) 1996-2005 R. Grafl, A. Krall, C. Kruegel, C. Oates,
   4    R. Obermaisser, M. Platter, M. Probst, S. Ring, E. Steiner,
   5    C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich, J. Wenninger,
   6    Institut f. Computersprachen - TU Wien
   7
   8    This file is part of CACAO.
   9
  10    This program is free software; you can redistribute it and/or
  11    modify it under the terms of the GNU General Public License as
  12    published by the Free Software Foundation; either version 2, or (at
  13    your option) any later version.
  14
  15    This program is distributed in the hope that it will be useful, but
  16    WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18    General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program; if not, write to the Free Software
  22    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
  23    02111-1307, USA.
  24
  25    Contact: cacao@complang.tuwien.ac.at
  26
  27    Authors: Andreas Krall
  28             Reinhard Grafl
  29
  30    Changes: Joseph Wenninger
  31             Christian Thalinger
  32             Christian Ullrich
  33
  34    $Id: codegen.c 2774 2005-06-22 09:47:44Z christian $
  35
  36 */
  37
  38
  39 #include <stdio.h>
  40
  41 #include "config.h"
  42
  43 #include "md.h"
  44 #include "md-abi.h"
  45 #include "md-abi.inc"
  46
  47 #include "vm/jit/alpha/arch.h"
  48 #include "vm/jit/alpha/codegen.h"
  49 #include "vm/jit/alpha/types.h"
  50 #include "vm/jit/alpha/asmoffsets.h"
  51
  52 #include "cacao/cacao.h"
  53 #include "native/native.h"
  54 #include "vm/builtin.h"
  55 #include "vm/global.h"
  56 #include "vm/loader.h"
  57 #include "vm/stringlocal.h"
  58 #include "vm/tables.h"
  59 #include "vm/jit/asmpart.h"
  60 #include "vm/jit/codegen.inc"
  61 #include "vm/jit/jit.h"
  62
  63 #if defined(LSRA)
  64 # include "vm/jit/lsra.h"
  65 # include "vm/jit/lsra.inc"
  66 #endif
  67
  68 #include "vm/jit/parse.h"
  69 #include "vm/jit/patcher.h"
  70 #include "vm/jit/reg.h"
  71 #include "vm/jit/reg.inc"
  72
  73
  74 /* codegen *********************************************************************
  75
  76    Generates machine code.
  77
  78 *******************************************************************************/
  79
  80 void codegen(methodinfo *m, codegendata *cd, registerdata *rd)
  81 {
  82         s4                  len, s1, s2, s3, d;
  83         ptrint              a;
  84         s4                  parentargs_base;
  85         s4                 *mcodeptr;
  86         stackptr            src;
  87         varinfo            *var;
  88         basicblock         *bptr;
  89         instruction        *iptr;
  90         exceptiontable     *ex;
  91         u2                  currentline;
  92         methodinfo         *lm;             /* local methodinfo for ICMD_INVOKE*  */
  93         builtintable_entry *bte;
  94         methoddesc         *md;
  95
  96         {
  97         s4 i, p, t, l;
  98         s4 savedregs_num;
  99
 100         savedregs_num = (m->isleafmethod) ? 0 : 1;        /* space to save the RA */
 101
 102         /* space to save used callee saved registers */
 103
 104         savedregs_num += (INT_SAV_CNT - rd->savintreguse);
 105         savedregs_num += (FLT_SAV_CNT - rd->savfltreguse);
 106
 107         parentargs_base = rd->memuse + savedregs_num;
 108
 109 #if defined(USE_THREADS)           /* space to save argument of monitor_enter */
 110
 111         if (checksync && (m->flags & ACC_SYNCHRONIZED))
 112                 parentargs_base++;
 113
 114 #endif
 115
 116         /* create method header */
 117
 118         (void) dseg_addaddress(cd, m);                          /* MethodPointer  */
 119         (void) dseg_adds4(cd, parentargs_base * 8);             /* FrameSize      */
 120
 121 #if defined(USE_THREADS)
 122
 123         /* IsSync contains the offset relative to the stack pointer for the
 124            argument of monitor_exit used in the exception handler. Since the
 125            offset could be zero and give a wrong meaning of the flag it is
 126            offset by one.
 127         */
 128
 129         if (checksync && (m->flags & ACC_SYNCHRONIZED))
 130                 (void) dseg_adds4(cd, (rd->memuse + 1) * 8);     /* IsSync         */
 131         else
 132
 133 #endif
 134
 135         (void) dseg_adds4(cd, 0);                               /* IsSync         */
 136
 137         (void) dseg_adds4(cd, m->isleafmethod);                 /* IsLeaf         */
 138         (void) dseg_adds4(cd, INT_SAV_CNT - rd->savintreguse);/* IntSave  */
 139         (void) dseg_adds4(cd, FLT_SAV_CNT - rd->savfltreguse);/* FltSave  */
 140
 141         dseg_addlinenumbertablesize(cd);
 142
 143         (void) dseg_adds4(cd, cd->exceptiontablelength);        /* ExTableSize    */
 144
 145         /* create exception table */
 146
 147         for (ex = cd->exceptiontable; ex != NULL; ex = ex->down) {
 148                 dseg_addtarget(cd, ex->start);
 149                 dseg_addtarget(cd, ex->end);
 150                 dseg_addtarget(cd, ex->handler);
 151                 (void) dseg_addaddress(cd, ex->catchtype.cls);
 152         }
 153
 154         /* initialize mcode variables */
 155
 156         mcodeptr = (s4 *) cd->mcodebase;
 157         cd->mcodeend = (s4 *) (cd->mcodebase + cd->mcodesize);
 158         MCODECHECK(128 + m->paramcount);
 159
 160         /* create stack frame (if necessary) */
 161
 162         if (parentargs_base) {
 163                 M_LDA(REG_SP, REG_SP, -parentargs_base * 8);
 164         }
 165
 166         /* save return address and used callee saved registers */
 167
 168         p = parentargs_base;
 169         if (!m->isleafmethod) {
 170                 p--; M_AST(REG_RA, REG_SP, p * 8);
 171         }
 172         for (i = INT_SAV_CNT - 1; i >= rd->savintreguse; i--) {
 173                 p--; M_LST(rd->savintregs[i], REG_SP, p * 8);
 174         }
 175         for (i = FLT_SAV_CNT - 1; i >= rd->savfltreguse; i--) {
 176                 p--; M_DST(rd->savfltregs[i], REG_SP, p * 8);
 177         }
 178
 179         /* take arguments out of register or stack frame */
 180
 181         md = m->parseddesc;
 182
 183         for (p = 0, l = 0; p < md->paramcount; p++) {
 184                 t = md->paramtypes[p].type;
 185                 var = &(rd->locals[l][t]);
 186                 l++;
 187                 if (IS_2_WORD_TYPE(t))    /* increment local counter for 2 word types */
 188                         l++;
 189                 if (var->type < 0)
 190                         continue;
 191                 s1 = md->params[p].regoff;
 192                 if (IS_INT_LNG_TYPE(t)) {                    /* integer args          */
 193                         if (!md->params[p].inmemory) {           /* register arguments    */
 194                                 s2 = rd->argintregs[s1];
 195                                 if (!(var->flags & INMEMORY)) {      /* reg arg -> register   */
 196                                         M_INTMOVE(s2, var->regoff);
 197
 198                                 } else {                             /* reg arg -> spilled    */
 199                                         M_LST(s2, REG_SP, var->regoff * 8);
 200                                 }
 201
 202                         } else {                                 /* stack arguments       */
 203                                 if (!(var->flags & INMEMORY)) {      /* stack arg -> register */
 204                                         M_LLD(var->regoff, REG_SP, (parentargs_base + s1) * 8);
 205
 206                                 } else {                             /* stack arg -> spilled  */
 207                                         var->regoff = parentargs_base + s1;
 208                                 }
 209                         }
 210
 211                 } else {                                     /* floating args         */
 212                         if (!md->params[p].inmemory) {           /* register arguments    */
 213                                 s2 = rd->argfltregs[s1];
 214                                 if (!(var->flags & INMEMORY)) {      /* reg arg -> register   */
 215                                         M_FLTMOVE(s2, var->regoff);
 216
 217                                 } else {                                         /* reg arg -> spilled    */
 218                                         M_DST(s2, REG_SP, var->regoff * 8);
 219                                 }
 220
 221                         } else {                                 /* stack arguments       */
 222                                 if (!(var->flags & INMEMORY)) {      /* stack-arg -> register */
 223                                         M_DLD(var->regoff, REG_SP, (parentargs_base + s1) * 8);
 224
 225                                 } else {                             /* stack-arg -> spilled  */
 226                                         var->regoff = parentargs_base + s1;
 227                                 }
 228                         }
 229                 }
 230         } /* end for */
 231
 232         /* call monitorenter function */
 233
 234 #if defined(USE_THREADS)
 235         if (checksync && (m->flags & ACC_SYNCHRONIZED)) {
 236                 /* stack offset for monitor argument */
 237
 238                 s1 = rd->memuse;
 239
 240                 if (runverbose) {
 241                         M_LDA(REG_SP, REG_SP, -(INT_ARG_CNT + FLT_ARG_CNT) * 8);
 242
 243                         for (p = 0; p < INT_ARG_CNT; p++)
 244                                 M_LST(rd->argintregs[p], REG_SP, p * 8);
 245
 246                         for (p = 0; p < FLT_ARG_CNT; p++)
 247                                 M_DST(rd->argfltregs[p], REG_SP, (INT_ARG_CNT + p) * 8);
 248
 249                         s1 += INT_ARG_CNT + FLT_ARG_CNT;
 250                 }
 251
 252                 /* decide which monitor enter function to call */
 253
 254                 if (m->flags & ACC_STATIC) {
 255                         p = dseg_addaddress(cd, m->class);
 256                         M_ALD(REG_ITMP1, REG_PV, p);
 257                         M_AST(REG_ITMP1, REG_SP, s1 * 8);
 258                         M_INTMOVE(REG_ITMP1, rd->argintregs[0]);
 259                         p = dseg_addaddress(cd, BUILTIN_staticmonitorenter);
 260                         M_ALD(REG_PV, REG_PV, p);
 261                         M_JSR(REG_RA, REG_PV);
 262                         d = -(s4) ((u1 *) mcodeptr - cd->mcodebase);
 263                         M_LDA(REG_PV, REG_RA, d);
 264
 265                 } else {
 266                         M_BEQZ(rd->argintregs[0], 0);
 267                         codegen_addxnullrefs(cd, mcodeptr);
 268                         M_AST(rd->argintregs[0], REG_SP, s1 * 8);
 269                         p = dseg_addaddress(cd, BUILTIN_monitorenter);
 270                         M_ALD(REG_PV, REG_PV, p);
 271                         M_JSR(REG_RA, REG_PV);
 272                         d = -(s4) ((u1 *) mcodeptr - cd->mcodebase);
 273                         M_LDA(REG_PV, REG_RA, d);
 274                 }
 275
 276                 if (runverbose) {
 277                         for (p = 0; p < INT_ARG_CNT; p++)
 278                                 M_LLD(rd->argintregs[p], REG_SP, p * 8);
 279
 280                         for (p = 0; p < FLT_ARG_CNT; p++)
 281                                 M_DLD(rd->argfltregs[p], REG_SP, (INT_ARG_CNT + p) * 8);
 282
 283                         M_LDA(REG_SP, REG_SP, (INT_ARG_CNT + FLT_ARG_CNT) * 8);
 284                 }
 285         }
 286 #endif
 287
 288         /* call trace function */
 289
 290         if (runverbose) {
 291                 M_LDA(REG_SP, REG_SP, -((INT_ARG_CNT + FLT_ARG_CNT + 2) * 8));
 292                 M_AST(REG_RA, REG_SP, 1 * 8);
 293
 294                 /* save integer argument registers */
 295
 296                 for (p = 0; p < md->paramcount && p < INT_ARG_CNT; p++)
 297                         M_LST(rd->argintregs[p], REG_SP, (2 + p) * 8);
 298
 299                 /* save and copy float arguments into integer registers */
 300
 301                 for (p = 0; p < md->paramcount && p < FLT_ARG_CNT; p++) {
 302                         t = md->paramtypes[p].type;
 303
 304                         if (IS_FLT_DBL_TYPE(t)) {
 305                                 if (IS_2_WORD_TYPE(t)) {
 306                                         M_DST(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 307
 308                                 } else {
 309                                         M_FST(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 310                                 }
 311
 312                                 M_LLD(rd->argintregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 313
 314                         } else {
 315                                 M_DST(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 316                         }
 317                 }
 318
 319                 p = dseg_addaddress(cd, m);
 320                 M_ALD(REG_ITMP1, REG_PV, p);
 321                 M_AST(REG_ITMP1, REG_SP, 0 * 8);
 322                 p = dseg_addaddress(cd, (void *) builtin_trace_args);
 323                 M_ALD(REG_PV, REG_PV, p);
 324                 M_JSR(REG_RA, REG_PV);
 325                 d = -(s4) ((u1 *) mcodeptr - cd->mcodebase);
 326                 M_LDA(REG_PV, REG_RA, d);
 327                 M_ALD(REG_RA, REG_SP, 1 * 8);
 328
 329                 /* restore integer argument registers */
 330
 331                 for (p = 0; p < md->paramcount && p < INT_ARG_CNT; p++)
 332                         M_LLD(rd->argintregs[p], REG_SP, (2 + p) * 8);
 333
 334                 /* restore float argument registers */
 335
 336                 for (p = 0; p < md->paramcount && p < FLT_ARG_CNT; p++) {
 337                         t = md->paramtypes[p].type;
 338
 339                         if (IS_FLT_DBL_TYPE(t)) {
 340                                 if (IS_2_WORD_TYPE(t)) {
 341                                         M_DLD(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 342
 343                                 } else {
 344                                         M_FLD(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 345                                 }
 346
 347                         } else {
 348                                 M_DLD(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 349                         }
 350                 }
 351
 352                 M_LDA(REG_SP, REG_SP, (INT_ARG_CNT + FLT_ARG_CNT + 2) * 8);
 353         }
 354
 355         }
 356
 357         /* end of header generation */
 358
 359         /* walk through all basic blocks */
 360
 361         for (bptr = m->basicblocks; bptr != NULL; bptr = bptr->next) {
 362
 363                 bptr->mpc = (s4) ((u1 *) mcodeptr - cd->mcodebase);
 364
 365                 if (bptr->flags >= BBREACHED) {
 366
 367                 /* branch resolving */
 368
 369                 {
 370                 branchref *brefs;
 371                 for (brefs = bptr->branchrefs; brefs != NULL; brefs = brefs->next) {
 372                         gen_resolvebranch((u1*) cd->mcodebase + brefs->branchpos,
 373                                           brefs->branchpos, bptr->mpc);
 374                         }
 375                 }
 376
 377                 /* copy interface registers to their destination */
 378
 379                 src = bptr->instack;
 380                 len = bptr->indepth;
 381                 MCODECHECK(64+len);
 382 #ifdef LSRA
 383                 if (opt_lsra) {
 384                 while (src != NULL) {
 385                         len--;
 386                         if ((len == 0) && (bptr->type != BBTYPE_STD)) {
 387                                         /*                              d = reg_of_var(m, src, REG_ITMP1); */
 388                                         if (!(src->flags & INMEMORY))
 389                                                 d= src->regoff;
 390                                         else
 391                                                 d=REG_ITMP1;
 392                                         M_INTMOVE(REG_ITMP1, d);
 393                                         store_reg_to_var_int(src, d);
 394                                 }
 395                                 src = src->prev;
 396                         }
 397                 } else {
 398 #endif
 399                         while (src != NULL) {
 400                                 len--;
 401                                 if ((len == 0) && (bptr->type != BBTYPE_STD)) {
 402                                 d = reg_of_var(rd, src, REG_ITMP1);
 403                                 M_INTMOVE(REG_ITMP1, d);
 404                                 store_reg_to_var_int(src, d);
 405                                 }
 406                         else {
 407                                 d = reg_of_var(rd, src, REG_IFTMP);
 408                                 if ((src->varkind != STACKVAR)) {
 409                                         s2 = src->type;
 410                                         if (IS_FLT_DBL_TYPE(s2)) {
 411                                                 if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
 412                                                         s1 = rd->interfaces[len][s2].regoff;
 413                                                         M_FLTMOVE(s1,d);
 414                                                         }
 415                                                 else {
 416                                                         M_DLD(d, REG_SP, 8 * rd->interfaces[len][s2].regoff);
 417                                                         }
 418                                                 store_reg_to_var_flt(src, d);
 419                                                 }
 420                                         else {
 421                                                 if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
 422                                                         s1 = rd->interfaces[len][s2].regoff;
 423                                                         M_INTMOVE(s1,d);
 424                                                         }
 425                                                 else {
 426                                                         M_LLD(d, REG_SP, 8 * rd->interfaces[len][s2].regoff);
 427                                                         }
 428                                                 store_reg_to_var_int(src, d);
 429                                                 }
 430                                         }
 431                                 }
 432                         src = src->prev;
 433                         }
 434 #ifdef LSRA
 435                 }
 436 #endif
 437
 438                 /* walk through all instructions */
 439
 440                 src = bptr->instack;
 441                 len = bptr->icount;
 442
 443                 for (iptr = bptr->iinstr; len > 0; src = iptr->dst, len--, iptr++) {
 444                         if (iptr->line != currentline) {
 445                                 dseg_addlinenumber(cd, iptr->line, mcodeptr);
 446                                 currentline = iptr->line;
 447                         }
 448
 449                 MCODECHECK(64);       /* an instruction usually needs < 64 words      */
 450                 switch (iptr->opc) {
 451
 452                 case ICMD_INLINE_START:
 453                 case ICMD_INLINE_END:
 454                         break;
 455
 456                 case ICMD_NOP:        /* ...  ==> ...                                 */
 457                         break;
 458
 459                 case ICMD_CHECKNULL:  /* ..., objectref  ==> ..., objectref           */
 460
 461                         var_to_reg_int(s1, src, REG_ITMP1);
 462                         M_BEQZ(s1, 0);
 463                         codegen_addxnullrefs(cd, mcodeptr);
 464                         break;
 465
 466                 /* constant operations ************************************************/
 467
 468                 case ICMD_ICONST:     /* ...  ==> ..., constant                       */
 469                                       /* op1 = 0, val.i = constant                    */
 470
 471                         d = reg_of_var(rd, iptr->dst, REG_ITMP1);
 472                         ICONST(d, iptr->val.i);
 473                         store_reg_to_var_int(iptr->dst, d);
 474                         break;
 475
 476                 case ICMD_LCONST:     /* ...  ==> ..., constant                       */
 477                                       /* op1 = 0, val.l = constant                    */
 478
 479                         d = reg_of_var(rd, iptr->dst, REG_ITMP1);
 480                         LCONST(d, iptr->val.l);
 481                         store_reg_to_var_int(iptr->dst, d);
 482                         break;
 483
 484                 case ICMD_FCONST:     /* ...  ==> ..., constant                       */
 485                                       /* op1 = 0, val.f = constant                    */
 486
 487                         d = reg_of_var(rd, iptr->dst, REG_FTMP1);
 488                         a = dseg_addfloat(cd, iptr->val.f);
 489                         M_FLD(d, REG_PV, a);
 490                         store_reg_to_var_flt(iptr->dst, d);
 491                         break;
 492
 493                 case ICMD_DCONST:     /* ...  ==> ..., constant                       */
 494                                       /* op1 = 0, val.d = constant                    */
 495
 496                         d = reg_of_var(rd, iptr->dst, REG_FTMP1);
 497                         a = dseg_adddouble(cd, iptr->val.d);
 498                         M_DLD(d, REG_PV, a);
 499                         store_reg_to_var_flt(iptr->dst, d);
 500                         break;
 501
 502                 case ICMD_ACONST:     /* ...  ==> ..., constant                       */
 503                                       /* op1 = 0, val.a = constant                    */
 504
 505                         d = reg_of_var(rd, iptr->dst, REG_ITMP1);
 506                         if (iptr->val.a) {
 507                                 a = dseg_addaddress(cd, iptr->val.a);
 508                                 M_ALD(d, REG_PV, a);
 509                         } else {
 510                                 M_INTMOVE(REG_ZERO, d);
 511                         }
 512                         store_reg_to_var_int(iptr->dst, d);
 513                         break;
 514
 515
 516                 /* load/store operations **********************************************/
 517
 518                 case ICMD_ILOAD:      /* ...  ==> ..., content of local variable      */
 519                 case ICMD_LLOAD:      /* op1 = local variable                         */
 520                 case ICMD_ALOAD:
 521
 522                         d = reg_of_var(rd, iptr->dst, REG_ITMP1);
 523                         if ((iptr->dst->varkind == LOCALVAR) &&
 524                             (iptr->dst->varnum == iptr->op1))
 525                                 break;
 526                         var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
 527                         if (var->flags & INMEMORY)
 528                                 M_LLD(d, REG_SP, 8 * var->regoff);
 529                         else
 530                                 {M_INTMOVE(var->regoff,d);}
 531                         store_reg_to_var_int(iptr->dst, d);
 532                         break;
 533
 534                 case ICMD_FLOAD:      /* ...  ==> ..., content of local variable      */
 535                 case ICMD_DLOAD:      /* op1 = local variable                         */
 536
 537                         d = reg_of_var(rd, iptr->dst, REG_FTMP1);
 538                         if ((iptr->dst->varkind == LOCALVAR) &&
 539                             (iptr->dst->varnum == iptr->op1))
 540                                 break;
 541                         var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
 542                         if (var->flags & INMEMORY)
 543                                 M_DLD(d, REG_SP, 8 * var->regoff);
 544                         else
 545                                 {M_FLTMOVE(var->regoff,d);}
 546                         store_reg_to_var_flt(iptr->dst, d);
 547                         break;
 548
 549
 550                 case ICMD_ISTORE:     /* ..., value  ==> ...                          */
 551                 case ICMD_LSTORE:     /* op1 = local variable                         */
 552                 case ICMD_ASTORE:
 553
 554                         if ((src->varkind == LOCALVAR) &&
 555                             (src->varnum == iptr->op1))
 556                                 break;
 557                         var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
 558                         if (var->flags & INMEMORY) {
 559                                 var_to_reg_int(s1, src, REG_ITMP1);
 560                                 M_LST(s1, REG_SP, 8 * var->regoff);
 561                                 }
 562                         else {
 563                                 var_to_reg_int(s1, src, var->regoff);
 564                                 M_INTMOVE(s1, var->regoff);
 565                                 }
 566                         break;
 567
 568                 case ICMD_FSTORE:     /* ..., value  ==> ...                          */
 569                 case ICMD_DSTORE:     /* op1 = local variable                         */
 570
 571                         if ((src->varkind == LOCALVAR) &&
 572                             (src->varnum == iptr->op1))
 573                                 break;
 574                         var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
 575                         if (var->flags & INMEMORY) {
 576                                 var_to_reg_flt(s1, src, REG_FTMP1);
 577                                 M_DST(s1, REG_SP, 8 * var->regoff);
 578                                 }
 579                         else {
 580                                 var_to_reg_flt(s1, src, var->regoff);
 581                                 M_FLTMOVE(s1, var->regoff);
 582                                 }
 583                         break;
 584
 585
 586                 /* pop/dup/swap operations ********************************************/
 587
 588                 /* attention: double and longs are only one entry in CACAO ICMDs      */
 589
 590                 case ICMD_POP:        /* ..., value  ==> ...                          */
 591                 case ICMD_POP2:       /* ..., value, value  ==> ...                   */
 592                         break;
 593
 594                 case ICMD_DUP:        /* ..., a ==> ..., a, a                         */
 595                         M_COPY(src, iptr->dst);
 596                         break;
 597
 598                 case ICMD_DUP_X1:     /* ..., a, b ==> ..., b, a, b                   */
 599
 600                         M_COPY(src,       iptr->dst);
 601                         M_COPY(src->prev, iptr->dst->prev);
 602                         M_COPY(iptr->dst, iptr->dst->prev->prev);
 603                         break;
 604
 605                 case ICMD_DUP_X2:     /* ..., a, b, c ==> ..., c, a, b, c             */
 606
 607                         M_COPY(src,             iptr->dst);
 608                         M_COPY(src->prev,       iptr->dst->prev);
 609                         M_COPY(src->prev->prev, iptr->dst->prev->prev);
 610                         M_COPY(iptr->dst,       iptr->dst->prev->prev->prev);
 611                         break;
 612
 613                 case ICMD_DUP2:       /* ..., a, b ==> ..., a, b, a, b                */
 614
 615                         M_COPY(src,       iptr->dst);
 616                         M_COPY(src->prev, iptr->dst->prev);
 617                         break;
 618
 619                 case ICMD_DUP2_X1:    /* ..., a, b, c ==> ..., b, c, a, b, c          */
 620
 621                         M_COPY(src,             iptr->dst);
 622                         M_COPY(src->prev,       iptr->dst->prev);
 623                         M_COPY(src->prev->prev, iptr->dst->prev->prev);
 624                         M_COPY(iptr->dst,       iptr->dst->prev->prev->prev);
 625                         M_COPY(iptr->dst->prev, iptr->dst->prev->prev->prev->prev);
 626                         break;
 627
 628                 case ICMD_DUP2_X2:    /* ..., a, b, c, d ==> ..., c, d, a, b, c, d    */
 629
 630                         M_COPY(src,                   iptr->dst);
 631                         M_COPY(src->prev,             iptr->dst->prev);
 632                         M_COPY(src->prev->prev,       iptr->dst->prev->prev);
 633                         M_COPY(src->prev->prev->prev, iptr->dst->prev->prev->prev);
 634                         M_COPY(iptr->dst,             iptr->dst->prev->prev->prev->prev);
 635                         M_COPY(iptr->dst->prev,       iptr->dst->prev->prev->prev->prev->prev);
 636                         break;
 637
 638                 case ICMD_SWAP:       /* ..., a, b ==> ..., b, a                      */
 639
 640                         M_COPY(src,       iptr->dst->prev);
 641                         M_COPY(src->prev, iptr->dst);
 642                         break;
 643
 644
 645                 /* integer operations *************************************************/
 646
 647                 case ICMD_INEG:       /* ..., value  ==> ..., - value                 */
 648
 649                         var_to_reg_int(s1, src, REG_ITMP1);
 650                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 651                         M_ISUB(REG_ZERO, s1, d);
 652                         store_reg_to_var_int(iptr->dst, d);
 653                         break;
 654
 655                 case ICMD_LNEG:       /* ..., value  ==> ..., - value                 */
 656
 657                         var_to_reg_int(s1, src, REG_ITMP1);
 658                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 659                         M_LSUB(REG_ZERO, s1, d);
 660                         store_reg_to_var_int(iptr->dst, d);
 661                         break;
 662
 663                 case ICMD_I2L:        /* ..., value  ==> ..., value                   */
 664
 665                         var_to_reg_int(s1, src, REG_ITMP1);
 666                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 667                         M_INTMOVE(s1, d);
 668                         store_reg_to_var_int(iptr->dst, d);
 669                         break;
 670
 671                 case ICMD_L2I:        /* ..., value  ==> ..., value                   */
 672
 673                         var_to_reg_int(s1, src, REG_ITMP1);
 674                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 675                         M_IADD(s1, REG_ZERO, d );
 676                         store_reg_to_var_int(iptr->dst, d);
 677                         break;
 678
 679                 case ICMD_INT2BYTE:   /* ..., value  ==> ..., value                   */
 680
 681                         var_to_reg_int(s1, src, REG_ITMP1);
 682                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 683                         if (has_ext_instr_set) {
 684                                 M_BSEXT(s1, d);
 685                                 }
 686                         else {
 687                                 M_SLL_IMM(s1, 56, d);
 688                                 M_SRA_IMM( d, 56, d);
 689                                 }
 690                         store_reg_to_var_int(iptr->dst, d);
 691                         break;
 692
 693                 case ICMD_INT2CHAR:   /* ..., value  ==> ..., value                   */
 694
 695                         var_to_reg_int(s1, src, REG_ITMP1);
 696                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 697             M_CZEXT(s1, d);
 698                         store_reg_to_var_int(iptr->dst, d);
 699                         break;
 700
 701                 case ICMD_INT2SHORT:  /* ..., value  ==> ..., value                   */
 702
 703                         var_to_reg_int(s1, src, REG_ITMP1);
 704                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 705                         if (has_ext_instr_set) {
 706                                 M_SSEXT(s1, d);
 707                                 }
 708                         else {
 709                                 M_SLL_IMM(s1, 48, d);
 710                                 M_SRA_IMM( d, 48, d);
 711                                 }
 712                         store_reg_to_var_int(iptr->dst, d);
 713                         break;
 714
 715
 716                 case ICMD_IADD:       /* ..., val1, val2  ==> ..., val1 + val2        */
 717
 718                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 719                         var_to_reg_int(s2, src, REG_ITMP2);
 720                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 721                         M_IADD(s1, s2, d);
 722                         store_reg_to_var_int(iptr->dst, d);
 723                         break;
 724
 725                 case ICMD_IADDCONST:  /* ..., value  ==> ..., value + constant        */
 726                                       /* val.i = constant                             */
 727
 728                         var_to_reg_int(s1, src, REG_ITMP1);
 729                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 730                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
 731                                 M_IADD_IMM(s1, iptr->val.i, d);
 732                                 }
 733                         else {
 734                                 ICONST(REG_ITMP2, iptr->val.i);
 735                                 M_IADD(s1, REG_ITMP2, d);
 736                                 }
 737                         store_reg_to_var_int(iptr->dst, d);
 738                         break;
 739
 740                 case ICMD_LADD:       /* ..., val1, val2  ==> ..., val1 + val2        */
 741
 742                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 743                         var_to_reg_int(s2, src, REG_ITMP2);
 744                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 745                         M_LADD(s1, s2, d);
 746                         store_reg_to_var_int(iptr->dst, d);
 747                         break;
 748
 749                 case ICMD_LADDCONST:  /* ..., value  ==> ..., value + constant        */
 750                                       /* val.l = constant                             */
 751
 752                         var_to_reg_int(s1, src, REG_ITMP1);
 753                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 754                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
 755                                 M_LADD_IMM(s1, iptr->val.l, d);
 756                                 }
 757                         else {
 758                                 LCONST(REG_ITMP2, iptr->val.l);
 759                                 M_LADD(s1, REG_ITMP2, d);
 760                                 }
 761                         store_reg_to_var_int(iptr->dst, d);
 762                         break;
 763
 764                 case ICMD_ISUB:       /* ..., val1, val2  ==> ..., val1 - val2        */
 765
 766                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 767                         var_to_reg_int(s2, src, REG_ITMP2);
 768                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 769                         M_ISUB(s1, s2, d);
 770                         store_reg_to_var_int(iptr->dst, d);
 771                         break;
 772
 773                 case ICMD_ISUBCONST:  /* ..., value  ==> ..., value + constant        */
 774                                       /* val.i = constant                             */
 775
 776                         var_to_reg_int(s1, src, REG_ITMP1);
 777                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 778                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
 779                                 M_ISUB_IMM(s1, iptr->val.i, d);
 780                                 }
 781                         else {
 782                                 ICONST(REG_ITMP2, iptr->val.i);
 783                                 M_ISUB(s1, REG_ITMP2, d);
 784                                 }
 785                         store_reg_to_var_int(iptr->dst, d);
 786                         break;
 787
 788                 case ICMD_LSUB:       /* ..., val1, val2  ==> ..., val1 - val2        */
 789
 790                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 791                         var_to_reg_int(s2, src, REG_ITMP2);
 792                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 793                         M_LSUB(s1, s2, d);
 794                         store_reg_to_var_int(iptr->dst, d);
 795                         break;
 796
 797                 case ICMD_LSUBCONST:  /* ..., value  ==> ..., value - constant        */
 798                                       /* val.l = constant                             */
 799
 800                         var_to_reg_int(s1, src, REG_ITMP1);
 801                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 802                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
 803                                 M_LSUB_IMM(s1, iptr->val.l, d);
 804                                 }
 805                         else {
 806                                 LCONST(REG_ITMP2, iptr->val.l);
 807                                 M_LSUB(s1, REG_ITMP2, d);
 808                                 }
 809                         store_reg_to_var_int(iptr->dst, d);
 810                         break;
 811
 812                 case ICMD_IMUL:       /* ..., val1, val2  ==> ..., val1 * val2        */
 813
 814                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 815                         var_to_reg_int(s2, src, REG_ITMP2);
 816                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 817                         M_IMUL(s1, s2, d);
 818                         store_reg_to_var_int(iptr->dst, d);
 819                         break;
 820
 821                 case ICMD_IMULCONST:  /* ..., value  ==> ..., value * constant        */
 822                                       /* val.i = constant                             */
 823
 824                         var_to_reg_int(s1, src, REG_ITMP1);
 825                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 826                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
 827                                 M_IMUL_IMM(s1, iptr->val.i, d);
 828                                 }
 829                         else {
 830                                 ICONST(REG_ITMP2, iptr->val.i);
 831                                 M_IMUL(s1, REG_ITMP2, d);
 832                                 }
 833                         store_reg_to_var_int(iptr->dst, d);
 834                         break;
 835
 836                 case ICMD_LMUL:       /* ..., val1, val2  ==> ..., val1 * val2        */
 837
 838                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 839                         var_to_reg_int(s2, src, REG_ITMP2);
 840                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 841                         M_LMUL (s1, s2, d);
 842                         store_reg_to_var_int(iptr->dst, d);
 843                         break;
 844
 845                 case ICMD_LMULCONST:  /* ..., value  ==> ..., value * constant        */
 846                                       /* val.l = constant                             */
 847
 848                         var_to_reg_int(s1, src, REG_ITMP1);
 849                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 850                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
 851                                 M_LMUL_IMM(s1, iptr->val.l, d);
 852                                 }
 853                         else {
 854                                 LCONST(REG_ITMP2, iptr->val.l);
 855                                 M_LMUL(s1, REG_ITMP2, d);
 856                                 }
 857                         store_reg_to_var_int(iptr->dst, d);
 858                         break;
 859
 860                 case ICMD_IDIVPOW2:   /* ..., value  ==> ..., value << constant       */
 861                 case ICMD_LDIVPOW2:   /* val.i = constant                             */
 862
 863                         var_to_reg_int(s1, src, REG_ITMP1);
 864                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 865                         if (iptr->val.i <= 15) {
 866                                 M_LDA(REG_ITMP2, s1, (1 << iptr->val.i) -1);
 867                                 M_CMOVGE(s1, s1, REG_ITMP2);
 868                                 }
 869                         else {
 870                                 M_SRA_IMM(s1, 63, REG_ITMP2);
 871                                 M_SRL_IMM(REG_ITMP2, 64 - iptr->val.i, REG_ITMP2);
 872                                 M_LADD(s1, REG_ITMP2, REG_ITMP2);
 873                                 }
 874                         M_SRA_IMM(REG_ITMP2, iptr->val.i, d);
 875                         store_reg_to_var_int(iptr->dst, d);
 876                         break;
 877
 878                 case ICMD_ISHL:       /* ..., val1, val2  ==> ..., val1 << val2       */
 879
 880                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 881                         var_to_reg_int(s2, src, REG_ITMP2);
 882                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 883                         M_AND_IMM(s2, 0x1f, REG_ITMP3);
 884                         M_SLL(s1, REG_ITMP3, d);
 885                         M_IADD(d, REG_ZERO, d);
 886                         store_reg_to_var_int(iptr->dst, d);
 887                         break;
 888
 889                 case ICMD_ISHLCONST:  /* ..., value  ==> ..., value << constant       */
 890                                       /* val.i = constant                             */
 891
 892                         var_to_reg_int(s1, src, REG_ITMP1);
 893                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 894                         M_SLL_IMM(s1, iptr->val.i & 0x1f, d);
 895                         M_IADD(d, REG_ZERO, d);
 896                         store_reg_to_var_int(iptr->dst, d);
 897                         break;
 898
 899                 case ICMD_ISHR:       /* ..., val1, val2  ==> ..., val1 >> val2       */
 900
 901                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 902                         var_to_reg_int(s2, src, REG_ITMP2);
 903                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 904                         M_AND_IMM(s2, 0x1f, REG_ITMP3);
 905                         M_SRA(s1, REG_ITMP3, d);
 906                         store_reg_to_var_int(iptr->dst, d);
 907                         break;
 908
 909                 case ICMD_ISHRCONST:  /* ..., value  ==> ..., value >> constant       */
 910                                       /* val.i = constant                             */
 911
 912                         var_to_reg_int(s1, src, REG_ITMP1);
 913                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 914                         M_SRA_IMM(s1, iptr->val.i & 0x1f, d);
 915                         store_reg_to_var_int(iptr->dst, d);
 916                         break;
 917
 918                 case ICMD_IUSHR:      /* ..., val1, val2  ==> ..., val1 >>> val2      */
 919
 920                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 921                         var_to_reg_int(s2, src, REG_ITMP2);
 922                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 923                         M_AND_IMM(s2, 0x1f, REG_ITMP2);
 924             M_IZEXT(s1, d);
 925                         M_SRL(d, REG_ITMP2, d);
 926                         M_IADD(d, REG_ZERO, d);
 927                         store_reg_to_var_int(iptr->dst, d);
 928                         break;
 929
 930                 case ICMD_IUSHRCONST: /* ..., value  ==> ..., value >>> constant      */
 931                                       /* val.i = constant                             */
 932
 933                         var_to_reg_int(s1, src, REG_ITMP1);
 934                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 935             M_IZEXT(s1, d);
 936                         M_SRL_IMM(d, iptr->val.i & 0x1f, d);
 937                         M_IADD(d, REG_ZERO, d);
 938                         store_reg_to_var_int(iptr->dst, d);
 939                         break;
 940
 941                 case ICMD_LSHL:       /* ..., val1, val2  ==> ..., val1 << val2       */
 942
 943                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 944                         var_to_reg_int(s2, src, REG_ITMP2);
 945                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 946                         M_SLL(s1, s2, d);
 947                         store_reg_to_var_int(iptr->dst, d);
 948                         break;
 949
 950                 case ICMD_LSHLCONST:  /* ..., value  ==> ..., value << constant       */
 951                                       /* val.i = constant                             */
 952
 953                         var_to_reg_int(s1, src, REG_ITMP1);
 954                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 955                         M_SLL_IMM(s1, iptr->val.i & 0x3f, d);
 956                         store_reg_to_var_int(iptr->dst, d);
 957                         break;
 958
 959                 case ICMD_LSHR:       /* ..., val1, val2  ==> ..., val1 >> val2       */
 960
 961                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 962                         var_to_reg_int(s2, src, REG_ITMP2);
 963                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 964                         M_SRA(s1, s2, d);
 965                         store_reg_to_var_int(iptr->dst, d);
 966                         break;
 967
 968                 case ICMD_LSHRCONST:  /* ..., value  ==> ..., value >> constant       */
 969                                       /* val.i = constant                             */
 970
 971                         var_to_reg_int(s1, src, REG_ITMP1);
 972                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 973                         M_SRA_IMM(s1, iptr->val.i & 0x3f, d);
 974                         store_reg_to_var_int(iptr->dst, d);
 975                         break;
 976
 977                 case ICMD_LUSHR:      /* ..., val1, val2  ==> ..., val1 >>> val2      */
 978
 979                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 980                         var_to_reg_int(s2, src, REG_ITMP2);
 981                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 982                         M_SRL(s1, s2, d);
 983                         store_reg_to_var_int(iptr->dst, d);
 984                         break;
 985
 986                 case ICMD_LUSHRCONST: /* ..., value  ==> ..., value >>> constant      */
 987                                       /* val.i = constant                             */
 988
 989                         var_to_reg_int(s1, src, REG_ITMP1);
 990                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
 991                         M_SRL_IMM(s1, iptr->val.i & 0x3f, d);
 992                         store_reg_to_var_int(iptr->dst, d);
 993                         break;
 994
 995                 case ICMD_IAND:       /* ..., val1, val2  ==> ..., val1 & val2        */
 996                 case ICMD_LAND:
 997
 998                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 999                         var_to_reg_int(s2, src, REG_ITMP2);
1000                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1001                         M_AND(s1, s2, d);
1002                         store_reg_to_var_int(iptr->dst, d);
1003                         break;
1004
1005                 case ICMD_IANDCONST:  /* ..., value  ==> ..., value & constant        */
1006                                       /* val.i = constant                             */
1007
1008                         var_to_reg_int(s1, src, REG_ITMP1);
1009                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1010                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
1011                                 M_AND_IMM(s1, iptr->val.i, d);
1012                                 }
1013                         else if (iptr->val.i == 0xffff) {
1014                                 M_CZEXT(s1, d);
1015                                 }
1016                         else if (iptr->val.i == 0xffffff) {
1017                                 M_ZAPNOT_IMM(s1, 0x07, d);
1018                                 }
1019                         else {
1020                                 ICONST(REG_ITMP2, iptr->val.i);
1021                                 M_AND(s1, REG_ITMP2, d);
1022                                 }
1023                         store_reg_to_var_int(iptr->dst, d);
1024                         break;
1025
1026                 case ICMD_IREMPOW2:   /* ..., value  ==> ..., value % constant        */
1027                                       /* val.i = constant                             */
1028
1029                         var_to_reg_int(s1, src, REG_ITMP1);
1030                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1031                         if (s1 == d) {
1032                                 M_MOV(s1, REG_ITMP1);
1033                                 s1 = REG_ITMP1;
1034                                 }
1035                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
1036                                 M_AND_IMM(s1, iptr->val.i, d);
1037                                 M_BGEZ(s1, 3);
1038                                 M_ISUB(REG_ZERO, s1, d);
1039                                 M_AND_IMM(d, iptr->val.i, d);
1040                                 }
1041                         else if (iptr->val.i == 0xffff) {
1042                                 M_CZEXT(s1, d);
1043                                 M_BGEZ(s1, 3);
1044                                 M_ISUB(REG_ZERO, s1, d);
1045                                 M_CZEXT(d, d);
1046                                 }
1047                         else if (iptr->val.i == 0xffffff) {
1048                                 M_ZAPNOT_IMM(s1, 0x07, d);
1049                                 M_BGEZ(s1, 3);
1050                                 M_ISUB(REG_ZERO, s1, d);
1051                                 M_ZAPNOT_IMM(d, 0x07, d);
1052                                 }
1053                         else {
1054                                 ICONST(REG_ITMP2, iptr->val.i);
1055                                 M_AND(s1, REG_ITMP2, d);
1056                                 M_BGEZ(s1, 3);
1057                                 M_ISUB(REG_ZERO, s1, d);
1058                                 M_AND(d, REG_ITMP2, d);
1059                                 }
1060                         M_ISUB(REG_ZERO, d, d);
1061                         store_reg_to_var_int(iptr->dst, d);
1062                         break;
1063
1064                 case ICMD_LANDCONST:  /* ..., value  ==> ..., value & constant        */
1065                                       /* val.l = constant                             */
1066
1067                         var_to_reg_int(s1, src, REG_ITMP1);
1068                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1069                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
1070                                 M_AND_IMM(s1, iptr->val.l, d);
1071                                 }
1072                         else if (iptr->val.l == 0xffffL) {
1073                                 M_CZEXT(s1, d);
1074                                 }
1075                         else if (iptr->val.l == 0xffffffL) {
1076                                 M_ZAPNOT_IMM(s1, 0x07, d);
1077                                 }
1078                         else if (iptr->val.l == 0xffffffffL) {
1079                                 M_IZEXT(s1, d);
1080                                 }
1081                         else if (iptr->val.l == 0xffffffffffL) {
1082                                 M_ZAPNOT_IMM(s1, 0x1f, d);
1083                                 }
1084                         else if (iptr->val.l == 0xffffffffffffL) {
1085                                 M_ZAPNOT_IMM(s1, 0x3f, d);
1086                                 }
1087                         else if (iptr->val.l == 0xffffffffffffffL) {
1088                                 M_ZAPNOT_IMM(s1, 0x7f, d);
1089                                 }
1090                         else {
1091                                 LCONST(REG_ITMP2, iptr->val.l);
1092                                 M_AND(s1, REG_ITMP2, d);
1093                                 }
1094                         store_reg_to_var_int(iptr->dst, d);
1095                         break;
1096
1097                 case ICMD_LREMPOW2:   /* ..., value  ==> ..., value % constant        */
1098                                       /* val.l = constant                             */
1099
1100                         var_to_reg_int(s1, src, REG_ITMP1);
1101                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1102                         if (s1 == d) {
1103                                 M_MOV(s1, REG_ITMP1);
1104                                 s1 = REG_ITMP1;
1105                                 }
1106                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
1107                                 M_AND_IMM(s1, iptr->val.l, d);
1108                                 M_BGEZ(s1, 3);
1109                                 M_LSUB(REG_ZERO, s1, d);
1110                                 M_AND_IMM(d, iptr->val.l, d);
1111                                 }
1112                         else if (iptr->val.l == 0xffffL) {
1113                                 M_CZEXT(s1, d);
1114                                 M_BGEZ(s1, 3);
1115                                 M_LSUB(REG_ZERO, s1, d);
1116                                 M_CZEXT(d, d);
1117                                 }
1118                         else if (iptr->val.l == 0xffffffL) {
1119                                 M_ZAPNOT_IMM(s1, 0x07, d);
1120                                 M_BGEZ(s1, 3);
1121                                 M_LSUB(REG_ZERO, s1, d);
1122                                 M_ZAPNOT_IMM(d, 0x07, d);
1123                                 }
1124                         else if (iptr->val.l == 0xffffffffL) {
1125                                 M_IZEXT(s1, d);
1126                                 M_BGEZ(s1, 3);
1127                                 M_LSUB(REG_ZERO, s1, d);
1128                                 M_IZEXT(d, d);
1129                                 }
1130                         else if (iptr->val.l == 0xffffffffffL) {
1131                                 M_ZAPNOT_IMM(s1, 0x1f, d);
1132                                 M_BGEZ(s1, 3);
1133                                 M_LSUB(REG_ZERO, s1, d);
1134                                 M_ZAPNOT_IMM(d, 0x1f, d);
1135                                 }
1136                         else if (iptr->val.l == 0xffffffffffffL) {
1137                                 M_ZAPNOT_IMM(s1, 0x3f, d);
1138                                 M_BGEZ(s1, 3);
1139                                 M_LSUB(REG_ZERO, s1, d);
1140                                 M_ZAPNOT_IMM(d, 0x3f, d);
1141                                 }
1142                         else if (iptr->val.l == 0xffffffffffffffL) {
1143                                 M_ZAPNOT_IMM(s1, 0x7f, d);
1144                                 M_BGEZ(s1, 3);
1145                                 M_LSUB(REG_ZERO, s1, d);
1146                                 M_ZAPNOT_IMM(d, 0x7f, d);
1147                                 }
1148                         else {
1149                                 LCONST(REG_ITMP2, iptr->val.l);
1150                                 M_AND(s1, REG_ITMP2, d);
1151                                 M_BGEZ(s1, 3);
1152                                 M_LSUB(REG_ZERO, s1, d);
1153                                 M_AND(d, REG_ITMP2, d);
1154                                 }
1155                         M_LSUB(REG_ZERO, d, d);
1156                         store_reg_to_var_int(iptr->dst, d);
1157                         break;
1158
1159                 case ICMD_IOR:        /* ..., val1, val2  ==> ..., val1 | val2        */
1160                 case ICMD_LOR:
1161
1162                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1163                         var_to_reg_int(s2, src, REG_ITMP2);
1164                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1165                         M_OR( s1,s2, d);
1166                         store_reg_to_var_int(iptr->dst, d);
1167                         break;
1168
1169                 case ICMD_IORCONST:   /* ..., value  ==> ..., value | constant        */
1170                                       /* val.i = constant                             */
1171
1172                         var_to_reg_int(s1, src, REG_ITMP1);
1173                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1174                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
1175                                 M_OR_IMM(s1, iptr->val.i, d);
1176                                 }
1177                         else {
1178                                 ICONST(REG_ITMP2, iptr->val.i);
1179                                 M_OR(s1, REG_ITMP2, d);
1180                                 }
1181                         store_reg_to_var_int(iptr->dst, d);
1182                         break;
1183
1184                 case ICMD_LORCONST:   /* ..., value  ==> ..., value | constant        */
1185                                       /* val.l = constant                             */
1186
1187                         var_to_reg_int(s1, src, REG_ITMP1);
1188                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1189                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
1190                                 M_OR_IMM(s1, iptr->val.l, d);
1191                                 }
1192                         else {
1193                                 LCONST(REG_ITMP2, iptr->val.l);
1194                                 M_OR(s1, REG_ITMP2, d);
1195                                 }
1196                         store_reg_to_var_int(iptr->dst, d);
1197                         break;
1198
1199                 case ICMD_IXOR:       /* ..., val1, val2  ==> ..., val1 ^ val2        */
1200                 case ICMD_LXOR:
1201
1202                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1203                         var_to_reg_int(s2, src, REG_ITMP2);
1204                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1205                         M_XOR(s1, s2, d);
1206                         store_reg_to_var_int(iptr->dst, d);
1207                         break;
1208
1209                 case ICMD_IXORCONST:  /* ..., value  ==> ..., value ^ constant        */
1210                                       /* val.i = constant                             */
1211
1212                         var_to_reg_int(s1, src, REG_ITMP1);
1213                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1214                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
1215                                 M_XOR_IMM(s1, iptr->val.i, d);
1216                                 }
1217                         else {
1218                                 ICONST(REG_ITMP2, iptr->val.i);
1219                                 M_XOR(s1, REG_ITMP2, d);
1220                                 }
1221                         store_reg_to_var_int(iptr->dst, d);
1222                         break;
1223
1224                 case ICMD_LXORCONST:  /* ..., value  ==> ..., value ^ constant        */
1225                                       /* val.l = constant                             */
1226
1227                         var_to_reg_int(s1, src, REG_ITMP1);
1228                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1229                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
1230                                 M_XOR_IMM(s1, iptr->val.l, d);
1231                                 }
1232                         else {
1233                                 LCONST(REG_ITMP2, iptr->val.l);
1234                                 M_XOR(s1, REG_ITMP2, d);
1235                                 }
1236                         store_reg_to_var_int(iptr->dst, d);
1237                         break;
1238
1239
1240                 case ICMD_LCMP:       /* ..., val1, val2  ==> ..., val1 cmp val2      */
1241
1242                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1243                         var_to_reg_int(s2, src, REG_ITMP2);
1244                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1245                         M_CMPLT(s1, s2, REG_ITMP3);
1246                         M_CMPLT(s2, s1, REG_ITMP1);
1247                         M_LSUB (REG_ITMP1, REG_ITMP3, d);
1248                         store_reg_to_var_int(iptr->dst, d);
1249                         break;
1250
1251
1252                 case ICMD_IINC:       /* ..., value  ==> ..., value + constant        */
1253                                       /* op1 = variable, val.i = constant             */
1254
1255                         var = &(rd->locals[iptr->op1][TYPE_INT]);
1256                         if (var->flags & INMEMORY) {
1257                                 s1 = REG_ITMP1;
1258                                 M_LLD(s1, REG_SP, 8 * var->regoff);
1259                                 }
1260                         else
1261                                 s1 = var->regoff;
1262                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
1263                                 M_IADD_IMM(s1, iptr->val.i, s1);
1264                                 }
1265                         else if ((iptr->val.i > -256) && (iptr->val.i < 0)) {
1266                                 M_ISUB_IMM(s1, (-iptr->val.i), s1);
1267                                 }
1268                         else {
1269                                 M_LDA (s1, s1, iptr->val.i);
1270                                 M_IADD(s1, REG_ZERO, s1);
1271                                 }
1272                         if (var->flags & INMEMORY)
1273                                 M_LST(s1, REG_SP, 8 * var->regoff);
1274                         break;
1275
1276
1277                 /* floating operations ************************************************/
1278
1279                 case ICMD_FNEG:       /* ..., value  ==> ..., - value                 */
1280
1281                         var_to_reg_flt(s1, src, REG_FTMP1);
1282                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1283                         M_FMOVN(s1, d);
1284                         store_reg_to_var_flt(iptr->dst, d);
1285                         break;
1286
1287                 case ICMD_DNEG:       /* ..., value  ==> ..., - value                 */
1288
1289                         var_to_reg_flt(s1, src, REG_FTMP1);
1290                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1291                         M_FMOVN(s1, d);
1292                         store_reg_to_var_flt(iptr->dst, d);
1293                         break;
1294
1295                 case ICMD_FADD:       /* ..., val1, val2  ==> ..., val1 + val2        */
1296
1297                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1298                         var_to_reg_flt(s2, src, REG_FTMP2);
1299                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1300                         if (opt_noieee) {
1301                                 M_FADD(s1, s2, d);
1302                                 }
1303                         else {
1304                                 if (d == s1 || d == s2) {
1305                                         M_FADDS(s1, s2, REG_FTMP3);
1306                                         M_TRAPB;
1307                                         M_FMOV(REG_FTMP3, d);
1308                                         }
1309                                 else {
1310                                         M_FADDS(s1, s2, d);
1311                                         M_TRAPB;
1312                                         }
1313                                 }
1314                         store_reg_to_var_flt(iptr->dst, d);
1315                         break;
1316
1317                 case ICMD_DADD:       /* ..., val1, val2  ==> ..., val1 + val2        */
1318
1319                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1320                         var_to_reg_flt(s2, src, REG_FTMP2);
1321                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1322                         if (opt_noieee) {
1323                                 M_DADD(s1, s2, d);
1324                                 }
1325                         else {
1326                                 if (d == s1 || d == s2) {
1327                                         M_DADDS(s1, s2, REG_FTMP3);
1328                                         M_TRAPB;
1329                                         M_FMOV(REG_FTMP3, d);
1330                                         }
1331                                 else {
1332                                         M_DADDS(s1, s2, d);
1333                                         M_TRAPB;
1334                                         }
1335                                 }
1336                         store_reg_to_var_flt(iptr->dst, d);
1337                         break;
1338
1339                 case ICMD_FSUB:       /* ..., val1, val2  ==> ..., val1 - val2        */
1340
1341                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1342                         var_to_reg_flt(s2, src, REG_FTMP2);
1343                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1344                         if (opt_noieee) {
1345                                 M_FSUB(s1, s2, d);
1346                                 }
1347                         else {
1348                                 if (d == s1 || d == s2) {
1349                                         M_FSUBS(s1, s2, REG_FTMP3);
1350                                         M_TRAPB;
1351                                         M_FMOV(REG_FTMP3, d);
1352                                         }
1353                                 else {
1354                                         M_FSUBS(s1, s2, d);
1355                                         M_TRAPB;
1356                                         }
1357                                 }
1358                         store_reg_to_var_flt(iptr->dst, d);
1359                         break;
1360
1361                 case ICMD_DSUB:       /* ..., val1, val2  ==> ..., val1 - val2        */
1362
1363                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1364                         var_to_reg_flt(s2, src, REG_FTMP2);
1365                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1366                         if (opt_noieee) {
1367                                 M_DSUB(s1, s2, d);
1368                                 }
1369                         else {
1370                                 if (d == s1 || d == s2) {
1371                                         M_DSUBS(s1, s2, REG_FTMP3);
1372                                         M_TRAPB;
1373                                         M_FMOV(REG_FTMP3, d);
1374                                         }
1375                                 else {
1376                                         M_DSUBS(s1, s2, d);
1377                                         M_TRAPB;
1378                                         }
1379                                 }
1380                         store_reg_to_var_flt(iptr->dst, d);
1381                         break;
1382
1383                 case ICMD_FMUL:       /* ..., val1, val2  ==> ..., val1 * val2        */
1384
1385                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1386                         var_to_reg_flt(s2, src, REG_FTMP2);
1387                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1388                         if (opt_noieee) {
1389                                 M_FMUL(s1, s2, d);
1390                                 }
1391                         else {
1392                                 if (d == s1 || d == s2) {
1393                                         M_FMULS(s1, s2, REG_FTMP3);
1394                                         M_TRAPB;
1395                                         M_FMOV(REG_FTMP3, d);
1396                                         }
1397                                 else {
1398                                         M_FMULS(s1, s2, d);
1399                                         M_TRAPB;
1400                                         }
1401                                 }
1402                         store_reg_to_var_flt(iptr->dst, d);
1403                         break;
1404
1405                 case ICMD_DMUL:       /* ..., val1, val2  ==> ..., val1 *** val2        */
1406
1407                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1408                         var_to_reg_flt(s2, src, REG_FTMP2);
1409                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1410                         if (opt_noieee) {
1411                                 M_DMUL(s1, s2, d);
1412                                 }
1413                         else {
1414                                 if (d == s1 || d == s2) {
1415                                         M_DMULS(s1, s2, REG_FTMP3);
1416                                         M_TRAPB;
1417                                         M_FMOV(REG_FTMP3, d);
1418                                         }
1419                                 else {
1420                                         M_DMULS(s1, s2, d);
1421                                         M_TRAPB;
1422                                         }
1423                                 }
1424                         store_reg_to_var_flt(iptr->dst, d);
1425                         break;
1426
1427                 case ICMD_FDIV:       /* ..., val1, val2  ==> ..., val1 / val2        */
1428
1429                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1430                         var_to_reg_flt(s2, src, REG_FTMP2);
1431                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1432                         if (opt_noieee) {
1433                                 M_FDIV(s1, s2, d);
1434                                 }
1435                         else {
1436                                 if (d == s1 || d == s2) {
1437                                         M_FDIVS(s1, s2, REG_FTMP3);
1438                                         M_TRAPB;
1439                                         M_FMOV(REG_FTMP3, d);
1440                                         }
1441                                 else {
1442                                         M_FDIVS(s1, s2, d);
1443                                         M_TRAPB;
1444                                         }
1445                                 }
1446                         store_reg_to_var_flt(iptr->dst, d);
1447                         break;
1448
1449                 case ICMD_DDIV:       /* ..., val1, val2  ==> ..., val1 / val2        */
1450
1451                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1452                         var_to_reg_flt(s2, src, REG_FTMP2);
1453                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1454                         if (opt_noieee) {
1455                                 M_DDIV(s1, s2, d);
1456                                 }
1457                         else {
1458                                 if (d == s1 || d == s2) {
1459                                         M_DDIVS(s1, s2, REG_FTMP3);
1460                                         M_TRAPB;
1461                                         M_FMOV(REG_FTMP3, d);
1462                                         }
1463                                 else {
1464                                         M_DDIVS(s1, s2, d);
1465                                         M_TRAPB;
1466                                         }
1467                                 }
1468                         store_reg_to_var_flt(iptr->dst, d);
1469                         break;
1470
1471                 case ICMD_I2F:       /* ..., value  ==> ..., (float) value            */
1472                 case ICMD_L2F:
1473                         var_to_reg_int(s1, src, REG_ITMP1);
1474                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1475                         a = dseg_adddouble(cd, 0.0);
1476                         M_LST (s1, REG_PV, a);
1477                         M_DLD (d, REG_PV, a);
1478                         M_CVTLF(d, d);
1479                         store_reg_to_var_flt(iptr->dst, d);
1480                         break;
1481
1482                 case ICMD_I2D:       /* ..., value  ==> ..., (double) value           */
1483                 case ICMD_L2D:
1484                         var_to_reg_int(s1, src, REG_ITMP1);
1485                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1486                         a = dseg_adddouble(cd, 0.0);
1487                         M_LST (s1, REG_PV, a);
1488                         M_DLD (d, REG_PV, a);
1489                         M_CVTLD(d, d);
1490                         store_reg_to_var_flt(iptr->dst, d);
1491                         break;
1492
1493                 case ICMD_F2I:       /* ..., value  ==> ..., (int) value              */
1494                 case ICMD_D2I:
1495                         var_to_reg_flt(s1, src, REG_FTMP1);
1496                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1497                         a = dseg_adddouble(cd, 0.0);
1498                         M_CVTDL_C(s1, REG_FTMP2);
1499                         M_CVTLI(REG_FTMP2, REG_FTMP3);
1500                         M_DST (REG_FTMP3, REG_PV, a);
1501                         M_ILD (d, REG_PV, a);
1502                         store_reg_to_var_int(iptr->dst, d);
1503                         break;
1504
1505                 case ICMD_F2L:       /* ..., value  ==> ..., (long) value             */
1506                 case ICMD_D2L:
1507                         var_to_reg_flt(s1, src, REG_FTMP1);
1508                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1509                         a = dseg_adddouble(cd, 0.0);
1510                         M_CVTDL_C(s1, REG_FTMP2);
1511                         M_DST (REG_FTMP2, REG_PV, a);
1512                         M_LLD (d, REG_PV, a);
1513                         store_reg_to_var_int(iptr->dst, d);
1514                         break;
1515
1516                 case ICMD_F2D:       /* ..., value  ==> ..., (double) value           */
1517
1518                         var_to_reg_flt(s1, src, REG_FTMP1);
1519                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1520                         M_CVTFDS(s1, d);
1521                         M_TRAPB;
1522                         store_reg_to_var_flt(iptr->dst, d);
1523                         break;
1524
1525                 case ICMD_D2F:       /* ..., value  ==> ..., (float) value            */
1526
1527                         var_to_reg_flt(s1, src, REG_FTMP1);
1528                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1529                         if (opt_noieee) {
1530                                 M_CVTDF(s1, d);
1531                                 }
1532                         else {
1533                                 M_CVTDFS(s1, d);
1534                                 M_TRAPB;
1535                                 }
1536                         store_reg_to_var_flt(iptr->dst, d);
1537                         break;
1538
1539                 case ICMD_FCMPL:      /* ..., val1, val2  ==> ..., val1 fcmpl val2    */
1540                 case ICMD_DCMPL:
1541                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1542                         var_to_reg_flt(s2, src, REG_FTMP2);
1543                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1544                         if (opt_noieee) {
1545                                 M_LSUB_IMM(REG_ZERO, 1, d);
1546                                 M_FCMPEQ(s1, s2, REG_FTMP3);
1547                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instructions */
1548                                 M_CLR   (d);
1549                                 M_FCMPLT(s2, s1, REG_FTMP3);
1550                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instruction  */
1551                                 M_LADD_IMM(REG_ZERO, 1, d);
1552                                 }
1553                         else {
1554                                 M_LSUB_IMM(REG_ZERO, 1, d);
1555                                 M_FCMPEQS(s1, s2, REG_FTMP3);
1556                                 M_TRAPB;
1557                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instructions */
1558                                 M_CLR   (d);
1559                                 M_FCMPLTS(s2, s1, REG_FTMP3);
1560                                 M_TRAPB;
1561                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instruction  */
1562                                 M_LADD_IMM(REG_ZERO, 1, d);
1563                                 }
1564                         store_reg_to_var_int(iptr->dst, d);
1565                         break;
1566
1567                 case ICMD_FCMPG:      /* ..., val1, val2  ==> ..., val1 fcmpg val2    */
1568                 case ICMD_DCMPG:
1569                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1570                         var_to_reg_flt(s2, src, REG_FTMP2);
1571                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1572                         if (opt_noieee) {
1573                                 M_LADD_IMM(REG_ZERO, 1, d);
1574                                 M_FCMPEQ(s1, s2, REG_FTMP3);
1575                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instruction  */
1576                                 M_CLR   (d);
1577                                 M_FCMPLT(s1, s2, REG_FTMP3);
1578                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instruction  */
1579                                 M_LSUB_IMM(REG_ZERO, 1, d);
1580                                 }
1581                         else {
1582                                 M_LADD_IMM(REG_ZERO, 1, d);
1583                                 M_FCMPEQS(s1, s2, REG_FTMP3);
1584                                 M_TRAPB;
1585                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instruction  */
1586                                 M_CLR   (d);
1587                                 M_FCMPLTS(s1, s2, REG_FTMP3);
1588                                 M_TRAPB;
1589                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instruction  */
1590                                 M_LSUB_IMM(REG_ZERO, 1, d);
1591                                 }
1592                         store_reg_to_var_int(iptr->dst, d);
1593                         break;
1594
1595
1596                 /* memory operations **************************************************/
1597
1598                 case ICMD_ARRAYLENGTH: /* ..., arrayref  ==> ..., length              */
1599
1600                         var_to_reg_int(s1, src, REG_ITMP1);
1601                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1602                         gen_nullptr_check(s1);
1603                         M_ILD(d, s1, OFFSET(java_arrayheader, size));
1604                         store_reg_to_var_int(iptr->dst, d);
1605                         break;
1606
1607                 case ICMD_AALOAD:     /* ..., arrayref, index  ==> ..., value         */
1608
1609                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1610                         var_to_reg_int(s2, src, REG_ITMP2);
1611                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1612                         if (iptr->op1 == 0) {
1613                                 gen_nullptr_check(s1);
1614                                 gen_bound_check;
1615                                 }
1616                         M_SAADDQ(s2, s1, REG_ITMP1);
1617                         M_ALD( d, REG_ITMP1, OFFSET(java_objectarray, data[0]));
1618                         store_reg_to_var_int(iptr->dst, d);
1619                         break;
1620
1621                 case ICMD_LALOAD:     /* ..., arrayref, index  ==> ..., value         */
1622
1623                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1624                         var_to_reg_int(s2, src, REG_ITMP2);
1625                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1626                         if (iptr->op1 == 0) {
1627                                 gen_nullptr_check(s1);
1628                                 gen_bound_check;
1629                                 }
1630                         M_S8ADDQ(s2, s1, REG_ITMP1);
1631                         M_LLD(d, REG_ITMP1, OFFSET(java_longarray, data[0]));
1632                         store_reg_to_var_int(iptr->dst, d);
1633                         break;
1634
1635                 case ICMD_IALOAD:     /* ..., arrayref, index  ==> ..., value         */
1636
1637                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1638                         var_to_reg_int(s2, src, REG_ITMP2);
1639                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1640                         if (iptr->op1 == 0) {
1641                                 gen_nullptr_check(s1);
1642                                 gen_bound_check;
1643                                 }
1644
1645                         M_S4ADDQ(s2, s1, REG_ITMP1);
1646                         M_ILD(d, REG_ITMP1, OFFSET(java_intarray, data[0]));
1647                         store_reg_to_var_int(iptr->dst, d);
1648                         break;
1649
1650                 case ICMD_FALOAD:     /* ..., arrayref, index  ==> ..., value         */
1651
1652                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1653                         var_to_reg_int(s2, src, REG_ITMP2);
1654                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1655                         if (iptr->op1 == 0) {
1656                                 gen_nullptr_check(s1);
1657                                 gen_bound_check;
1658                                 }
1659                         M_S4ADDQ(s2, s1, REG_ITMP1);
1660                         M_FLD(d, REG_ITMP1, OFFSET(java_floatarray, data[0]));
1661                         store_reg_to_var_flt(iptr->dst, d);
1662                         break;
1663
1664                 case ICMD_DALOAD:     /* ..., arrayref, index  ==> ..., value         */
1665
1666                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1667                         var_to_reg_int(s2, src, REG_ITMP2);
1668                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1669                         if (iptr->op1 == 0) {
1670                                 gen_nullptr_check(s1);
1671                                 gen_bound_check;
1672                                 }
1673                         M_S8ADDQ(s2, s1, REG_ITMP1);
1674                         M_DLD(d, REG_ITMP1, OFFSET(java_doublearray, data[0]));
1675                         store_reg_to_var_flt(iptr->dst, d);
1676                         break;
1677
1678                 case ICMD_CALOAD:     /* ..., arrayref, index  ==> ..., value         */
1679
1680                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1681                         var_to_reg_int(s2, src, REG_ITMP2);
1682                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1683                         if (iptr->op1 == 0) {
1684                                 gen_nullptr_check(s1);
1685                                 gen_bound_check;
1686                                 }
1687                         if (has_ext_instr_set) {
1688                                 M_LADD(s2, s1, REG_ITMP1);
1689                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1690                                 M_SLDU(d, REG_ITMP1, OFFSET(java_chararray, data[0]));
1691                                 }
1692                         else {
1693                                 M_LADD (s2, s1, REG_ITMP1);
1694                                 M_LADD (s2, REG_ITMP1, REG_ITMP1);
1695                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_chararray, data[0]));
1696                                 M_LDA  (REG_ITMP1, REG_ITMP1, OFFSET(java_chararray, data[0]));
1697                                 M_EXTWL(REG_ITMP2, REG_ITMP1, d);
1698                                 }
1699                         store_reg_to_var_int(iptr->dst, d);
1700                         break;
1701
1702                 case ICMD_SALOAD:     /* ..., arrayref, index  ==> ..., value         */
1703
1704                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1705                         var_to_reg_int(s2, src, REG_ITMP2);
1706                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1707                         if (iptr->op1 == 0) {
1708                                 gen_nullptr_check(s1);
1709                                 gen_bound_check;
1710                                 }
1711                         if (has_ext_instr_set) {
1712                                 M_LADD(s2, s1, REG_ITMP1);
1713                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1714                                 M_SLDU( d, REG_ITMP1, OFFSET (java_shortarray, data[0]));
1715                                 M_SSEXT(d, d);
1716                                 }
1717                         else {
1718                                 M_LADD(s2, s1, REG_ITMP1);
1719                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1720                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_shortarray, data[0]));
1721                                 M_LDA(REG_ITMP1, REG_ITMP1, OFFSET(java_shortarray, data[0])+2);
1722                                 M_EXTQH(REG_ITMP2, REG_ITMP1, d);
1723                                 M_SRA_IMM(d, 48, d);
1724                                 }
1725                         store_reg_to_var_int(iptr->dst, d);
1726                         break;
1727
1728                 case ICMD_BALOAD:     /* ..., arrayref, index  ==> ..., value         */
1729
1730                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1731                         var_to_reg_int(s2, src, REG_ITMP2);
1732                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1733                         if (iptr->op1 == 0) {
1734                                 gen_nullptr_check(s1);
1735                                 gen_bound_check;
1736                                 }
1737                         if (has_ext_instr_set) {
1738                                 M_LADD   (s2, s1, REG_ITMP1);
1739                                 M_BLDU   (d, REG_ITMP1, OFFSET (java_bytearray, data[0]));
1740                                 M_BSEXT  (d, d);
1741                                 }
1742                         else {
1743                                 M_LADD(s2, s1, REG_ITMP1);
1744                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_bytearray, data[0]));
1745                                 M_LDA(REG_ITMP1, REG_ITMP1, OFFSET(java_bytearray, data[0])+1);
1746                                 M_EXTQH(REG_ITMP2, REG_ITMP1, d);
1747                                 M_SRA_IMM(d, 56, d);
1748                                 }
1749                         store_reg_to_var_int(iptr->dst, d);
1750                         break;
1751
1752
1753                 case ICMD_AASTORE:    /* ..., arrayref, index, value  ==> ...         */
1754
1755                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1756                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1757                         if (iptr->op1 == 0) {
1758                                 gen_nullptr_check(s1);
1759                                 gen_bound_check;
1760                                 }
1761                         var_to_reg_int(s3, src, REG_ITMP3);
1762                         M_SAADDQ(s2, s1, REG_ITMP1);
1763                         M_AST   (s3, REG_ITMP1, OFFSET(java_objectarray, data[0]));
1764                         break;
1765
1766                 case ICMD_LASTORE:    /* ..., arrayref, index, value  ==> ...         */
1767
1768                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1769                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1770                         if (iptr->op1 == 0) {
1771                                 gen_nullptr_check(s1);
1772                                 gen_bound_check;
1773                                 }
1774                         var_to_reg_int(s3, src, REG_ITMP3);
1775                         M_S8ADDQ(s2, s1, REG_ITMP1);
1776                         M_LST   (s3, REG_ITMP1, OFFSET(java_longarray, data[0]));
1777                         break;
1778
1779                 case ICMD_IASTORE:    /* ..., arrayref, index, value  ==> ...         */
1780
1781                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1782                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1783                         if (iptr->op1 == 0) {
1784                                 gen_nullptr_check(s1);
1785                                 gen_bound_check;
1786                                 }
1787
1788                         var_to_reg_int(s3, src, REG_ITMP3);
1789                         M_S4ADDQ(s2, s1, REG_ITMP1);
1790                         M_IST   (s3, REG_ITMP1, OFFSET(java_intarray, data[0]));
1791                         break;
1792
1793                 case ICMD_FASTORE:    /* ..., arrayref, index, value  ==> ...         */
1794
1795                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1796                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1797                         if (iptr->op1 == 0) {
1798                                 gen_nullptr_check(s1);
1799                                 gen_bound_check;
1800                                 }
1801                         var_to_reg_flt(s3, src, REG_FTMP3);
1802                         M_S4ADDQ(s2, s1, REG_ITMP1);
1803                         M_FST   (s3, REG_ITMP1, OFFSET(java_floatarray, data[0]));
1804                         break;
1805
1806                 case ICMD_DASTORE:    /* ..., arrayref, index, value  ==> ...         */
1807
1808                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1809                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1810                         if (iptr->op1 == 0) {
1811                                 gen_nullptr_check(s1);
1812                                 gen_bound_check;
1813                                 }
1814                         var_to_reg_flt(s3, src, REG_FTMP3);
1815                         M_S8ADDQ(s2, s1, REG_ITMP1);
1816                         M_DST   (s3, REG_ITMP1, OFFSET(java_doublearray, data[0]));
1817                         break;
1818
1819                 case ICMD_CASTORE:    /* ..., arrayref, index, value  ==> ...         */
1820
1821                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1822                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1823                         if (iptr->op1 == 0) {
1824                                 gen_nullptr_check(s1);
1825                                 gen_bound_check;
1826                                 }
1827                         var_to_reg_int(s3, src, REG_ITMP3);
1828                         if (has_ext_instr_set) {
1829                                 M_LADD(s2, s1, REG_ITMP1);
1830                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1831                                 M_SST (s3, REG_ITMP1, OFFSET(java_chararray, data[0]));
1832                                 }
1833                         else {
1834                                 M_LADD (s2, s1, REG_ITMP1);
1835                                 M_LADD (s2, REG_ITMP1, REG_ITMP1);
1836                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_chararray, data[0]));
1837                                 M_LDA  (REG_ITMP1, REG_ITMP1, OFFSET(java_chararray, data[0]));
1838                                 M_INSWL(s3, REG_ITMP1, REG_ITMP3);
1839                                 M_MSKWL(REG_ITMP2, REG_ITMP1, REG_ITMP2);
1840                                 M_OR   (REG_ITMP2, REG_ITMP3, REG_ITMP2);
1841                                 M_LST_U(REG_ITMP2, REG_ITMP1, 0);
1842                                 }
1843                         break;
1844
1845                 case ICMD_SASTORE:    /* ..., arrayref, index, value  ==> ...         */
1846
1847                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1848                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1849                         if (iptr->op1 == 0) {
1850                                 gen_nullptr_check(s1);
1851                                 gen_bound_check;
1852                                 }
1853                         var_to_reg_int(s3, src, REG_ITMP3);
1854                         if (has_ext_instr_set) {
1855                                 M_LADD(s2, s1, REG_ITMP1);
1856                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1857                                 M_SST (s3, REG_ITMP1, OFFSET(java_shortarray, data[0]));
1858                                 }
1859                         else {
1860                                 M_LADD (s2, s1, REG_ITMP1);
1861                                 M_LADD (s2, REG_ITMP1, REG_ITMP1);
1862                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_shortarray, data[0]));
1863                                 M_LDA  (REG_ITMP1, REG_ITMP1, OFFSET(java_shortarray, data[0]));
1864                                 M_INSWL(s3, REG_ITMP1, REG_ITMP3);
1865                                 M_MSKWL(REG_ITMP2, REG_ITMP1, REG_ITMP2);
1866                                 M_OR   (REG_ITMP2, REG_ITMP3, REG_ITMP2);
1867                                 M_LST_U(REG_ITMP2, REG_ITMP1, 0);
1868                                 }
1869                         break;
1870
1871                 case ICMD_BASTORE:    /* ..., arrayref, index, value  ==> ...         */
1872
1873                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1874                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1875                         if (iptr->op1 == 0) {
1876                                 gen_nullptr_check(s1);
1877                                 gen_bound_check;
1878                                 }
1879                         var_to_reg_int(s3, src, REG_ITMP3);
1880                         if (has_ext_instr_set) {
1881                                 M_LADD(s2, s1, REG_ITMP1);
1882                                 M_BST (s3, REG_ITMP1, OFFSET(java_bytearray, data[0]));
1883                                 }
1884                         else {
1885                                 M_LADD (s2, s1, REG_ITMP1);
1886                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_bytearray, data[0]));
1887                                 M_LDA  (REG_ITMP1, REG_ITMP1, OFFSET(java_bytearray, data[0]));
1888                                 M_INSBL(s3, REG_ITMP1, REG_ITMP3);
1889                                 M_MSKBL(REG_ITMP2, REG_ITMP1, REG_ITMP2);
1890                                 M_OR   (REG_ITMP2, REG_ITMP3, REG_ITMP2);
1891                                 M_LST_U(REG_ITMP2, REG_ITMP1, 0);
1892                                 }
1893                         break;
1894
1895
1896                 case ICMD_IASTORECONST:   /* ..., arrayref, index  ==> ...            */
1897
1898                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1899                         var_to_reg_int(s2, src, REG_ITMP2);
1900                         if (iptr->op1 == 0) {
1901                                 gen_nullptr_check(s1);
1902                                 gen_bound_check;
1903                         }
1904                         M_S4ADDQ(s2, s1, REG_ITMP1);
1905                         M_IST(REG_ZERO, REG_ITMP1, OFFSET(java_intarray, data[0]));
1906                         break;
1907
1908                 case ICMD_LASTORECONST:   /* ..., arrayref, index  ==> ...            */
1909
1910                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1911                         var_to_reg_int(s2, src, REG_ITMP2);
1912                         if (iptr->op1 == 0) {
1913                                 gen_nullptr_check(s1);
1914                                 gen_bound_check;
1915                         }
1916                         M_S8ADDQ(s2, s1, REG_ITMP1);
1917                         M_LST(REG_ZERO, REG_ITMP1, OFFSET(java_longarray, data[0]));
1918                         break;
1919
1920                 case ICMD_AASTORECONST:   /* ..., arrayref, index  ==> ...            */
1921
1922                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1923                         var_to_reg_int(s2, src, REG_ITMP2);
1924                         if (iptr->op1 == 0) {
1925                                 gen_nullptr_check(s1);
1926                                 gen_bound_check;
1927                         }
1928                         M_SAADDQ(s2, s1, REG_ITMP1);
1929                         M_AST(REG_ZERO, REG_ITMP1, OFFSET(java_objectarray, data[0]));
1930                         break;
1931
1932                 case ICMD_BASTORECONST:   /* ..., arrayref, index  ==> ...            */
1933
1934                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1935                         var_to_reg_int(s2, src, REG_ITMP2);
1936                         if (iptr->op1 == 0) {
1937                                 gen_nullptr_check(s1);
1938                                 gen_bound_check;
1939                         }
1940                         if (has_ext_instr_set) {
1941                                 M_LADD(s2, s1, REG_ITMP1);
1942                                 M_BST(REG_ZERO, REG_ITMP1, OFFSET(java_bytearray, data[0]));
1943
1944                         } else {
1945                                 M_LADD(s2, s1, REG_ITMP1);
1946                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_bytearray, data[0]));
1947                                 M_LDA(REG_ITMP1, REG_ITMP1, OFFSET(java_bytearray, data[0]));
1948                                 M_INSBL(REG_ZERO, REG_ITMP1, REG_ITMP3);
1949                                 M_MSKBL(REG_ITMP2, REG_ITMP1, REG_ITMP2);
1950                                 M_OR(REG_ITMP2, REG_ITMP3, REG_ITMP2);
1951                                 M_LST_U(REG_ITMP2, REG_ITMP1, 0);
1952                         }
1953                         break;
1954
1955                 case ICMD_CASTORECONST:   /* ..., arrayref, index  ==> ...            */
1956
1957                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1958                         var_to_reg_int(s2, src, REG_ITMP2);
1959                         if (iptr->op1 == 0) {
1960                                 gen_nullptr_check(s1);
1961                                 gen_bound_check;
1962                         }
1963                         if (has_ext_instr_set) {
1964                                 M_LADD(s2, s1, REG_ITMP1);
1965                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1966                                 M_SST(REG_ZERO, REG_ITMP1, OFFSET(java_chararray, data[0]));
1967
1968                         } else {
1969                                 M_LADD(s2, s1, REG_ITMP1);
1970                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1971                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_chararray, data[0]));
1972                                 M_LDA(REG_ITMP1, REG_ITMP1, OFFSET(java_chararray, data[0]));
1973                                 M_INSWL(REG_ZERO, REG_ITMP1, REG_ITMP3);
1974                                 M_MSKWL(REG_ITMP2, REG_ITMP1, REG_ITMP2);
1975                                 M_OR(REG_ITMP2, REG_ITMP3, REG_ITMP2);
1976                                 M_LST_U(REG_ITMP2, REG_ITMP1, 0);
1977                         }
1978                         break;
1979
1980                 case ICMD_SASTORECONST:   /* ..., arrayref, index  ==> ...            */
1981
1982                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1983                         var_to_reg_int(s2, src, REG_ITMP2);
1984                         if (iptr->op1 == 0) {
1985                                 gen_nullptr_check(s1);
1986                                 gen_bound_check;
1987                         }
1988                         if (has_ext_instr_set) {
1989                                 M_LADD(s2, s1, REG_ITMP1);
1990                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1991                                 M_SST(REG_ZERO, REG_ITMP1, OFFSET(java_shortarray, data[0]));
1992
1993                         } else {
1994                                 M_LADD(s2, s1, REG_ITMP1);
1995                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1996                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_shortarray, data[0]));
1997                                 M_LDA(REG_ITMP1, REG_ITMP1, OFFSET(java_shortarray, data[0]));
1998                                 M_INSWL(REG_ZERO, REG_ITMP1, REG_ITMP3);
1999                                 M_MSKWL(REG_ITMP2, REG_ITMP1, REG_ITMP2);
2000                                 M_OR(REG_ITMP2, REG_ITMP3, REG_ITMP2);
2001                                 M_LST_U(REG_ITMP2, REG_ITMP1, 0);
2002                         }
2003                         break;
2004
2005
2006                 case ICMD_GETSTATIC:  /* ...  ==> ..., value                          */
2007                                       /* op1 = type, val.a = field address            */
2008
2009                         if (!iptr->val.a) {
2010                                 codegen_addpatchref(cd, mcodeptr,
2011                                                                         PATCHER_get_putstatic,
2012                                                                         (unresolved_field *) iptr->target);
2013
2014                                 if (showdisassemble)
2015                                         M_NOP;
2016
2017                                 a = 0;
2018
2019                         } else {
2020                                 fieldinfo *fi = iptr->val.a;
2021
2022                                 if (!fi->class->initialized) {
2023                                         codegen_addpatchref(cd, mcodeptr,
2024                                                                                 PATCHER_clinit, fi->class);
2025
2026                                         if (showdisassemble)
2027                                                 M_NOP;
2028                                 }
2029
2030                                 a = (ptrint) &(fi->value);
2031                         }
2032
2033                         a = dseg_addaddress(cd, a);
2034                         M_ALD(REG_ITMP1, REG_PV, a);
2035                         switch (iptr->op1) {
2036                         case TYPE_INT:
2037                                 d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2038                                 M_ILD(d, REG_ITMP1, 0);
2039                                 store_reg_to_var_int(iptr->dst, d);
2040                                 break;
2041                         case TYPE_LNG:
2042                                 d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2043                                 M_LLD(d, REG_ITMP1, 0);
2044                                 store_reg_to_var_int(iptr->dst, d);
2045                                 break;
2046                         case TYPE_ADR:
2047                                 d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2048                                 M_ALD(d, REG_ITMP1, 0);
2049                                 store_reg_to_var_int(iptr->dst, d);
2050                                 break;
2051                         case TYPE_FLT:
2052                                 d = reg_of_var(rd, iptr->dst, REG_FTMP1);
2053                                 M_FLD(d, REG_ITMP1, 0);
2054                                 store_reg_to_var_flt(iptr->dst, d);
2055                                 break;
2056                         case TYPE_DBL:
2057                                 d = reg_of_var(rd, iptr->dst, REG_FTMP1);
2058                                 M_DLD(d, REG_ITMP1, 0);
2059                                 store_reg_to_var_flt(iptr->dst, d);
2060                                 break;
2061                         }
2062                         break;
2063
2064                 case ICMD_PUTSTATIC:  /* ..., value  ==> ...                          */
2065                                       /* op1 = type, val.a = field address            */
2066
2067                         if (!iptr->val.a) {
2068                                 codegen_addpatchref(cd, mcodeptr,
2069                                                                         PATCHER_get_putstatic,
2070                                                                         (unresolved_field *) iptr->target);
2071
2072                                 if (showdisassemble)
2073                                         M_NOP;
2074
2075                                 a = 0;
2076
2077                         } else {
2078                                 fieldinfo *fi = iptr->val.a;
2079
2080                                 if (!fi->class->initialized) {
2081                                         codegen_addpatchref(cd, mcodeptr,
2082                                                                                 PATCHER_clinit, fi->class);
2083
2084                                         if (showdisassemble)
2085                                                 M_NOP;
2086                                 }
2087
2088                                 a = (ptrint) &(fi->value);
2089                         }
2090
2091                         a = dseg_addaddress(cd, a);
2092                         M_ALD(REG_ITMP1, REG_PV, a);
2093                         switch (iptr->op1) {
2094                         case TYPE_INT:
2095                                 var_to_reg_int(s2, src, REG_ITMP2);
2096                                 M_IST(s2, REG_ITMP1, 0);
2097                                 break;
2098                         case TYPE_LNG:
2099                                 var_to_reg_int(s2, src, REG_ITMP2);
2100                                 M_LST(s2, REG_ITMP1, 0);
2101                                 break;
2102                         case TYPE_ADR:
2103                                 var_to_reg_int(s2, src, REG_ITMP2);
2104                                 M_AST(s2, REG_ITMP1, 0);
2105                                 break;
2106                         case TYPE_FLT:
2107                                 var_to_reg_flt(s2, src, REG_FTMP2);
2108                                 M_FST(s2, REG_ITMP1, 0);
2109                                 break;
2110                         case TYPE_DBL:
2111                                 var_to_reg_flt(s2, src, REG_FTMP2);
2112                                 M_DST(s2, REG_ITMP1, 0);
2113                                 break;
2114                         }
2115                         break;
2116
2117                 case ICMD_PUTSTATICCONST: /* ...  ==> ...                             */
2118                                           /* val = value (in current instruction)     */
2119                                           /* op1 = type, val.a = field address (in    */
2120                                           /* following NOP)                           */
2121
2122                         if (!iptr[1].val.a) {
2123                                 codegen_addpatchref(cd, mcodeptr,
2124                                                                         PATCHER_get_putstatic,
2125                                                                         (unresolved_field *) iptr[1].target);
2126
2127                                 if (showdisassemble)
2128                                         M_NOP;
2129
2130                                 a = 0;
2131
2132                         } else {
2133                                 fieldinfo *fi = iptr[1].val.a;
2134
2135                                 if (!fi->class->initialized) {
2136                                         codegen_addpatchref(cd, mcodeptr,
2137                                                                                 PATCHER_clinit, fi->class);
2138
2139                                         if (showdisassemble)
2140                                                 M_NOP;
2141                                 }
2142
2143                                 a = (ptrint) &(fi->value);
2144                         }
2145
2146                         a = dseg_addaddress(cd, a);
2147                         M_ALD(REG_ITMP1, REG_PV, a);
2148                         switch (iptr->op1) {
2149                         case TYPE_INT:
2150                                 M_IST(REG_ZERO, REG_ITMP1, 0);
2151                                 break;
2152                         case TYPE_LNG:
2153                                 M_LST(REG_ZERO, REG_ITMP1, 0);
2154                                 break;
2155                         case TYPE_ADR:
2156                                 M_AST(REG_ZERO, REG_ITMP1, 0);
2157                                 break;
2158                         case TYPE_FLT:
2159                                 M_FST(REG_ZERO, REG_ITMP1, 0);
2160                                 break;
2161                         case TYPE_DBL:
2162                                 M_DST(REG_ZERO, REG_ITMP1, 0);
2163                                 break;
2164                         }
2165                         break;
2166
2167
2168                 case ICMD_GETFIELD:   /* ...  ==> ..., value                          */
2169                                       /* op1 = type, val.i = field offset             */
2170
2171                         var_to_reg_int(s1, src, REG_ITMP1);
2172                         gen_nullptr_check(s1);
2173
2174                         if (!iptr->val.a) {
2175                                 codegen_addpatchref(cd, mcodeptr,
2176                                                                         PATCHER_get_putfield,
2177                                                                         (unresolved_field *) iptr->target);
2178
2179                                 if (showdisassemble)
2180                                         M_NOP;
2181
2182                                 a = 0;
2183
2184                         } else {
2185                                 a = ((fieldinfo *) (iptr->val.a))->offset;
2186                         }
2187
2188                         switch (iptr->op1) {
2189                         case TYPE_INT:
2190                                 d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2191                                 M_ILD(d, s1, a);
2192                                 store_reg_to_var_int(iptr->dst, d);
2193                                 break;
2194                         case TYPE_LNG:
2195                                 d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2196                                 M_LLD(d, s1, a);
2197                                 store_reg_to_var_int(iptr->dst, d);
2198                                 break;
2199                         case TYPE_ADR:
2200                                 d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2201                                 M_ALD(d, s1, a);
2202                                 store_reg_to_var_int(iptr->dst, d);
2203                                 break;
2204                         case TYPE_FLT:
2205                                 d = reg_of_var(rd, iptr->dst, REG_FTMP3);
2206                                 M_FLD(d, s1, a);
2207                                 store_reg_to_var_flt(iptr->dst, d);
2208                                 break;
2209                         case TYPE_DBL:
2210                                 d = reg_of_var(rd, iptr->dst, REG_FTMP3);
2211                                 M_DLD(d, s1, a);
2212                                 store_reg_to_var_flt(iptr->dst, d);
2213                                 break;
2214                         }
2215                         break;
2216
2217                 case ICMD_PUTFIELD:   /* ..., objectref, value  ==> ...               */
2218                                       /* op1 = type, val.a = field address            */
2219
2220                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2221                         gen_nullptr_check(s1);
2222
2223                         if (!IS_FLT_DBL_TYPE(iptr->op1)) {
2224                                 var_to_reg_int(s2, src, REG_ITMP2);
2225                         } else {
2226                                 var_to_reg_flt(s2, src, REG_FTMP2);
2227                         }
2228
2229                         if (!iptr->val.a) {
2230                                 codegen_addpatchref(cd, mcodeptr,
2231                                                                         PATCHER_get_putfield,
2232                                                                         (unresolved_field *) iptr->target);
2233
2234                                 if (showdisassemble)
2235                                         M_NOP;
2236
2237                                 a = 0;
2238
2239                         } else {
2240                                 a = ((fieldinfo *) (iptr->val.a))->offset;
2241                         }
2242
2243                         switch (iptr->op1) {
2244                         case TYPE_INT:
2245                                 M_IST(s2, s1, a);
2246                                 break;
2247                         case TYPE_LNG:
2248                                 M_LST(s2, s1, a);
2249                                 break;
2250                         case TYPE_ADR:
2251                                 M_AST(s2, s1, a);
2252                                 break;
2253                         case TYPE_FLT:
2254                                 M_FST(s2, s1, a);
2255                                 break;
2256                         case TYPE_DBL:
2257                                 M_DST(s2, s1, a);
2258                                 break;
2259                         }
2260                         break;
2261
2262                 case ICMD_PUTFIELDCONST:  /* ..., objectref  ==> ...                  */
2263                                           /* val = value (in current instruction)     */
2264                                           /* op1 = type, val.a = field address (in    */
2265                                           /* following NOP)                           */
2266
2267                         var_to_reg_int(s1, src, REG_ITMP1);
2268                         gen_nullptr_check(s1);
2269
2270                         if (!iptr[1].val.a) {
2271                                 codegen_addpatchref(cd, mcodeptr,
2272                                                                         PATCHER_get_putfield,
2273                                                                         (unresolved_field *) iptr[1].target);
2274
2275                                 if (showdisassemble)
2276                                         M_NOP;
2277
2278                                 a = 0;
2279
2280                         } else {
2281                                 a = ((fieldinfo *) (iptr[1].val.a))->offset;
2282                         }
2283
2284                         switch (iptr[1].op1) {
2285                         case TYPE_INT:
2286                                 M_IST(REG_ZERO, s1, a);
2287                                 break;
2288                         case TYPE_LNG:
2289                                 M_LST(REG_ZERO, s1, a);
2290                                 break;
2291                         case TYPE_ADR:
2292                                 M_AST(REG_ZERO, s1, a);
2293                                 break;
2294                         case TYPE_FLT:
2295                                 M_FST(REG_ZERO, s1, a);
2296                                 break;
2297                         case TYPE_DBL:
2298                                 M_DST(REG_ZERO, s1, a);
2299                                 break;
2300                         }
2301                         break;
2302
2303
2304                 /* branch operations **************************************************/
2305
2306                 case ICMD_ATHROW:       /* ..., objectref ==> ... (, objectref)       */
2307
2308                         var_to_reg_int(s1, src, REG_ITMP1);
2309                         M_INTMOVE(s1, REG_ITMP1_XPTR);
2310                         a = dseg_addaddress(cd, asm_handle_exception);
2311                         M_ALD(REG_ITMP2, REG_PV, a);
2312                         M_JMP(REG_ITMP2_XPC, REG_ITMP2);
2313                         M_NOP;              /* nop ensures that XPC is less than the end */
2314                                             /* of basic block                            */
2315                         ALIGNCODENOP;
2316                         break;
2317
2318                 case ICMD_GOTO:         /* ... ==> ...                                */
2319                                         /* op1 = target JavaVM pc                     */
2320                         M_BR(0);
2321                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2322                         ALIGNCODENOP;
2323                         break;
2324
2325                 case ICMD_JSR:          /* ... ==> ...                                */
2326                                         /* op1 = target JavaVM pc                     */
2327
2328                         M_BSR(REG_ITMP1, 0);
2329                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2330                         break;
2331
2332                 case ICMD_RET:          /* ... ==> ...                                */
2333                                         /* op1 = local variable                       */
2334
2335                         var = &(rd->locals[iptr->op1][TYPE_ADR]);
2336                         if (var->flags & INMEMORY) {
2337                                 M_ALD(REG_ITMP1, REG_SP, 8 * var->regoff);
2338                                 M_RET(REG_ZERO, REG_ITMP1);
2339                                 }
2340                         else
2341                                 M_RET(REG_ZERO, var->regoff);
2342                         ALIGNCODENOP;
2343                         break;
2344
2345                 case ICMD_IFNULL:       /* ..., value ==> ...                         */
2346                                         /* op1 = target JavaVM pc                     */
2347
2348                         var_to_reg_int(s1, src, REG_ITMP1);
2349                         M_BEQZ(s1, 0);
2350                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2351                         break;
2352
2353                 case ICMD_IFNONNULL:    /* ..., value ==> ...                         */
2354                                         /* op1 = target JavaVM pc                     */
2355
2356                         var_to_reg_int(s1, src, REG_ITMP1);
2357                         M_BNEZ(s1, 0);
2358                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2359                         break;
2360
2361                 case ICMD_IFEQ:         /* ..., value ==> ...                         */
2362                                         /* op1 = target JavaVM pc, val.i = constant   */
2363
2364                         var_to_reg_int(s1, src, REG_ITMP1);
2365                         if (iptr->val.i == 0) {
2366                                 M_BEQZ(s1, 0);
2367                                 }
2368                         else {
2369                                 if ((iptr->val.i > 0) && (iptr->val.i <= 255)) {
2370                                         M_CMPEQ_IMM(s1, iptr->val.i, REG_ITMP1);
2371                                         }
2372                                 else {
2373                                         ICONST(REG_ITMP2, iptr->val.i);
2374                                         M_CMPEQ(s1, REG_ITMP2, REG_ITMP1);
2375                                         }
2376                                 M_BNEZ(REG_ITMP1, 0);
2377                                 }
2378                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2379                         break;
2380
2381                 case ICMD_IFLT:         /* ..., value ==> ...                         */
2382                                         /* op1 = target JavaVM pc, val.i = constant   */
2383
2384                         var_to_reg_int(s1, src, REG_ITMP1);
2385                         if (iptr->val.i == 0) {
2386                                 M_BLTZ(s1, 0);
2387                                 }
2388                         else {
2389                                 if ((iptr->val.i > 0) && (iptr->val.i <= 255)) {
2390                                         M_CMPLT_IMM(s1, iptr->val.i, REG_ITMP1);
2391                                         }
2392                                 else {
2393                                         ICONST(REG_ITMP2, iptr->val.i);
2394                                         M_CMPLT(s1, REG_ITMP2, REG_ITMP1);
2395                                         }
2396                                 M_BNEZ(REG_ITMP1, 0);
2397                                 }
2398                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2399                         break;
2400
2401                 case ICMD_IFLE:         /* ..., value ==> ...                         */
2402                                         /* op1 = target JavaVM pc, val.i = constant   */
2403
2404                         var_to_reg_int(s1, src, REG_ITMP1);
2405                         if (iptr->val.i == 0) {
2406                                 M_BLEZ(s1, 0);
2407                                 }
2408                         else {
2409                                 if ((iptr->val.i > 0) && (iptr->val.i <= 255)) {
2410                                         M_CMPLE_IMM(s1, iptr->val.i, REG_ITMP1);
2411                                         }
2412                                 else {
2413                                         ICONST(REG_ITMP2, iptr->val.i);
2414                                         M_CMPLE(s1, REG_ITMP2, REG_ITMP1);
2415                                         }
2416                                 M_BNEZ(REG_ITMP1, 0);
2417                                 }
2418                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2419                         break;
2420
2421                 case ICMD_IFNE:         /* ..., value ==> ...                         */
2422                                         /* op1 = target JavaVM pc, val.i = constant   */
2423
2424                         var_to_reg_int(s1, src, REG_ITMP1);
2425                         if (iptr->val.i == 0) {
2426                                 M_BNEZ(s1, 0);
2427                                 }
2428                         else {
2429                                 if ((iptr->val.i > 0) && (iptr->val.i <= 255)) {
2430                                         M_CMPEQ_IMM(s1, iptr->val.i, REG_ITMP1);
2431                                         }
2432                                 else {
2433                                         ICONST(REG_ITMP2, iptr->val.i);
2434                                         M_CMPEQ(s1, REG_ITMP2, REG_ITMP1);
2435                                         }
2436                                 M_BEQZ(REG_ITMP1, 0);
2437                                 }
2438                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2439                         break;
2440
2441                 case ICMD_IFGT:         /* ..., value ==> ...                         */
2442                                         /* op1 = target JavaVM pc, val.i = constant   */
2443
2444                         var_to_reg_int(s1, src, REG_ITMP1);
2445                         if (iptr->val.i == 0) {
2446                                 M_BGTZ(s1, 0);
2447                                 }
2448                         else {
2449                                 if ((iptr->val.i > 0) && (iptr->val.i <= 255)) {
2450                                         M_CMPLE_IMM(s1, iptr->val.i, REG_ITMP1);
2451                                         }
2452                                 else {
2453                                         ICONST(REG_ITMP2, iptr->val.i);
2454                                         M_CMPLE(s1, REG_ITMP2, REG_ITMP1);
2455                                         }
2456                                 M_BEQZ(REG_ITMP1, 0);
2457                                 }
2458                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2459                         break;
2460
2461                 case ICMD_IFGE:         /* ..., value ==> ...                         */
2462                                         /* op1 = target JavaVM pc, val.i = constant   */
2463
2464                         var_to_reg_int(s1, src, REG_ITMP1);
2465                         if (iptr->val.i == 0) {
2466                                 M_BGEZ(s1, 0);
2467                                 }
2468                         else {
2469                                 if ((iptr->val.i > 0) && (iptr->val.i <= 255)) {
2470                                         M_CMPLT_IMM(s1, iptr->val.i, REG_ITMP1);
2471                                         }
2472                                 else {
2473                                         ICONST(REG_ITMP2, iptr->val.i);
2474                                         M_CMPLT(s1, REG_ITMP2, REG_ITMP1);
2475                                         }
2476                                 M_BEQZ(REG_ITMP1, 0);
2477                                 }
2478                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2479                         break;
2480
2481                 case ICMD_IF_LEQ:       /* ..., value ==> ...                         */
2482                                         /* op1 = target JavaVM pc, val.l = constant   */
2483
2484                         var_to_reg_int(s1, src, REG_ITMP1);
2485                         if (iptr->val.l == 0) {
2486                                 M_BEQZ(s1, 0);
2487                                 }
2488                         else {
2489                                 if ((iptr->val.l > 0) && (iptr->val.l <= 255)) {
2490                                         M_CMPEQ_IMM(s1, iptr->val.l, REG_ITMP1);
2491                                         }
2492                                 else {
2493                                         LCONST(REG_ITMP2, iptr->val.l);
2494                                         M_CMPEQ(s1, REG_ITMP2, REG_ITMP1);
2495                                         }
2496                                 M_BNEZ(REG_ITMP1, 0);
2497                                 }
2498                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2499                         break;
2500
2501                 case ICMD_IF_LLT:       /* ..., value ==> ...                         */
2502                                         /* op1 = target JavaVM pc, val.l = constant   */
2503
2504                         var_to_reg_int(s1, src, REG_ITMP1);
2505                         if (iptr->val.l == 0) {
2506                                 M_BLTZ(s1, 0);
2507                                 }
2508                         else {
2509                                 if ((iptr->val.l > 0) && (iptr->val.l <= 255)) {
2510                                         M_CMPLT_IMM(s1, iptr->val.l, REG_ITMP1);
2511                                         }
2512                                 else {
2513                                         LCONST(REG_ITMP2, iptr->val.l);
2514                                         M_CMPLT(s1, REG_ITMP2, REG_ITMP1);
2515                                         }
2516                                 M_BNEZ(REG_ITMP1, 0);
2517                                 }
2518                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2519                         break;
2520
2521                 case ICMD_IF_LLE:       /* ..., value ==> ...                         */
2522                                         /* op1 = target JavaVM pc, val.l = constant   */
2523
2524                         var_to_reg_int(s1, src, REG_ITMP1);
2525                         if (iptr->val.l == 0) {
2526                                 M_BLEZ(s1, 0);
2527                                 }
2528                         else {
2529                                 if ((iptr->val.l > 0) && (iptr->val.l <= 255)) {
2530                                         M_CMPLE_IMM(s1, iptr->val.l, REG_ITMP1);
2531                                         }
2532                                 else {
2533                                         LCONST(REG_ITMP2, iptr->val.l);
2534                                         M_CMPLE(s1, REG_ITMP2, REG_ITMP1);
2535                                         }
2536                                 M_BNEZ(REG_ITMP1, 0);
2537                                 }
2538                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2539                         break;
2540
2541                 case ICMD_IF_LNE:       /* ..., value ==> ...                         */
2542                                         /* op1 = target JavaVM pc, val.l = constant   */
2543
2544                         var_to_reg_int(s1, src, REG_ITMP1);
2545                         if (iptr->val.l == 0) {
2546                                 M_BNEZ(s1, 0);
2547                                 }
2548                         else {
2549                                 if ((iptr->val.l > 0) && (iptr->val.l <= 255)) {
2550                                         M_CMPEQ_IMM(s1, iptr->val.l, REG_ITMP1);
2551                                         }
2552                                 else {
2553                                         LCONST(REG_ITMP2, iptr->val.l);
2554                                         M_CMPEQ(s1, REG_ITMP2, REG_ITMP1);
2555                                         }
2556                                 M_BEQZ(REG_ITMP1, 0);
2557                                 }
2558                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2559                         break;
2560
2561                 case ICMD_IF_LGT:       /* ..., value ==> ...                         */
2562                                         /* op1 = target JavaVM pc, val.l = constant   */
2563
2564                         var_to_reg_int(s1, src, REG_ITMP1);
2565                         if (iptr->val.l == 0) {
2566                                 M_BGTZ(s1, 0);
2567                                 }
2568                         else {
2569                                 if ((iptr->val.l > 0) && (iptr->val.l <= 255)) {
2570                                         M_CMPLE_IMM(s1, iptr->val.l, REG_ITMP1);
2571                                         }
2572                                 else {
2573                                         LCONST(REG_ITMP2, iptr->val.l);
2574                                         M_CMPLE(s1, REG_ITMP2, REG_ITMP1);
2575                                         }
2576                                 M_BEQZ(REG_ITMP1, 0);
2577                                 }
2578                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2579                         break;
2580
2581                 case ICMD_IF_LGE:       /* ..., value ==> ...                         */
2582                                         /* op1 = target JavaVM pc, val.l = constant   */
2583
2584                         var_to_reg_int(s1, src, REG_ITMP1);
2585                         if (iptr->val.l == 0) {
2586                                 M_BGEZ(s1, 0);
2587                                 }
2588                         else {
2589                                 if ((iptr->val.l > 0) && (iptr->val.l <= 255)) {
2590                                         M_CMPLT_IMM(s1, iptr->val.l, REG_ITMP1);
2591                                         }
2592                                 else {
2593                                         LCONST(REG_ITMP2, iptr->val.l);
2594                                         M_CMPLT(s1, REG_ITMP2, REG_ITMP1);
2595                                         }
2596                                 M_BEQZ(REG_ITMP1, 0);
2597                                 }
2598                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2599                         break;
2600
2601                 case ICMD_IF_ICMPEQ:    /* ..., value, value ==> ...                  */
2602                 case ICMD_IF_LCMPEQ:    /* op1 = target JavaVM pc                     */
2603                 case ICMD_IF_ACMPEQ:
2604
2605                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2606                         var_to_reg_int(s2, src, REG_ITMP2);
2607                         M_CMPEQ(s1, s2, REG_ITMP1);
2608                         M_BNEZ(REG_ITMP1, 0);
2609                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2610                         break;
2611
2612                 case ICMD_IF_ICMPNE:    /* ..., value, value ==> ...                  */
2613                 case ICMD_IF_LCMPNE:    /* op1 = target JavaVM pc                     */
2614                 case ICMD_IF_ACMPNE:
2615
2616                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2617                         var_to_reg_int(s2, src, REG_ITMP2);
2618                         M_CMPEQ(s1, s2, REG_ITMP1);
2619                         M_BEQZ(REG_ITMP1, 0);
2620                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2621                         break;
2622
2623                 case ICMD_IF_ICMPLT:    /* ..., value, value ==> ...                  */
2624                 case ICMD_IF_LCMPLT:    /* op1 = target JavaVM pc                     */
2625
2626                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2627                         var_to_reg_int(s2, src, REG_ITMP2);
2628                         M_CMPLT(s1, s2, REG_ITMP1);
2629                         M_BNEZ(REG_ITMP1, 0);
2630                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2631                         break;
2632
2633                 case ICMD_IF_ICMPGT:    /* ..., value, value ==> ...                  */
2634                 case ICMD_IF_LCMPGT:    /* op1 = target JavaVM pc                     */
2635
2636                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2637                         var_to_reg_int(s2, src, REG_ITMP2);
2638                         M_CMPLE(s1, s2, REG_ITMP1);
2639                         M_BEQZ(REG_ITMP1, 0);
2640                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2641                         break;
2642
2643                 case ICMD_IF_ICMPLE:    /* ..., value, value ==> ...                  */
2644                 case ICMD_IF_LCMPLE:    /* op1 = target JavaVM pc                     */
2645
2646                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2647                         var_to_reg_int(s2, src, REG_ITMP2);
2648                         M_CMPLE(s1, s2, REG_ITMP1);
2649                         M_BNEZ(REG_ITMP1, 0);
2650                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2651                         break;
2652
2653                 case ICMD_IF_ICMPGE:    /* ..., value, value ==> ...                  */
2654                 case ICMD_IF_LCMPGE:    /* op1 = target JavaVM pc                     */
2655
2656                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2657                         var_to_reg_int(s2, src, REG_ITMP2);
2658                         M_CMPLT(s1, s2, REG_ITMP1);
2659                         M_BEQZ(REG_ITMP1, 0);
2660                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2661                         break;
2662
2663                 /* (value xx 0) ? IFxx_ICONST : ELSE_ICONST                           */
2664
2665                 case ICMD_ELSE_ICONST:  /* handled by IFxx_ICONST                     */
2666                         break;
2667
2668                 case ICMD_IFEQ_ICONST:  /* ..., value ==> ..., constant               */
2669                                         /* val.i = constant                           */
2670
2671                         var_to_reg_int(s1, src, REG_ITMP1);
2672                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2673                         s3 = iptr->val.i;
2674                         if (iptr[1].opc == ICMD_ELSE_ICONST) {
2675                                 if ((s3 == 1) && (iptr[1].val.i == 0)) {
2676                                         M_CMPEQ(s1, REG_ZERO, d);
2677                                         store_reg_to_var_int(iptr->dst, d);
2678                                         break;
2679                                         }
2680                                 if ((s3 == 0) && (iptr[1].val.i == 1)) {
2681                                         M_CMPEQ(s1, REG_ZERO, d);
2682                                         M_XOR_IMM(d, 1, d);
2683                                         store_reg_to_var_int(iptr->dst, d);
2684                                         break;
2685                                         }
2686                                 if (s1 == d) {
2687                                         M_MOV(s1, REG_ITMP1);
2688                                         s1 = REG_ITMP1;
2689                                         }
2690                                 ICONST(d, iptr[1].val.i);
2691                                 }
2692                         if ((s3 >= 0) && (s3 <= 255)) {
2693                                 M_CMOVEQ_IMM(s1, s3, d);
2694                                 }
2695                         else {
2696                                 ICONST(REG_ITMP2, s3);
2697                                 M_CMOVEQ(s1, REG_ITMP2, d);
2698                                 }
2699                         store_reg_to_var_int(iptr->dst, d);
2700                         break;
2701
2702                 case ICMD_IFNE_ICONST:  /* ..., value ==> ..., constant               */
2703                                         /* val.i = constant                           */
2704
2705                         var_to_reg_int(s1, src, REG_ITMP1);
2706                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2707                         s3 = iptr->val.i;
2708                         if (iptr[1].opc == ICMD_ELSE_ICONST) {
2709                                 if ((s3 == 0) && (iptr[1].val.i == 1)) {
2710                                         M_CMPEQ(s1, REG_ZERO, d);
2711                                         store_reg_to_var_int(iptr->dst, d);
2712                                         break;
2713                                         }
2714                                 if ((s3 == 1) && (iptr[1].val.i == 0)) {
2715                                         M_CMPEQ(s1, REG_ZERO, d);
2716                                         M_XOR_IMM(d, 1, d);
2717                                         store_reg_to_var_int(iptr->dst, d);
2718                                         break;
2719                                         }
2720                                 if (s1 == d) {
2721                                         M_MOV(s1, REG_ITMP1);
2722                                         s1 = REG_ITMP1;
2723                                         }
2724                                 ICONST(d, iptr[1].val.i);
2725                                 }
2726                         if ((s3 >= 0) && (s3 <= 255)) {
2727                                 M_CMOVNE_IMM(s1, s3, d);
2728                                 }
2729                         else {
2730                                 ICONST(REG_ITMP2, s3);
2731                                 M_CMOVNE(s1, REG_ITMP2, d);
2732                                 }
2733                         store_reg_to_var_int(iptr->dst, d);
2734                         break;
2735
2736                 case ICMD_IFLT_ICONST:  /* ..., value ==> ..., constant               */
2737                                         /* val.i = constant                           */
2738
2739                         var_to_reg_int(s1, src, REG_ITMP1);
2740                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2741                         s3 = iptr->val.i;
2742                         if ((iptr[1].opc == ICMD_ELSE_ICONST)) {
2743                                 if ((s3 == 1) && (iptr[1].val.i == 0)) {
2744                                         M_CMPLT(s1, REG_ZERO, d);
2745                                         store_reg_to_var_int(iptr->dst, d);
2746                                         break;
2747                                         }
2748                                 if ((s3 == 0) && (iptr[1].val.i == 1)) {
2749                                         M_CMPLE(REG_ZERO, s1, d);
2750                                         store_reg_to_var_int(iptr->dst, d);
2751                                         break;
2752                                         }
2753                                 if (s1 == d) {
2754                                         M_MOV(s1, REG_ITMP1);
2755                                         s1 = REG_ITMP1;
2756                                         }
2757                                 ICONST(d, iptr[1].val.i);
2758                                 }
2759                         if ((s3 >= 0) && (s3 <= 255)) {
2760                                 M_CMOVLT_IMM(s1, s3, d);
2761                                 }
2762                         else {
2763                                 ICONST(REG_ITMP2, s3);
2764                                 M_CMOVLT(s1, REG_ITMP2, d);
2765                                 }
2766                         store_reg_to_var_int(iptr->dst, d);
2767                         break;
2768
2769                 case ICMD_IFGE_ICONST:  /* ..., value ==> ..., constant               */
2770                                         /* val.i = constant                           */
2771
2772                         var_to_reg_int(s1, src, REG_ITMP1);
2773                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2774                         s3 = iptr->val.i;
2775                         if ((iptr[1].opc == ICMD_ELSE_ICONST)) {
2776                                 if ((s3 == 1) && (iptr[1].val.i == 0)) {
2777                                         M_CMPLE(REG_ZERO, s1, d);
2778                                         store_reg_to_var_int(iptr->dst, d);
2779                                         break;
2780                                         }
2781                                 if ((s3 == 0) && (iptr[1].val.i == 1)) {
2782                                         M_CMPLT(s1, REG_ZERO, d);
2783                                         store_reg_to_var_int(iptr->dst, d);
2784                                         break;
2785                                         }
2786                                 if (s1 == d) {
2787                                         M_MOV(s1, REG_ITMP1);
2788                                         s1 = REG_ITMP1;
2789                                         }
2790                                 ICONST(d, iptr[1].val.i);
2791                                 }
2792                         if ((s3 >= 0) && (s3 <= 255)) {
2793                                 M_CMOVGE_IMM(s1, s3, d);
2794                                 }
2795                         else {
2796                                 ICONST(REG_ITMP2, s3);
2797                                 M_CMOVGE(s1, REG_ITMP2, d);
2798                                 }
2799                         store_reg_to_var_int(iptr->dst, d);
2800                         break;
2801
2802                 case ICMD_IFGT_ICONST:  /* ..., value ==> ..., constant               */
2803                                         /* val.i = constant                           */
2804
2805                         var_to_reg_int(s1, src, REG_ITMP1);
2806                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2807                         s3 = iptr->val.i;
2808                         if ((iptr[1].opc == ICMD_ELSE_ICONST)) {
2809                                 if ((s3 == 1) && (iptr[1].val.i == 0)) {
2810                                         M_CMPLT(REG_ZERO, s1, d);
2811                                         store_reg_to_var_int(iptr->dst, d);
2812                                         break;
2813                                         }
2814                                 if ((s3 == 0) && (iptr[1].val.i == 1)) {
2815                                         M_CMPLE(s1, REG_ZERO, d);
2816                                         store_reg_to_var_int(iptr->dst, d);
2817                                         break;
2818                                         }
2819                                 if (s1 == d) {
2820                                         M_MOV(s1, REG_ITMP1);
2821                                         s1 = REG_ITMP1;
2822                                         }
2823                                 ICONST(d, iptr[1].val.i);
2824                                 }
2825                         if ((s3 >= 0) && (s3 <= 255)) {
2826                                 M_CMOVGT_IMM(s1, s3, d);
2827                                 }
2828                         else {
2829                                 ICONST(REG_ITMP2, s3);
2830                                 M_CMOVGT(s1, REG_ITMP2, d);
2831                                 }
2832                         store_reg_to_var_int(iptr->dst, d);
2833                         break;
2834
2835                 case ICMD_IFLE_ICONST:  /* ..., value ==> ..., constant               */
2836                                         /* val.i = constant                           */
2837
2838                         var_to_reg_int(s1, src, REG_ITMP1);
2839                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
2840                         s3 = iptr->val.i;
2841                         if ((iptr[1].opc == ICMD_ELSE_ICONST)) {
2842                                 if ((s3 == 1) && (iptr[1].val.i == 0)) {
2843                                         M_CMPLE(s1, REG_ZERO, d);
2844                                         store_reg_to_var_int(iptr->dst, d);
2845                                         break;
2846                                         }
2847                                 if ((s3 == 0) && (iptr[1].val.i == 1)) {
2848                                         M_CMPLT(REG_ZERO, s1, d);
2849                                         store_reg_to_var_int(iptr->dst, d);
2850                                         break;
2851                                         }
2852                                 if (s1 == d) {
2853                                         M_MOV(s1, REG_ITMP1);
2854                                         s1 = REG_ITMP1;
2855                                         }
2856                                 ICONST(d, iptr[1].val.i);
2857                                 }
2858                         if ((s3 >= 0) && (s3 <= 255)) {
2859                                 M_CMOVLE_IMM(s1, s3, d);
2860                                 }
2861                         else {
2862                                 ICONST(REG_ITMP2, s3);
2863                                 M_CMOVLE(s1, REG_ITMP2, d);
2864                                 }
2865                         store_reg_to_var_int(iptr->dst, d);
2866                         break;
2867
2868
2869                 case ICMD_IRETURN:      /* ..., retvalue ==> ...                      */
2870                 case ICMD_LRETURN:
2871                 case ICMD_ARETURN:
2872
2873                         var_to_reg_int(s1, src, REG_RESULT);
2874                         M_INTMOVE(s1, REG_RESULT);
2875
2876                         goto nowperformreturn;
2877
2878                 case ICMD_FRETURN:      /* ..., retvalue ==> ...                      */
2879                 case ICMD_DRETURN:
2880
2881                         var_to_reg_flt(s1, src, REG_FRESULT);
2882                         M_FLTMOVE(s1, REG_FRESULT);
2883
2884                         goto nowperformreturn;
2885
2886                 case ICMD_RETURN:       /* ...  ==> ...                               */
2887
2888 nowperformreturn:
2889                         {
2890                         s4 i, p;
2891
2892                         p = parentargs_base;
2893
2894                         /* call trace function */
2895
2896                         if (runverbose) {
2897                                 M_LDA(REG_SP, REG_SP, -3 * 8);
2898                                 M_AST(REG_RA, REG_SP, 0 * 8);
2899                                 M_LST(REG_RESULT, REG_SP, 1 * 8);
2900                                 M_DST(REG_FRESULT, REG_SP, 2 * 8);
2901                                 a = dseg_addaddress(cd, m);
2902                                 M_ALD(rd->argintregs[0], REG_PV, a);
2903                                 M_MOV(REG_RESULT, rd->argintregs[1]);
2904                                 M_FLTMOVE(REG_FRESULT, rd->argfltregs[2]);
2905                                 M_FLTMOVE(REG_FRESULT, rd->argfltregs[3]);
2906                                 a = dseg_addaddress(cd, (void *) builtin_displaymethodstop);
2907                                 M_ALD(REG_PV, REG_PV, a);
2908                                 M_JSR(REG_RA, REG_PV);
2909                                 s1 = (s4) ((u1 *) mcodeptr - cd->mcodebase);
2910                                 if (s1 <= 32768) M_LDA(REG_PV, REG_RA, -s1);
2911                                 else {
2912                                         s4 ml = -s1, mh = 0;
2913                                         while (ml < -32768) { ml += 65536; mh--; }
2914                                         M_LDA(REG_PV, REG_RA, ml);
2915                                         M_LDAH(REG_PV, REG_PV, mh);
2916                                 }
2917                                 M_DLD(REG_FRESULT, REG_SP, 2 * 8);
2918                                 M_LLD(REG_RESULT, REG_SP, 1 * 8);
2919                                 M_ALD(REG_RA, REG_SP, 0 * 8);
2920                                 M_LDA(REG_SP, REG_SP, 3 * 8);
2921                         }
2922
2923 #if defined(USE_THREADS)
2924                         if (checksync && (m->flags & ACC_SYNCHRONIZED)) {
2925                                 s4 disp;
2926
2927                                 M_ALD(rd->argintregs[0], REG_SP, rd->memuse * 8);
2928
2929                                 switch (iptr->opc) {
2930                                 case ICMD_IRETURN:
2931                                 case ICMD_LRETURN:
2932                                 case ICMD_ARETURN:
2933                                         M_LST(REG_RESULT, REG_SP, rd->memuse * 8);
2934                                         break;
2935                                 case ICMD_FRETURN:
2936                                 case ICMD_DRETURN:
2937                                         M_DST(REG_FRESULT, REG_SP, rd->memuse * 8);
2938                                         break;
2939                                 }
2940
2941                                 a = dseg_addaddress(cd, BUILTIN_monitorexit);
2942                                 M_ALD(REG_PV, REG_PV, a);
2943                                 M_JSR(REG_RA, REG_PV);
2944                                 disp = -(s4) ((u1 *) mcodeptr - cd->mcodebase);
2945                                 M_LDA(REG_PV, REG_RA, disp);
2946
2947                                 switch (iptr->opc) {
2948                                 case ICMD_IRETURN:
2949                                 case ICMD_LRETURN:
2950                                 case ICMD_ARETURN:
2951                                         M_LLD(REG_RESULT, REG_SP, rd->memuse * 8);
2952                                         break;
2953                                 case ICMD_FRETURN:
2954                                 case ICMD_DRETURN:
2955                                         M_DLD(REG_FRESULT, REG_SP, rd->memuse * 8);
2956                                         break;
2957                                 }
2958                         }
2959 #endif
2960
2961                         /* restore return address                                         */
2962
2963                         if (!m->isleafmethod) {
2964                                 p--; M_LLD(REG_RA, REG_SP, p * 8);
2965                         }
2966
2967                         /* restore saved registers                                        */
2968
2969                         for (i = INT_SAV_CNT - 1; i >= rd->savintreguse; i--) {
2970                                 p--; M_LLD(rd->savintregs[i], REG_SP, p * 8);
2971                         }
2972                         for (i = FLT_SAV_CNT - 1; i >= rd->savfltreguse; i--) {
2973                                 p--; M_DLD(rd->savfltregs[i], REG_SP, p * 8);
2974                         }
2975
2976                         /* deallocate stack                                               */
2977
2978                         if (parentargs_base) {
2979                                 M_LDA(REG_SP, REG_SP, parentargs_base * 8);
2980                         }
2981
2982                         M_RET(REG_ZERO, REG_RA);
2983                         ALIGNCODENOP;
2984                         }
2985                         break;
2986
2987
2988                 case ICMD_TABLESWITCH:  /* ..., index ==> ...                         */
2989                         {
2990                         s4 i, l, *s4ptr;
2991                         void **tptr;
2992
2993                         tptr = (void **) iptr->target;
2994
2995                         s4ptr = iptr->val.a;
2996                         l = s4ptr[1];                          /* low     */
2997                         i = s4ptr[2];                          /* high    */
2998
2999                         var_to_reg_int(s1, src, REG_ITMP1);
3000                         if (l == 0)
3001                                 {M_INTMOVE(s1, REG_ITMP1);}
3002                         else if (l <= 32768) {
3003                                 M_LDA(REG_ITMP1, s1, -l);
3004                                 }
3005                         else {
3006                                 ICONST(REG_ITMP2, l);
3007                                 M_ISUB(s1, REG_ITMP2, REG_ITMP1);
3008                                 }
3009                         i = i - l + 1;
3010
3011                         /* range check */
3012
3013                         if (i <= 256)
3014                                 M_CMPULE_IMM(REG_ITMP1, i - 1, REG_ITMP2);
3015                         else {
3016                                 M_LDA(REG_ITMP2, REG_ZERO, i - 1);
3017                                 M_CMPULE(REG_ITMP1, REG_ITMP2, REG_ITMP2);
3018                                 }
3019                         M_BEQZ(REG_ITMP2, 0);
3020
3021
3022                         /* codegen_addreference(cd, BlockPtrOfPC(s4ptr[0]), mcodeptr); */
3023                         codegen_addreference(cd, (basicblock *) tptr[0], mcodeptr);
3024
3025                         /* build jump table top down and use address of lowest entry */
3026
3027                         /* s4ptr += 3 + i; */
3028                         tptr += i;
3029
3030                         while (--i >= 0) {
3031                                 /* dseg_addtarget(cd, BlockPtrOfPC(*--s4ptr)); */
3032                                 dseg_addtarget(cd, (basicblock *) tptr[0]);
3033                                 --tptr;
3034                                 }
3035                         }
3036
3037                         /* length of dataseg after last dseg_addtarget is used by load */
3038
3039                         M_SAADDQ(REG_ITMP1, REG_PV, REG_ITMP2);
3040                         M_ALD(REG_ITMP2, REG_ITMP2, -(cd->dseglen));
3041                         M_JMP(REG_ZERO, REG_ITMP2);
3042                         ALIGNCODENOP;
3043                         break;
3044
3045
3046                 case ICMD_LOOKUPSWITCH: /* ..., key ==> ...                           */
3047                         {
3048                         s4 i, l, val, *s4ptr;
3049                         void **tptr;
3050
3051                         tptr = (void **) iptr->target;
3052
3053                         s4ptr = iptr->val.a;
3054                         l = s4ptr[0];                          /* default  */
3055                         i = s4ptr[1];                          /* count    */
3056
3057                         MCODECHECK((i<<2)+8);
3058                         var_to_reg_int(s1, src, REG_ITMP1);
3059                         while (--i >= 0) {
3060                                 s4ptr += 2;
3061                                 ++tptr;
3062
3063                                 val = s4ptr[0];
3064                                 if ((val >= 0) && (val <= 255)) {
3065                                         M_CMPEQ_IMM(s1, val, REG_ITMP2);
3066                                         }
3067                                 else {
3068                                         if ((val >= -32768) && (val <= 32767)) {
3069                                                 M_LDA(REG_ITMP2, REG_ZERO, val);
3070                                                 }
3071                                         else {
3072                                                 a = dseg_adds4(cd, val);
3073                                                 M_ILD(REG_ITMP2, REG_PV, a);
3074                                                 }
3075                                         M_CMPEQ(s1, REG_ITMP2, REG_ITMP2);
3076                                         }
3077                                 M_BNEZ(REG_ITMP2, 0);
3078                                 /* codegen_addreference(cd, BlockPtrOfPC(s4ptr[1]), mcodeptr); */
3079                                 codegen_addreference(cd, (basicblock *) tptr[0], mcodeptr);
3080                                 }
3081
3082                         M_BR(0);
3083                         /* codegen_addreference(cd, BlockPtrOfPC(l), mcodeptr); */
3084
3085                         tptr = (void **) iptr->target;
3086                         codegen_addreference(cd, (basicblock *) tptr[0], mcodeptr);
3087
3088                         ALIGNCODENOP;
3089                         break;
3090                         }
3091
3092
3093                 case ICMD_BUILTIN:      /* ..., arg1, arg2, arg3 ==> ...              */
3094                                         /* op1 = arg count val.a = builtintable entry */
3095
3096                         bte = iptr->val.a;
3097                         md = bte->md;
3098                         goto gen_method;
3099
3100                 case ICMD_INVOKESTATIC: /* ..., [arg1, [arg2 ...]] ==> ...            */
3101                                         /* op1 = arg count, val.a = method pointer    */
3102
3103                 case ICMD_INVOKESPECIAL:/* ..., objectref, [arg1, [arg2 ...]] ==> ... */
3104                 case ICMD_INVOKEVIRTUAL:/* op1 = arg count, val.a = method pointer    */
3105                 case ICMD_INVOKEINTERFACE:
3106
3107                         lm = iptr->val.a;
3108
3109                         if (lm)
3110                                 md = lm->parseddesc;
3111                         else {
3112                                 unresolved_method *um = iptr->target;
3113                                 md = um->methodref->parseddesc.md;
3114                         }
3115
3116 gen_method:
3117                         s3 = iptr->op1;
3118
3119                         MCODECHECK((s3 << 1) + 64);
3120
3121                         /* copy arguments to registers or stack location                  */
3122
3123                         for (s3 = s3 - 1; s3 >= 0; s3--, src = src->prev) {
3124                                 if (src->varkind == ARGVAR)
3125                                         continue;
3126                                 if (IS_INT_LNG_TYPE(src->type)) {
3127                                         if (!md->params[s3].inmemory) {
3128                                                 s1 = rd->argintregs[md->params[s3].regoff];
3129                                                 var_to_reg_int(d, src, s1);
3130                                                 M_INTMOVE(d, s1);
3131                                         } else {
3132                                                 var_to_reg_int(d, src, REG_ITMP1);
3133                                                 M_LST(d, REG_SP, md->params[s3].regoff * 8);
3134                                         }
3135
3136                                 } else {
3137                                         if (!md->params[s3].inmemory) {
3138                                                 s1 = rd->argfltregs[md->params[s3].regoff];
3139                                                 var_to_reg_flt(d, src, s1);
3140                                                 M_FLTMOVE(d, s1);
3141                                         } else {
3142                                                 var_to_reg_flt(d, src, REG_FTMP1);
3143                                                 M_DST(d, REG_SP, md->params[s3].regoff * 8);
3144                                         }
3145                                 }
3146                         }
3147
3148                         switch (iptr->opc) {
3149                         case ICMD_BUILTIN:
3150                                 if (iptr->target) {
3151                                         codegen_addpatchref(cd, mcodeptr, bte->fp, iptr->target);
3152
3153                                         if (showdisassemble)
3154                                                 M_NOP;
3155
3156                                         a = 0;
3157
3158                                 } else {
3159                                         a = (ptrint) bte->fp;
3160                                 }
3161
3162                                 a = dseg_addaddress(cd, a);
3163                                 d = md->returntype.type;
3164
3165                                 M_ALD(REG_PV, REG_PV, a);     /* Pointer to built-in-function */
3166                                 break;
3167
3168                         case ICMD_INVOKESPECIAL:
3169                                 gen_nullptr_check(rd->argintregs[0]);
3170                                 M_ILD(REG_ITMP1, rd->argintregs[0], 0); /* hardware nullptr   */
3171                                 /* fall through */
3172
3173                         case ICMD_INVOKESTATIC:
3174                                 if (!lm) {
3175                                         unresolved_method *um = iptr->target;
3176
3177                                         codegen_addpatchref(cd, mcodeptr,
3178                                                                                 PATCHER_invokestatic_special, um);
3179
3180                                         if (showdisassemble)
3181                                                 M_NOP;
3182
3183                                         a = 0;
3184                                         d = um->methodref->parseddesc.md->returntype.type;
3185
3186                                 } else {
3187                                         a = (ptrint) lm->stubroutine;
3188                                         d = lm->parseddesc->returntype.type;
3189                                 }
3190
3191                                 a = dseg_addaddress(cd, a);
3192                                 M_ALD(REG_PV, REG_PV, a);            /* method pointer in r27 */
3193                                 break;
3194
3195                         case ICMD_INVOKEVIRTUAL:
3196                                 gen_nullptr_check(rd->argintregs[0]);
3197
3198                                 if (!lm) {
3199                                         unresolved_method *um = iptr->target;
3200
3201                                         codegen_addpatchref(cd, mcodeptr,
3202                                                                                 PATCHER_invokevirtual, um);
3203
3204                                         if (showdisassemble)
3205                                                 M_NOP;
3206
3207                                         s1 = 0;
3208                                         d = um->methodref->parseddesc.md->returntype.type;
3209
3210                                 } else {
3211                                         s1 = OFFSET(vftbl_t, table[0]) +
3212                                                 sizeof(methodptr) * lm->vftblindex;
3213                                         d = lm->parseddesc->returntype.type;
3214                                 }
3215
3216                                 M_ALD(REG_METHODPTR, rd->argintregs[0],
3217                                           OFFSET(java_objectheader, vftbl));
3218                                 M_ALD(REG_PV, REG_METHODPTR, s1);
3219                                 break;
3220
3221                         case ICMD_INVOKEINTERFACE:
3222                                 gen_nullptr_check(rd->argintregs[0]);
3223
3224                                 if (!lm) {
3225                                         unresolved_method *um = iptr->target;
3226
3227                                         codegen_addpatchref(cd, mcodeptr,
3228                                                                                 PATCHER_invokeinterface, um);
3229
3230                                         if (showdisassemble)
3231                                                 M_NOP;
3232
3233                                         s1 = 0;
3234                                         s2 = 0;
3235                                         d = um->methodref->parseddesc.md->returntype.type;
3236
3237                                 } else {
3238                                         s1 = OFFSET(vftbl_t, interfacetable[0]) -
3239                                                 sizeof(methodptr*) * lm->class->index;
3240
3241                                         s2 = sizeof(methodptr) * (lm - lm->class->methods);
3242
3243                                         d = lm->parseddesc->returntype.type;
3244                                 }
3245
3246                                 M_ALD(REG_METHODPTR, rd->argintregs[0],
3247                                           OFFSET(java_objectheader, vftbl));
3248                                 M_ALD(REG_METHODPTR, REG_METHODPTR, s1);
3249                                 M_ALD(REG_PV, REG_METHODPTR, s2);
3250                                 break;
3251                         }
3252
3253                         M_JSR(REG_RA, REG_PV);
3254
3255                         /* recompute pv */
3256
3257                         s1 = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3258                         if (s1 <= 32768) M_LDA(REG_PV, REG_RA, -s1);
3259                         else {
3260                                 s4 ml = -s1, mh = 0;
3261                                 while (ml < -32768) { ml += 65536; mh--; }
3262                                 M_LDA(REG_PV, REG_RA, ml);
3263                                 M_LDAH(REG_PV, REG_PV, mh);
3264                         }
3265
3266                         /* d contains return type */
3267
3268                         if (d != TYPE_VOID) {
3269                                 if (IS_INT_LNG_TYPE(iptr->dst->type)) {
3270                                         s1 = reg_of_var(rd, iptr->dst, REG_RESULT);
3271                                         M_INTMOVE(REG_RESULT, s1);
3272                                         store_reg_to_var_int(iptr->dst, s1);
3273                                 } else {
3274                                         s1 = reg_of_var(rd, iptr->dst, REG_FRESULT);
3275                                         M_FLTMOVE(REG_FRESULT, s1);
3276                                         store_reg_to_var_flt(iptr->dst, s1);
3277                                 }
3278                         }
3279                         break;
3280
3281
3282                 case ICMD_CHECKCAST:  /* ..., objectref ==> ..., objectref            */
3283
3284                                       /* op1:   0 == array, 1 == class                */
3285                                       /* val.a: (classinfo*) superclass               */
3286
3287                         /*  superclass is an interface:
3288                          *
3289                          *  OK if ((sub == NULL) ||
3290                          *         (sub->vftbl->interfacetablelength > super->index) &&
3291                          *         (sub->vftbl->interfacetable[-super->index] != NULL));
3292                          *
3293                          *  superclass is a class:
3294                          *
3295                          *  OK if ((sub == NULL) || (0
3296                          *         <= (sub->vftbl->baseval - super->vftbl->baseval) <=
3297                          *         super->vftbl->diffval));
3298                          */
3299
3300                         {
3301                         classinfo *super;
3302                         vftbl_t   *supervftbl;
3303                         s4         superindex;
3304
3305                         super = (classinfo *) iptr->val.a;
3306
3307                         if (!super) {
3308                                 superindex = 0;
3309                                 supervftbl = NULL;
3310
3311                         } else {
3312                                 superindex = super->index;
3313                                 supervftbl = super->vftbl;
3314                         }
3315
3316 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3317                         codegen_threadcritrestart(cd, (u1 *) mcodeptr - cd->mcodebase);
3318 #endif
3319                         var_to_reg_int(s1, src, REG_ITMP1);
3320
3321                         /* calculate interface checkcast code size */
3322
3323                         s2 = 6;
3324                         if (!super)
3325                                 s2 += showdisassemble ? 1 : 0;
3326
3327                         /* calculate class checkcast code size */
3328
3329                         s3 = 9 /* 8 + (s1 == REG_ITMP1) */;
3330                         if (!super)
3331                                 s3 += showdisassemble ? 1 : 0;
3332
3333                         /* if class is not resolved, check which code to call */
3334
3335                         if (!super) {
3336                                 M_BEQZ(s1, 4 + (showdisassemble ? 1 : 0) + s2 + 1 + s3);
3337
3338                                 codegen_addpatchref(cd, mcodeptr,
3339                                                                         PATCHER_checkcast_instanceof_flags,
3340                                                                         (constant_classref *) iptr->target);
3341
3342                                 if (showdisassemble)
3343                                         M_NOP;
3344
3345                                 a = dseg_adds4(cd, 0); /* super->flags */
3346                                 M_ILD(REG_ITMP2, REG_PV, a);
3347                                 a = dseg_adds4(cd, ACC_INTERFACE);
3348                                 M_ILD(REG_ITMP3, REG_PV, a);
3349                                 M_AND(REG_ITMP2, REG_ITMP3, REG_ITMP2);
3350                                 M_BEQZ(REG_ITMP2, s2 + 1);
3351                         }
3352
3353                         /* interface checkcast code */
3354
3355                         if (!super || (super->flags & ACC_INTERFACE)) {
3356                                 if (super) {
3357                                         M_BEQZ(s1, s2);
3358
3359                                 } else {
3360                                         codegen_addpatchref(cd, mcodeptr,
3361                                                                                 PATCHER_checkcast_instanceof_interface,
3362                                                                                 (constant_classref *) iptr->target);
3363
3364                                         if (showdisassemble)
3365                                                 M_NOP;
3366                                 }
3367
3368                                 M_ALD(REG_ITMP2, s1, OFFSET(java_objectheader, vftbl));
3369                                 M_ILD(REG_ITMP3, REG_ITMP2, OFFSET(vftbl_t, interfacetablelength));
3370                                 M_LDA(REG_ITMP3, REG_ITMP3, -superindex);
3371                                 M_BLEZ(REG_ITMP3, 0);
3372                                 codegen_addxcastrefs(cd, mcodeptr);
3373                                 M_ALD(REG_ITMP3, REG_ITMP2,
3374                                           OFFSET(vftbl_t, interfacetable[0]) -
3375                                           superindex * sizeof(methodptr*));
3376                                 M_BEQZ(REG_ITMP3, 0);
3377                                 codegen_addxcastrefs(cd, mcodeptr);
3378
3379                                 if (!super)
3380                                         M_BR(s3);
3381                         }
3382
3383                         /* class checkcast code */
3384
3385                         if (!super || !(super->flags & ACC_INTERFACE)) {
3386                                 if (super) {
3387                                         M_BEQZ(s1, s3);
3388
3389                                 } else {
3390                                         codegen_addpatchref(cd, mcodeptr,
3391                                                                                 PATCHER_checkcast_instanceof_class,
3392                                                                                 (constant_classref *) iptr->target);
3393
3394                                         if (showdisassemble)
3395                                                 M_NOP;
3396                                 }
3397
3398                                 M_ALD(REG_ITMP2, s1, OFFSET(java_objectheader, vftbl));
3399                                 a = dseg_addaddress(cd, supervftbl);
3400                                 M_ALD(REG_ITMP3, REG_PV, a);
3401 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3402                                 codegen_threadcritstart(cd, (u1 *) mcodeptr - cd->mcodebase);
3403 #endif
3404                                 M_ILD(REG_ITMP2, REG_ITMP2, OFFSET(vftbl_t, baseval));
3405 /*                              if (s1 != REG_ITMP1) { */
3406 /*                                      M_ILD(REG_ITMP1, REG_ITMP3, OFFSET(vftbl_t, baseval)); */
3407 /*                                      M_ILD(REG_ITMP3, REG_ITMP3, OFFSET(vftbl_t, diffval)); */
3408 /*  #if defined(USE_THREADS) && defined(NATIVE_THREADS) */
3409 /*                                      codegen_threadcritstop(cd, (u1 *) mcodeptr - cd->mcodebase); */
3410 /*  #endif */
3411 /*                                      M_ISUB(REG_ITMP2, REG_ITMP1, REG_ITMP2); */
3412
3413 /*                              } else { */
3414                                         M_ILD(REG_ITMP3, REG_ITMP3, OFFSET(vftbl_t, baseval));
3415                                         M_ISUB(REG_ITMP2, REG_ITMP3, REG_ITMP2);
3416                                         M_ALD(REG_ITMP3, REG_PV, a);
3417                                         M_ILD(REG_ITMP3, REG_ITMP3, OFFSET(vftbl_t, diffval));
3418 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3419                                         codegen_threadcritstop(cd, (u1 *) mcodeptr - cd->mcodebase);
3420 #endif
3421 /*                              } */
3422                                 M_CMPULE(REG_ITMP2, REG_ITMP3, REG_ITMP3);
3423                                 M_BEQZ(REG_ITMP3, 0);
3424                                 codegen_addxcastrefs(cd, mcodeptr);
3425                         }
3426                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
3427                         M_INTMOVE(s1, d);
3428                         store_reg_to_var_int(iptr->dst, d);
3429                         }
3430                         break;
3431
3432                 case ICMD_INSTANCEOF: /* ..., objectref ==> ..., intresult            */
3433
3434                                       /* op1:   0 == array, 1 == class                */
3435                                       /* val.a: (classinfo*) superclass               */
3436
3437                         /*  superclass is an interface:
3438                          *
3439                          *  return (sub != NULL) &&
3440                          *         (sub->vftbl->interfacetablelength > super->index) &&
3441                          *         (sub->vftbl->interfacetable[-super->index] != NULL);
3442                          *
3443                          *  superclass is a class:
3444                          *
3445                          *  return ((sub != NULL) && (0
3446                          *          <= (sub->vftbl->baseval - super->vftbl->baseval) <=
3447                          *          super->vftbl->diffvall));
3448                          */
3449
3450                         {
3451                         classinfo *super;
3452                         vftbl_t   *supervftbl;
3453                         s4         superindex;
3454
3455                         super = (classinfo *) iptr->val.a;
3456
3457                         if (!super) {
3458                                 superindex = 0;
3459                                 supervftbl = NULL;
3460
3461                         } else {
3462                                 superindex = super->index;
3463                                 supervftbl = super->vftbl;
3464                         }
3465
3466 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3467                         codegen_threadcritrestart(cd, (u1 *) mcodeptr - cd->mcodebase);
3468 #endif
3469                         var_to_reg_int(s1, src, REG_ITMP1);
3470                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
3471                         if (s1 == d) {
3472                                 M_MOV(s1, REG_ITMP1);
3473                                 s1 = REG_ITMP1;
3474                         }
3475
3476                         /* calculate interface instanceof code size */
3477
3478                         s2 = 6;
3479                         if (!super)
3480                                 s2 += (d == REG_ITMP2 ? 1 : 0) + (showdisassemble ? 1 : 0);
3481
3482                         /* calculate class instanceof code size */
3483
3484                         s3 = 7;
3485                         if (!super)
3486                                 s3 += (showdisassemble ? 1 : 0);
3487
3488                         /* if class is not resolved, check which code to call */
3489
3490                         if (!super) {
3491                                 M_CLR(d);
3492                                 M_BEQZ(s1, 4 + (showdisassemble ? 1 : 0) + s2 + 1 + s3);
3493
3494                                 codegen_addpatchref(cd, mcodeptr,
3495                                                                         PATCHER_checkcast_instanceof_flags,
3496                                                                         (constant_classref *) iptr->target);
3497
3498                                 if (showdisassemble)
3499                                         M_NOP;
3500
3501                                 a = dseg_adds4(cd, 0); /* super->flags */
3502                                 M_ILD(REG_ITMP3, REG_PV, a);
3503                                 a = dseg_adds4(cd, ACC_INTERFACE);
3504                                 M_ILD(REG_ITMP2, REG_PV, a);
3505                                 M_AND(REG_ITMP3, REG_ITMP2, REG_ITMP3);
3506                                 M_BEQZ(REG_ITMP3, s2 + 1);
3507                         }
3508
3509                         /* interface instanceof code */
3510
3511                         if (!super || (super->flags & ACC_INTERFACE)) {
3512                                 if (super) {
3513                                         M_CLR(d);
3514                                         M_BEQZ(s1, s2);
3515
3516                                 } else {
3517                                         /* If d == REG_ITMP2, then it's destroyed in check code   */
3518                                         /* above.                                                 */
3519                                         if (d == REG_ITMP2)
3520                                                 M_CLR(d);
3521
3522                                         codegen_addpatchref(cd, mcodeptr,
3523                                                                                 PATCHER_checkcast_instanceof_interface,
3524                                                                                 (constant_classref *) iptr->target);
3525
3526                                         if (showdisassemble)
3527                                                 M_NOP;
3528                                 }
3529
3530                                 M_ALD(REG_ITMP1, s1, OFFSET(java_objectheader, vftbl));
3531                                 M_ILD(REG_ITMP3, REG_ITMP1, OFFSET(vftbl_t, interfacetablelength));
3532                                 M_LDA(REG_ITMP3, REG_ITMP3, -superindex);
3533                                 M_BLEZ(REG_ITMP3, 2);
3534                                 M_ALD(REG_ITMP1, REG_ITMP1,
3535                                           OFFSET(vftbl_t, interfacetable[0]) -
3536                                           superindex * sizeof(methodptr*));
3537                                 M_CMPULT(REG_ZERO, REG_ITMP1, d);      /* REG_ITMP1 != 0  */
3538
3539                                 if (!super)
3540                                         M_BR(s3);
3541                         }
3542
3543                         /* class instanceof code */
3544
3545                         if (!super || !(super->flags & ACC_INTERFACE)) {
3546                                 if (super) {
3547                                         M_CLR(d);
3548                                         M_BEQZ(s1, s3);
3549
3550                                 } else {
3551                                         codegen_addpatchref(cd, mcodeptr,
3552                                                                                 PATCHER_checkcast_instanceof_class,
3553                                                                                 (constant_classref *) iptr->target);
3554
3555                                         if (showdisassemble)
3556                                                 M_NOP;
3557                                 }
3558
3559                                 M_ALD(REG_ITMP1, s1, OFFSET(java_objectheader, vftbl));
3560                                 a = dseg_addaddress(cd, supervftbl);
3561                                 M_ALD(REG_ITMP2, REG_PV, a);
3562 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3563                                 codegen_threadcritstart(cd, (u1 *) mcodeptr - cd->mcodebase);
3564 #endif
3565                                 M_ILD(REG_ITMP1, REG_ITMP1, OFFSET(vftbl_t, baseval));
3566                                 M_ILD(REG_ITMP3, REG_ITMP2, OFFSET(vftbl_t, baseval));
3567                                 M_ILD(REG_ITMP2, REG_ITMP2, OFFSET(vftbl_t, diffval));
3568 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3569                                 codegen_threadcritstop(cd, (u1 *) mcodeptr - cd->mcodebase);
3570 #endif
3571                                 M_ISUB(REG_ITMP1, REG_ITMP3, REG_ITMP1);
3572                                 M_CMPULE(REG_ITMP1, REG_ITMP2, d);
3573                         }
3574                         store_reg_to_var_int(iptr->dst, d);
3575                         }
3576                         break;
3577
3578
3579                 case ICMD_CHECKASIZE:  /* ..., size ==> ..., size                     */
3580
3581                         var_to_reg_int(s1, src, REG_ITMP1);
3582                         M_BLTZ(s1, 0);
3583                         codegen_addxcheckarefs(cd, mcodeptr);
3584                         break;
3585
3586                 case ICMD_CHECKEXCEPTION:    /* ... ==> ...                           */
3587
3588                         M_BEQZ(REG_RESULT, 0);
3589                         codegen_addxexceptionrefs(cd, mcodeptr);
3590                         break;
3591
3592                 case ICMD_MULTIANEWARRAY:/* ..., cnt1, [cnt2, ...] ==> ..., arrayref  */
3593                                       /* op1 = dimension, val.a = array descriptor    */
3594
3595                         /* check for negative sizes and copy sizes to stack if necessary  */
3596
3597                         MCODECHECK((iptr->op1 << 1) + 64);
3598
3599                         for (s1 = iptr->op1; --s1 >= 0; src = src->prev) {
3600                                 var_to_reg_int(s2, src, REG_ITMP1);
3601                                 M_BLTZ(s2, 0);
3602                                 codegen_addxcheckarefs(cd, mcodeptr);
3603
3604                                 /* copy SAVEDVAR sizes to stack */
3605
3606                                 if (src->varkind != ARGVAR) {
3607                                         M_LST(s2, REG_SP, s1 * 8);
3608                                 }
3609                         }
3610
3611                         /* is patcher function set? */
3612
3613                         if (iptr->target) {
3614                                 codegen_addpatchref(cd, mcodeptr,
3615                                                                         (functionptr) iptr->target, iptr->val.a);
3616
3617                                 if (showdisassemble)
3618                                         M_NOP;
3619
3620                                 a = 0;
3621
3622                         } else {
3623                                 a = (ptrint) iptr->val.a;
3624                         }
3625
3626                         /* a0 = dimension count */
3627
3628                         ICONST(rd->argintregs[0], iptr->op1);
3629
3630                         /* a1 = arraydescriptor */
3631
3632                         a = dseg_addaddress(cd, a);
3633                         M_ALD(rd->argintregs[1], REG_PV, a);
3634
3635                         /* a2 = pointer to dimensions = stack pointer */
3636
3637                         M_INTMOVE(REG_SP, rd->argintregs[2]);
3638
3639                         a = dseg_addaddress(cd, (void *) BUILTIN_multianewarray);
3640                         M_ALD(REG_PV, REG_PV, a);
3641                         M_JSR(REG_RA, REG_PV);
3642                         s1 = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3643                         if (s1 <= 32768)
3644                                 M_LDA(REG_PV, REG_RA, -s1);
3645                         else {
3646                                 s4 ml = -s1, mh = 0;
3647                                 while (ml < -32768) { ml += 65536; mh--; }
3648                                 M_LDA(REG_PV, REG_RA, ml);
3649                                 M_LDAH(REG_PV, REG_PV, mh);
3650                         }
3651                         s1 = reg_of_var(rd, iptr->dst, REG_RESULT);
3652                         M_INTMOVE(REG_RESULT, s1);
3653                         store_reg_to_var_int(iptr->dst, s1);
3654                         break;
3655
3656                 default:
3657                         throw_cacao_exception_exit(string_java_lang_InternalError,
3658                                                                            "Unknown ICMD %d", iptr->opc);
3659         } /* switch */
3660
3661         } /* for instruction */
3662
3663         /* copy values to interface registers */
3664
3665         src = bptr->outstack;
3666         len = bptr->outdepth;
3667         MCODECHECK(64+len);
3668 #ifdef LSRA
3669         if (!opt_lsra)
3670 #endif
3671         while (src) {
3672                 len--;
3673                 if ((src->varkind != STACKVAR)) {
3674                         s2 = src->type;
3675                         if (IS_FLT_DBL_TYPE(s2)) {
3676                                 var_to_reg_flt(s1, src, REG_FTMP1);
3677                                 if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
3678                                         M_FLTMOVE(s1,rd->interfaces[len][s2].regoff);
3679                                         }
3680                                 else {
3681                                         M_DST(s1, REG_SP, 8 * rd->interfaces[len][s2].regoff);
3682                                         }
3683                                 }
3684                         else {
3685                                 var_to_reg_int(s1, src, REG_ITMP1);
3686                                 if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
3687                                         M_INTMOVE(s1,rd->interfaces[len][s2].regoff);
3688                                         }
3689                                 else {
3690                                         M_LST(s1, REG_SP, 8 * rd->interfaces[len][s2].regoff);
3691                                         }
3692                                 }
3693                         }
3694                 src = src->prev;
3695                 }
3696         } /* if (bptr -> flags >= BBREACHED) */
3697         } /* for basic block */
3698
3699         codegen_createlinenumbertable(cd);
3700
3701         {
3702         /* generate bound check stubs */
3703
3704         s4 *xcodeptr = NULL;
3705         branchref *bref;
3706
3707         for (bref = cd->xboundrefs; bref != NULL; bref = bref->next) {
3708                 gen_resolvebranch((u1*) cd->mcodebase + bref->branchpos,
3709                                   bref->branchpos,
3710                                                   (u1*) mcodeptr - cd->mcodebase);
3711
3712                 MCODECHECK(8);
3713
3714                 /* move index register into REG_ITMP1 */
3715                 M_MOV(bref->reg, REG_ITMP1);
3716                 M_LDA(REG_ITMP2_XPC, REG_PV, bref->branchpos - 4);
3717
3718                 if (xcodeptr != NULL) {
3719                         M_BR(xcodeptr - mcodeptr - 1);
3720
3721                 } else {
3722                         xcodeptr = mcodeptr;
3723
3724                         a = dseg_addaddress(cd, asm_throw_and_handle_arrayindexoutofbounds_exception);
3725                         M_ALD(REG_PV, REG_PV, a);
3726
3727                         M_JSR(REG_RA, REG_PV);
3728
3729                         /* recompute pv */
3730                         s1 = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3731                         if (s1 <= 32768) M_LDA(REG_PV, REG_RA, -s1);
3732                         else {
3733                                 s4 ml = -s1, mh = 0;
3734                                 while (ml < -32768) { ml += 65536; mh--; }
3735                                 M_LDA(REG_PV, REG_RA, ml);
3736                                 M_LDAH(REG_PV, REG_PV, mh);
3737                         }
3738                 }
3739         }
3740
3741         /* generate negative array size check stubs */
3742
3743         xcodeptr = NULL;
3744
3745         for (bref = cd->xcheckarefs; bref != NULL; bref = bref->next) {
3746                 if ((cd->exceptiontablelength == 0) && (xcodeptr != NULL)) {
3747                         gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
3748                                                           bref->branchpos,
3749                                                           (u1 *) xcodeptr - (u1 *) cd->mcodebase - 4);
3750                         continue;
3751                 }
3752
3753                 gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
3754                                   bref->branchpos,
3755                                                   (u1 *) mcodeptr - cd->mcodebase);
3756
3757                 MCODECHECK(8);
3758
3759                 M_LDA(REG_ITMP2_XPC, REG_PV, bref->branchpos - 4);
3760
3761                 if (xcodeptr != NULL) {
3762                         M_BR(xcodeptr - mcodeptr - 1);
3763
3764                 } else {
3765                         xcodeptr = mcodeptr;
3766
3767                         a = dseg_addaddress(cd, string_java_lang_NegativeArraySizeException);
3768                         M_ALD(REG_ITMP1_XPTR,REG_PV,a);
3769
3770                         a = dseg_addaddress(cd, asm_throw_and_handle_nat_exception);
3771                         M_ALD(REG_PV, REG_PV, a);
3772
3773                         M_JSR(REG_RA, REG_PV);
3774
3775                         /* recompute pv */
3776                         s1 = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3777                         if (s1 <= 32768) M_LDA(REG_PV, REG_RA, -s1);
3778                         else {
3779                                 s4 ml = -s1, mh = 0;
3780                                 while (ml < -32768) { ml += 65536; mh--; }
3781                                 M_LDA(REG_PV, REG_RA, ml);
3782                                 M_LDAH(REG_PV, REG_PV, mh);
3783                         }
3784                 }
3785         }
3786
3787         /* generate cast check stubs */
3788
3789         xcodeptr = NULL;
3790
3791         for (bref = cd->xcastrefs; bref != NULL; bref = bref->next) {
3792                 if ((cd->exceptiontablelength == 0) && (xcodeptr != NULL)) {
3793                         gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
3794                                                           bref->branchpos,
3795                                                           (u1 *) xcodeptr - (u1 *) cd->mcodebase - 4);
3796                         continue;
3797                 }
3798
3799                 gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
3800                                   bref->branchpos,
3801                                                   (u1 *) mcodeptr - cd->mcodebase);
3802
3803                 MCODECHECK(8);
3804
3805                 M_LDA(REG_ITMP2_XPC, REG_PV, bref->branchpos - 4);
3806
3807                 if (xcodeptr != NULL) {
3808                         M_BR(xcodeptr - mcodeptr - 1);
3809
3810                 } else {
3811                         xcodeptr = mcodeptr;
3812
3813                         a = dseg_addaddress(cd, string_java_lang_ClassCastException);
3814                         M_ALD(REG_ITMP1_XPTR,REG_PV,a);
3815
3816                         a = dseg_addaddress(cd, asm_throw_and_handle_nat_exception);
3817                         M_ALD(REG_PV, REG_PV, a);
3818
3819                         M_JSR(REG_RA, REG_PV);
3820
3821                         /* recompute pv */
3822                         s1 = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3823                         if (s1 <= 32768) M_LDA(REG_PV, REG_RA, -s1);
3824                         else {
3825                                 s4 ml = -s1, mh = 0;
3826                                 while (ml < -32768) { ml += 65536; mh--; }
3827                                 M_LDA(REG_PV, REG_RA, ml);
3828                                 M_LDAH(REG_PV, REG_PV, mh);
3829                         }
3830                 }
3831         }
3832
3833         /* generate exception check stubs */
3834
3835         xcodeptr = NULL;
3836
3837         for (bref = cd->xexceptionrefs; bref != NULL; bref = bref->next) {
3838                 if ((cd->exceptiontablelength == 0) && (xcodeptr != NULL)) {
3839                         gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
3840                                                           bref->branchpos,
3841                                                           (u1 *) xcodeptr - (u1 *) cd->mcodebase - 4);
3842                         continue;
3843                 }
3844
3845                 gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
3846                                   bref->branchpos,
3847                                                   (u1 *) mcodeptr - cd->mcodebase);
3848
3849                 MCODECHECK(8);
3850
3851                 M_LDA(REG_ITMP2_XPC, REG_PV, bref->branchpos - 4);
3852
3853                 if (xcodeptr != NULL) {
3854                         M_BR(xcodeptr - mcodeptr - 1);
3855
3856                 } else {
3857                         xcodeptr = mcodeptr;
3858
3859 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3860                         M_LSUB_IMM(REG_SP, 1 * 8, REG_SP);
3861                         M_LST(REG_ITMP2_XPC, REG_SP, 0 * 8);
3862
3863                         a = dseg_addaddress(cd, &builtin_get_exceptionptrptr);
3864                         M_ALD(REG_PV, REG_PV, a);
3865                         M_JSR(REG_RA, REG_PV);
3866
3867                         /* recompute pv */
3868                         s1 = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3869                         if (s1 <= 32768) M_LDA(REG_PV, REG_RA, -s1);
3870                         else {
3871                                 s4 ml = -s1, mh = 0;
3872                                 while (ml < -32768) { ml += 65536; mh--; }
3873                                 M_LDA(REG_PV, REG_RA, ml);
3874                                 M_LDAH(REG_PV, REG_PV, mh);
3875                         }
3876
3877                         M_ALD(REG_ITMP1_XPTR, REG_RESULT, 0);
3878                         M_AST(REG_ZERO, REG_RESULT, 0);
3879
3880                         M_LLD(REG_ITMP2_XPC, REG_SP, 0 * 8);
3881                         M_LADD_IMM(REG_SP, 1 * 8, REG_SP);
3882 #else
3883                         a = dseg_addaddress(cd, &_exceptionptr);
3884                         M_ALD(REG_ITMP3, REG_PV, a);
3885                         M_ALD(REG_ITMP1_XPTR, REG_ITMP3, 0);
3886                         M_AST(REG_ZERO, REG_ITMP3, 0);
3887 #endif
3888
3889                         a = dseg_addaddress(cd, asm_refillin_and_handle_exception);
3890                         M_ALD(REG_PV, REG_PV, a);
3891
3892                         M_JMP(REG_RA, REG_PV);
3893
3894                         /* recompute pv */
3895                         s1 = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3896                         if (s1 <= 32768) M_LDA(REG_PV, REG_RA, -s1);
3897                         else {
3898                                 s4 ml = -s1, mh = 0;
3899                                 while (ml < -32768) { ml += 65536; mh--; }
3900                                 M_LDA(REG_PV, REG_RA, ml);
3901                                 M_LDAH(REG_PV, REG_PV, mh);
3902                         }
3903
3904                 }
3905         }
3906
3907         /* generate null pointer check stubs */
3908
3909         xcodeptr = NULL;
3910
3911         for (bref = cd->xnullrefs; bref != NULL; bref = bref->next) {
3912                 if ((cd->exceptiontablelength == 0) && (xcodeptr != NULL)) {
3913                         gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
3914                                                           bref->branchpos,
3915                                                           (u1 *) xcodeptr - (u1 *) cd->mcodebase - 4);
3916                         continue;
3917                 }
3918
3919                 gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
3920                                   bref->branchpos,
3921                                                   (u1 *) mcodeptr - cd->mcodebase);
3922
3923                 MCODECHECK(8);
3924
3925                 M_LDA(REG_ITMP2_XPC, REG_PV, bref->branchpos - 4);
3926
3927                 if (xcodeptr != NULL) {
3928                         M_BR(xcodeptr - mcodeptr - 1);
3929
3930                 } else {
3931                         xcodeptr = mcodeptr;
3932
3933                         a = dseg_addaddress(cd, string_java_lang_NullPointerException);
3934                         M_ALD(REG_ITMP1_XPTR,REG_PV,a);
3935
3936                         a = dseg_addaddress(cd, asm_throw_and_handle_nat_exception);
3937                         M_ALD(REG_PV, REG_PV, a);
3938
3939                         M_JSR(REG_RA, REG_PV);
3940
3941                         /* recompute pv */
3942                         s1 = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3943                         if (s1 <= 32768) M_LDA(REG_PV, REG_RA, -s1);
3944                         else {
3945                                 s4 ml = -s1, mh = 0;
3946                                 while (ml < -32768) { ml += 65536; mh--; }
3947                                 M_LDA(REG_PV, REG_RA, ml);
3948                                 M_LDAH(REG_PV, REG_PV, mh);
3949                         }
3950                 }
3951         }
3952
3953         /* generate put/getstatic stub call code */
3954
3955         {
3956                 patchref *pref;
3957                 u4        mcode;
3958                 s4       *tmpmcodeptr;
3959
3960                 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
3961                         /* check code segment size */
3962
3963                         MCODECHECK(13 + 4 + 1);
3964
3965                         /* Get machine code which is patched back in later. The call is   */
3966                         /* 1 instruction word long.                                       */
3967
3968                         xcodeptr = (s4 *) (cd->mcodebase + pref->branchpos);
3969                         mcode = *xcodeptr;
3970
3971                         /* patch in the call to call the following code (done at compile  */
3972                         /* time)                                                          */
3973
3974                         tmpmcodeptr = mcodeptr;         /* save current mcodeptr          */
3975                         mcodeptr = xcodeptr;            /* set mcodeptr to patch position */
3976
3977                         M_BSR(REG_ITMP3, tmpmcodeptr - (xcodeptr + 1));
3978
3979                         mcodeptr = tmpmcodeptr;         /* restore the current mcodeptr   */
3980
3981                         /* create stack frame */
3982
3983                         M_LSUB_IMM(REG_SP, 5 * 8, REG_SP);
3984
3985                         /* move return address onto stack */
3986
3987                         M_AST(REG_ITMP3, REG_SP, 4 * 8);
3988
3989                         /* move pointer to java_objectheader onto stack */
3990
3991 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3992                         /* create a virtual java_objectheader */
3993
3994                         (void) dseg_addaddress(cd, get_dummyLR());          /* monitorPtr */
3995                         a = dseg_addaddress(cd, NULL);                      /* vftbl      */
3996
3997                         if (a >= -32768) {
3998                                 M_LDA(REG_ITMP3, REG_PV, a);
3999                         } else {
4000                                 M_LDAH(REG_ITMP3, REG_PV, (a >> 16) & 0x0000ffff);
4001                                 M_LDA(REG_ITMP3, REG_ITMP3, a & 0x0000ffff);
4002                         }
4003                         M_AST(REG_ITMP3, REG_SP, 3 * 8);
4004 #else
4005                         M_AST(REG_ZERO, REG_SP, 3 * 8);
4006 #endif
4007
4008                         /* move machine code onto stack */
4009
4010                         a = dseg_adds4(cd, mcode);
4011                         if (a >= -32768) {
4012                                 M_ILD(REG_ITMP3, REG_PV, a);
4013                         } else {
4014                                 M_LDAH(REG_ITMP3, REG_PV, (a >> 16) & 0x0000ffff);
4015                                 M_ILD(REG_ITMP3, REG_ITMP3, a & 0x0000ffff);
4016                         }
4017                         M_IST(REG_ITMP3, REG_SP, 2 * 8);
4018
4019                         /* move class/method/field reference onto stack */
4020
4021                         a = dseg_addaddress(cd, pref->ref);
4022                         if (a >= -32768) {
4023                                 M_ALD(REG_ITMP3, REG_PV, a);
4024                         } else {
4025                                 M_LDAH(REG_ITMP3, REG_PV, (a >> 16) & 0x0000ffff);
4026                                 M_ALD(REG_ITMP3, REG_ITMP3, a & 0x0000ffff);
4027                         }
4028                         M_AST(REG_ITMP3, REG_SP, 1 * 8);
4029
4030                         /* move patcher function pointer onto stack */
4031
4032                         a = dseg_addaddress(cd, pref->patcher);
4033                         if (a >= -32768) {
4034                                 M_ALD(REG_ITMP3, REG_PV, a);
4035                         } else {
4036                                 M_LDAH(REG_ITMP3, REG_PV, (a >> 16) & 0x0000ffff);
4037                                 M_ALD(REG_ITMP3, REG_ITMP3, a & 0x0000ffff);
4038                         }
4039                         M_AST(REG_ITMP3, REG_SP, 0 * 8);
4040
4041                         a = dseg_addaddress(cd, asm_wrapper_patcher);
4042                         if (a >= -32768) {
4043                                 M_ALD(REG_ITMP3, REG_PV, a);
4044                         } else {
4045                                 M_LDAH(REG_ITMP3, REG_PV, (a >> 16) & 0x0000ffff);
4046                                 M_ALD(REG_ITMP3, REG_ITMP3, a & 0x0000ffff);
4047                         }
4048                         M_JMP(REG_ZERO, REG_ITMP3);
4049                 }
4050         }
4051         }
4052
4053         codegen_finish(m, cd, (s4) ((u1 *) mcodeptr - cd->mcodebase));
4054 }
4055
4056
4057 /* createcompilerstub **********************************************************
4058
4059    Creates a stub routine which calls the compiler.
4060
4061 *******************************************************************************/
4062
4063 #define COMPSTUBSIZE    3
4064
4065 functionptr createcompilerstub(methodinfo *m)
4066 {
4067         u8 *s = CNEW(u8, COMPSTUBSIZE);     /* memory to hold the stub            */
4068         s4 *mcodeptr = (s4 *) s;            /* code generation pointer            */
4069
4070                                             /* code for the stub                  */
4071         M_ALD(REG_PV, REG_PV, 16);          /* load pointer to the compiler       */
4072         M_JMP(0, REG_PV);                   /* jump to the compiler, return address
4073                                                in reg 0 is used as method pointer */
4074         s[1] = (ptrint) m;                  /* literals to be adressed            */
4075         s[2] = (ptrint) asm_call_jit_compiler; /* jump directly via PV from above */
4076
4077 #if defined(STATISTICS)
4078         if (opt_stat)
4079                 count_cstub_len += COMPSTUBSIZE * 8;
4080 #endif
4081
4082         return (functionptr) s;
4083 }
4084
4085
4086 /* createnativestub ************************************************************
4087
4088    Creates a stub routine which calls a native method.
4089
4090 *******************************************************************************/
4091
4092 functionptr createnativestub(functionptr f, methodinfo *m, codegendata *cd,
4093                                                          registerdata *rd, methoddesc *nmd)
4094 {
4095         s4         *mcodeptr;               /* code generation pointer            */
4096         s4          stackframesize;         /* size of stackframe if needed       */
4097         s4          disp;
4098         methoddesc *md;
4099         s4          nativeparams;
4100         s4          i, j;                   /* count variables                    */
4101         s4          t;
4102         s4          s1, s2, off;
4103
4104         /* initialize variables */
4105
4106         md = m->parseddesc;
4107         nativeparams = (m->flags & ACC_STATIC) ? 2 : 1;
4108
4109
4110         /* calculate stack frame size */
4111
4112         stackframesize =
4113                 1 +                             /* return address                     */
4114                 6 +                             /* dynamic stack info                 */
4115                 1 +                             /* methodinfo for call trace          */
4116                 (md->paramcount > INT_ARG_CNT ? INT_ARG_CNT : md->paramcount) +
4117                 nmd->memuse;
4118
4119
4120         /* create method header */
4121
4122         (void) dseg_addaddress(cd, m);                          /* MethodPointer  */
4123         (void) dseg_adds4(cd, stackframesize * 8);              /* FrameSize      */
4124         (void) dseg_adds4(cd, 0);                               /* IsSync         */
4125         (void) dseg_adds4(cd, 0);                               /* IsLeaf         */
4126         (void) dseg_adds4(cd, 0);                               /* IntSave        */
4127         (void) dseg_adds4(cd, 0);                               /* FltSave        */
4128         (void) dseg_addlinenumbertablesize(cd);
4129         (void) dseg_adds4(cd, 0);                               /* ExTableSize    */
4130
4131
4132         /* initialize mcode variables */
4133
4134         mcodeptr = (s4 *) cd->mcodebase;
4135         cd->mcodeend = (s4 *) (cd->mcodebase + cd->mcodesize);
4136
4137
4138         /* generate stub code */
4139
4140         M_LDA(REG_SP, REG_SP, -stackframesize * 8);
4141         M_AST(REG_RA, REG_SP, (stackframesize - 1) * 8);
4142
4143
4144         /* if function is static, check for initialized */
4145
4146         if ((m->flags & ACC_STATIC) && !m->class->initialized) {
4147                 codegen_addpatchref(cd, mcodeptr, PATCHER_clinit, m->class);
4148
4149                 if (showdisassemble)
4150                         M_NOP;
4151         }
4152
4153         /* call trace function */
4154
4155         if (runverbose) {
4156                 /* save integer argument registers */
4157
4158                 for (i = 0, j = 1; i < md->paramcount && i < INT_ARG_CNT; i++)
4159                         if (IS_INT_LNG_TYPE(md->paramtypes[i].type))
4160                                 M_LST(rd->argintregs[i], REG_SP, j++ * 8);
4161
4162                 /* save and copy float arguments into integer registers */
4163
4164                 for (i = 0; i < md->paramcount && i < FLT_ARG_CNT; i++) {
4165                         t = md->paramtypes[i].type;
4166
4167                         if (IS_FLT_DBL_TYPE(t)) {
4168                                 if (IS_2_WORD_TYPE(t)) {
4169                                         M_DST(rd->argfltregs[i], REG_SP, j * 8);
4170                                         M_LLD(rd->argintregs[i], REG_SP, j * 8);
4171                                 } else {
4172                                         M_FST(rd->argfltregs[i], REG_SP, j * 8);
4173                                         M_ILD(rd->argintregs[i], REG_SP, j * 8);
4174                                 }
4175                                 j++;
4176                         }
4177                 }
4178
4179                 off = dseg_addaddress(cd, m);
4180                 M_ALD(REG_ITMP1, REG_PV, off);
4181                 M_AST(REG_ITMP1, REG_SP, 0 * 8);
4182                 off = dseg_addaddress(cd, builtin_trace_args);
4183                 M_ALD(REG_PV, REG_PV, off);
4184                 M_JSR(REG_RA, REG_PV);
4185                 disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
4186                 M_LDA(REG_PV, REG_RA, -disp);
4187
4188                 for (i = 0, j = 1; i < md->paramcount && i < INT_ARG_CNT; i++)
4189                         if (IS_INT_LNG_TYPE(md->paramtypes[i].type))
4190                                 M_LLD(rd->argintregs[i], REG_SP, j++ * 8);
4191
4192                 for (i = 0; i < md->paramcount && i < FLT_ARG_CNT; i++) {
4193                         t = md->paramtypes[i].type;
4194
4195                         if (IS_FLT_DBL_TYPE(t)) {
4196                                 if (IS_2_WORD_TYPE(t)) {
4197                                         M_DLD(rd->argfltregs[i], REG_SP, j * 8);
4198                                 } else {
4199                                         M_FLD(rd->argfltregs[i], REG_SP, j * 8);
4200                                 }
4201                                 j++;
4202                         }
4203                 }
4204         }
4205
4206
4207         /* save integer and float argument registers */
4208
4209         for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++)
4210                 if (IS_INT_LNG_TYPE(md->paramtypes[i].type))
4211                         M_LST(rd->argintregs[i], REG_SP, j++ * 8);
4212
4213         for (i = 0; i < md->paramcount && i < FLT_ARG_CNT; i++)
4214                 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type))
4215                         M_DST(rd->argfltregs[i], REG_SP, j++ * 8);
4216
4217         /* create native stack info */
4218
4219         off = dseg_addaddress(cd, builtin_asm_get_stackframeinfo);
4220         M_ALD(REG_PV, REG_PV, off);
4221         M_JSR(REG_RA, REG_PV);
4222         disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
4223         M_LDA(REG_PV, REG_RA, -disp);
4224
4225         M_LST(REG_RESULT, REG_SP, (stackframesize - 5) * 8); /* save adress of pointer */
4226         M_LLD(REG_ITMP2, REG_RESULT, 0); /* get pointer */
4227         M_LST(REG_ITMP2, REG_SP, (stackframesize - 6) * 8); /* save old value */
4228         M_LDA(REG_ITMP3, REG_SP, (stackframesize - 6) * 8); /* calculate new value */
4229         M_LST(REG_ITMP3, REG_RESULT, 0); /* store new value */
4230         off = dseg_addaddress(cd, m);
4231         M_LLD(REG_ITMP2, REG_PV, off);
4232         M_LST(REG_ITMP2, REG_SP, (stackframesize - 4) * 8);
4233         M_LST(REG_ZERO, REG_SP, (stackframesize - 3) * 8);
4234         M_LST(REG_ZERO, REG_SP, (stackframesize - 2) * 8);
4235
4236         /* restore integer and float argument registers */
4237
4238         for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++)
4239                 if (IS_INT_LNG_TYPE(md->paramtypes[i].type))
4240                         M_LLD(rd->argintregs[i], REG_SP, j++ * 8);
4241
4242         for (i = 0; i < md->paramcount && i < FLT_ARG_CNT; i++)
4243                 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type))
4244                         M_DLD(rd->argfltregs[i], REG_SP, j++ * 8);
4245
4246
4247         /* copy or spill arguments to new locations */
4248
4249         for (i = md->paramcount - 1, j = i + nativeparams; i >= 0; i--, j--) {
4250                 t = md->paramtypes[i].type;
4251
4252                 if (IS_INT_LNG_TYPE(t)) {
4253                         if (!md->params[i].inmemory) {
4254                                 s1 = rd->argintregs[md->params[i].regoff];
4255
4256                                 if (!nmd->params[j].inmemory) {
4257                                         s2 = rd->argintregs[nmd->params[j].regoff];
4258                                         M_INTMOVE(s1, s2);
4259
4260                                 } else {
4261                                         s2 = nmd->params[j].regoff;
4262                                         M_LST(s1, REG_SP, s2 * 8);
4263                                 }
4264
4265                         } else {
4266                                 s1 = md->params[i].regoff + stackframesize;
4267                                 s2 = nmd->params[j].regoff;
4268                                 M_LLD(REG_ITMP1, REG_SP, s1 * 8);
4269                                 M_LST(REG_ITMP1, REG_SP, s2 * 8);
4270                         }
4271
4272                 } else {
4273                         if (!md->params[i].inmemory) {
4274                                 s1 = rd->argfltregs[md->params[i].regoff];
4275
4276                                 if (!nmd->params[j].inmemory) {
4277                                         s2 = rd->argfltregs[nmd->params[j].regoff];
4278                                         M_FLTMOVE(s1, s2);
4279
4280                                 } else {
4281                                         s2 = nmd->params[j].regoff;
4282                                         M_DST(s1, REG_SP, s2 * 8);
4283                                 }
4284
4285                         } else {
4286                                 s1 = md->params[i].regoff + stackframesize;
4287                                 s2 = nmd->params[j].regoff;
4288                                 M_DLD(REG_FTMP1, REG_SP, s1 * 8);
4289                                 M_DST(REG_FTMP1, REG_SP, s2 * 8);
4290                         }
4291                 }
4292         }
4293
4294         /* put class into second argument register */
4295
4296         if (m->flags & ACC_STATIC) {
4297                 off = dseg_addaddress(cd, m->class);
4298                 M_ALD(rd->argintregs[1], REG_PV, off);
4299         }
4300
4301         /* put env into first argument register */
4302
4303         off = dseg_addaddress(cd, &env);
4304         M_ALD(rd->argintregs[0], REG_PV, off);
4305
4306         /* do the native function call */
4307
4308 #if !defined(STATIC_CLASSPATH)
4309         if (f == NULL) {
4310                 codegen_addpatchref(cd, mcodeptr, PATCHER_resolve_native, m);
4311
4312                 if (showdisassemble)
4313                         M_NOP;
4314         }
4315 #endif
4316
4317         off = dseg_addaddress(cd, f);
4318         M_ALD(REG_PV, REG_PV, off);         /* load adress of native method       */
4319         M_JSR(REG_RA, REG_PV);              /* call native method                 */
4320         disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
4321         M_LDA(REG_PV, REG_RA, -disp);       /* recompute pv from ra               */
4322
4323
4324         /* remove native stack info */
4325
4326         M_LLD(REG_ITMP3, REG_SP, (stackframesize - 5) * 8); /* get address of stacktrace helper pointer */
4327         M_LLD(REG_ITMP1, REG_SP, (stackframesize - 6) * 8); /* get old value */
4328         M_LST(REG_ITMP1, REG_ITMP3, 0); /* set old value */
4329
4330
4331         /* call finished trace */
4332
4333         if (runverbose) {
4334                 M_LST(REG_RESULT, REG_SP, 0 * 8);
4335                 M_DST(REG_FRESULT, REG_SP, 1 * 8);
4336
4337                 off = dseg_addaddress(cd, m);
4338                 M_ALD(rd->argintregs[0], REG_PV, off);
4339
4340                 M_MOV(REG_RESULT, rd->argintregs[1]);
4341                 M_FMOV(REG_FRESULT, rd->argfltregs[2]);
4342                 M_FMOV(REG_FRESULT, rd->argfltregs[3]);
4343
4344                 off = dseg_addaddress(cd, builtin_displaymethodstop);
4345                 M_ALD(REG_PV, REG_PV, off);
4346                 M_JSR(REG_RA, REG_PV);
4347                 disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
4348                 M_LDA(REG_PV, REG_RA, -disp);
4349
4350                 M_LLD(REG_RESULT, REG_SP, 0 * 8);
4351                 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
4352         }
4353
4354
4355         /* check for exception */
4356
4357 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
4358         if (IS_FLT_DBL_TYPE(md->returntype.type))
4359                 M_DST(REG_FRESULT, REG_SP, 0 * 8);
4360         else
4361                 M_AST(REG_RESULT, REG_SP, 0 * 8);
4362
4363         off = dseg_addaddress(cd, builtin_get_exceptionptrptr);
4364         M_ALD(REG_PV, REG_PV, off);
4365         M_JSR(REG_RA, REG_PV);
4366         disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
4367         M_LDA(REG_PV, REG_RA, -disp);
4368         M_MOV(REG_RESULT, REG_ITMP3);
4369
4370         if (IS_FLT_DBL_TYPE(md->returntype.type))
4371                 M_DLD(REG_FRESULT, REG_SP, 0 * 8);
4372         else
4373                 M_ALD(REG_RESULT, REG_SP, 0 * 8);
4374 #else
4375         off = dseg_addaddress(cd, &_exceptionptr);
4376         M_ALD(REG_ITMP3, REG_PV, off);      /* get address of exceptionptr        */
4377 #endif
4378
4379         M_ALD(REG_ITMP1, REG_ITMP3, 0);     /* load exception into reg. itmp1     */
4380         M_BNEZ(REG_ITMP1, 3);               /* if no exception then return        */
4381
4382         M_ALD(REG_RA, REG_SP, (stackframesize - 1) * 8); /* load return address   */
4383
4384         M_LDA(REG_SP, REG_SP, stackframesize * 8);
4385
4386         M_RET(REG_ZERO, REG_RA);            /* return to caller                   */
4387
4388         /* handle exception */
4389
4390         M_AST(REG_ZERO, REG_ITMP3, 0);      /* store NULL into exceptionptr       */
4391
4392         M_ALD(REG_RA, REG_SP, (stackframesize - 1) * 8); /* load return address   */
4393         M_LDA(REG_ITMP2, REG_RA, -4);       /* move fault address into reg. itmp2 */
4394
4395         M_LDA(REG_SP, REG_SP, stackframesize * 8);
4396
4397         off = dseg_addaddress(cd, asm_handle_nat_exception);
4398         M_ALD(REG_ITMP3, REG_PV, off);      /* load asm exception handler address */
4399         M_JMP(REG_ZERO, REG_ITMP3);         /* jump to asm exception handler      */
4400
4401
4402         /* process patcher calls **************************************************/
4403
4404         {
4405                 patchref *pref;
4406                 s4       *xcodeptr;
4407                 u4        mcode;
4408                 s4       *tmpmcodeptr;
4409
4410                 /* there can only be one <clinit> ref entry                           */
4411                 pref = cd->patchrefs;
4412
4413                 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
4414                         /* Get machine code which is patched back in later. The call is   */
4415                         /* 1 instruction word long.                                       */
4416
4417                         xcodeptr = (s4 *) (cd->mcodebase + pref->branchpos);
4418                         mcode = (u4) *xcodeptr;
4419
4420                         /* patch in the call to call the following code (done at compile  */
4421                         /* time)                                                          */
4422
4423                         tmpmcodeptr = mcodeptr;         /* save current mcodeptr          */
4424                         mcodeptr = xcodeptr;            /* set mcodeptr to patch position */
4425
4426                         M_BSR(REG_ITMP3, tmpmcodeptr - (xcodeptr + 1));
4427
4428                         mcodeptr = tmpmcodeptr;         /* restore the current mcodeptr   */
4429
4430                         /* create stack frame                                             */
4431
4432                         M_LSUB_IMM(REG_SP, 5 * 8, REG_SP);
4433
4434                         /* move return address onto stack */
4435
4436                         M_AST(REG_ITMP3, REG_SP, 4 * 8);
4437
4438                         /* move pointer to java_objectheader onto stack */
4439
4440 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
4441                         /* create a virtual java_objectheader */
4442
4443                         (void) dseg_addaddress(cd, get_dummyLR());          /* monitorPtr */
4444                         off = dseg_addaddress(cd, NULL);                    /* vftbl      */
4445
4446                         M_LDA(REG_ITMP3, REG_PV, off);
4447                         M_AST(REG_ITMP3, REG_SP, 3 * 8);
4448 #else
4449                         M_AST(REG_ZERO, REG_SP, 3 * 8);
4450 #endif
4451
4452                         /* move machine code onto stack */
4453
4454                         off = dseg_adds4(cd, mcode);
4455                         M_ILD(REG_ITMP3, REG_PV, off);
4456                         M_IST(REG_ITMP3, REG_SP, 2 * 8);
4457
4458                         /* move class/method/field reference onto stack */
4459
4460                         off = dseg_addaddress(cd, pref->ref);
4461                         M_ALD(REG_ITMP3, REG_PV, off);
4462                         M_AST(REG_ITMP3, REG_SP, 1 * 8);
4463
4464                         /* move patcher function pointer onto stack */
4465
4466                         off = dseg_addaddress(cd, pref->patcher);
4467                         M_ALD(REG_ITMP3, REG_PV, off);
4468                         M_AST(REG_ITMP3, REG_SP, 0 * 8);
4469
4470                         off = dseg_addaddress(cd, asm_wrapper_patcher);
4471                         M_ALD(REG_ITMP3, REG_PV, off);
4472                         M_JMP(REG_ZERO, REG_ITMP3);
4473                 }
4474         }
4475
4476         codegen_finish(m, cd, (s4) ((u1 *) mcodeptr - cd->mcodebase));
4477
4478         return m->entrypoint;
4479 }
4480
4481
4482 /*
4483  * These are local overrides for various environment variables in Emacs.
4484  * Please do not remove this and leave it at the end of the file, where
4485  * Emacs will automagically detect them.
4486  * ---------------------------------------------------------------------
4487  * Local variables:
4488  * mode: c
4489  * indent-tabs-mode: t
4490  * c-basic-offset: 4
4491  * tab-width: 4
4492  * End:
4493  */