src/vm/jit/alpha/codegen.c

   1 /* src/vm/jit/alpha/codegen.c - machine code generator for Alpha
   2
   3    Copyright (C) 1996-2005, 2006 R. Grafl, A. Krall, C. Kruegel,
   4    C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
   5    E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
   6    J. Wenninger, Institut f. Computersprachen - TU Wien
   7
   8    This file is part of CACAO.
   9
  10    This program is free software; you can redistribute it and/or
  11    modify it under the terms of the GNU General Public License as
  12    published by the Free Software Foundation; either version 2, or (at
  13    your option) any later version.
  14
  15    This program is distributed in the hope that it will be useful, but
  16    WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18    General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program; if not, write to the Free Software
  22    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  23    02110-1301, USA.
  24
  25    Contact: cacao@cacaojvm.org
  26
  27    Authors: Andreas Krall
  28             Reinhard Grafl
  29
  30    Changes: Joseph Wenninger
  31             Christian Thalinger
  32             Christian Ullrich
  33             Edwin Steiner
  34
  35    $Id: codegen.c 4653 2006-03-18 04:14:17Z edwin $
  36
  37 */
  38
  39
  40 #include "config.h"
  41
  42 #include <assert.h>
  43 #include <stdio.h>
  44
  45 #include "vm/types.h"
  46
  47 #include "md.h"
  48 #include "md-abi.h"
  49
  50 #include "vm/jit/alpha/arch.h"
  51 #include "vm/jit/alpha/codegen.h"
  52
  53 #include "native/jni.h"
  54 #include "native/native.h"
  55 #include "vm/builtin.h"
  56 #include "vm/exceptions.h"
  57 #include "vm/global.h"
  58 #include "vm/loader.h"
  59 #include "vm/options.h"
  60 #include "vm/stringlocal.h"
  61 #include "vm/vm.h"
  62 #include "vm/jit/asmpart.h"
  63 #include "vm/jit/codegen-common.h"
  64 #include "vm/jit/dseg.h"
  65 #include "vm/jit/jit.h"
  66 #include "vm/jit/parse.h"
  67 #include "vm/jit/patcher.h"
  68 #include "vm/jit/reg.h"
  69 #include "vm/jit/replace.h"
  70
  71 #if defined(ENABLE_LSRA)
  72 # include "vm/jit/allocator/lsra.h"
  73 #endif
  74
  75
  76 /* codegen *********************************************************************
  77
  78    Generates machine code.
  79
  80 *******************************************************************************/
  81
  82 bool codegen(methodinfo *m, codegendata *cd, registerdata *rd)
  83 {
  84         s4                  len, s1, s2, s3, d, disp;
  85         s4                  parentargs_base;
  86         s4                 *mcodeptr;
  87         stackptr            src;
  88         varinfo            *var;
  89         basicblock         *bptr;
  90         instruction        *iptr;
  91         exceptiontable     *ex;
  92         u2                  currentline;
  93         methodinfo         *lm;             /* local methodinfo for ICMD_INVOKE*  */
  94         builtintable_entry *bte;
  95         methoddesc         *md;
  96         rplpoint           *replacementpoint;
  97
  98         /* prevent compiler warnings */
  99
 100         d = 0;
 101         currentline = 0;
 102         lm = NULL;
 103         bte = NULL;
 104
 105         {
 106         s4 i, p, t, l;
 107         s4 savedregs_num;
 108
 109         savedregs_num = (m->isleafmethod) ? 0 : 1;        /* space to save the RA */
 110
 111         /* space to save used callee saved registers */
 112
 113         savedregs_num += (INT_SAV_CNT - rd->savintreguse);
 114         savedregs_num += (FLT_SAV_CNT - rd->savfltreguse);
 115
 116         parentargs_base = rd->memuse + savedregs_num;
 117
 118 #if defined(USE_THREADS)           /* space to save argument of monitor_enter */
 119         if (checksync && (m->flags & ACC_SYNCHRONIZED))
 120                 parentargs_base++;
 121 #endif
 122
 123         /* create method header */
 124
 125         (void) dseg_addaddress(cd, m);                          /* MethodPointer  */
 126         (void) dseg_adds4(cd, parentargs_base * 8);             /* FrameSize      */
 127
 128 #if defined(USE_THREADS)
 129         /* IsSync contains the offset relative to the stack pointer for the
 130            argument of monitor_exit used in the exception handler. Since the
 131            offset could be zero and give a wrong meaning of the flag it is
 132            offset by one.
 133         */
 134
 135         if (checksync && (m->flags & ACC_SYNCHRONIZED))
 136                 (void) dseg_adds4(cd, (rd->memuse + 1) * 8);        /* IsSync         */
 137         else
 138 #endif
 139                 (void) dseg_adds4(cd, 0);                           /* IsSync         */
 140
 141         (void) dseg_adds4(cd, m->isleafmethod);                 /* IsLeaf         */
 142         (void) dseg_adds4(cd, INT_SAV_CNT - rd->savintreguse);  /* IntSave        */
 143         (void) dseg_adds4(cd, FLT_SAV_CNT - rd->savfltreguse);  /* FltSave        */
 144
 145         dseg_addlinenumbertablesize(cd);
 146
 147         (void) dseg_adds4(cd, cd->exceptiontablelength);        /* ExTableSize    */
 148
 149         /* create exception table */
 150
 151         for (ex = cd->exceptiontable; ex != NULL; ex = ex->down) {
 152                 dseg_addtarget(cd, ex->start);
 153                 dseg_addtarget(cd, ex->end);
 154                 dseg_addtarget(cd, ex->handler);
 155                 (void) dseg_addaddress(cd, ex->catchtype.cls);
 156         }
 157
 158         /* initialize mcode variables */
 159
 160         mcodeptr = (s4 *) cd->mcodeptr;
 161
 162         /* create stack frame (if necessary) */
 163
 164         if (parentargs_base)
 165                 M_LDA(REG_SP, REG_SP, -parentargs_base * 8);
 166
 167         /* save return address and used callee saved registers */
 168
 169         p = parentargs_base;
 170         if (!m->isleafmethod) {
 171                 p--; M_AST(REG_RA, REG_SP, p * 8);
 172         }
 173         for (i = INT_SAV_CNT - 1; i >= rd->savintreguse; i--) {
 174                 p--; M_LST(rd->savintregs[i], REG_SP, p * 8);
 175         }
 176         for (i = FLT_SAV_CNT - 1; i >= rd->savfltreguse; i--) {
 177                 p--; M_DST(rd->savfltregs[i], REG_SP, p * 8);
 178         }
 179
 180         /* take arguments out of register or stack frame */
 181
 182         md = m->parseddesc;
 183
 184         for (p = 0, l = 0; p < md->paramcount; p++) {
 185                 t = md->paramtypes[p].type;
 186                 var = &(rd->locals[l][t]);
 187                 l++;
 188                 if (IS_2_WORD_TYPE(t))    /* increment local counter for 2 word types */
 189                         l++;
 190                 if (var->type < 0)
 191                         continue;
 192                 s1 = md->params[p].regoff;
 193                 if (IS_INT_LNG_TYPE(t)) {                    /* integer args          */
 194                         if (!md->params[p].inmemory) {           /* register arguments    */
 195                                 s2 = rd->argintregs[s1];
 196                                 if (!(var->flags & INMEMORY)) {      /* reg arg -> register   */
 197                                         M_INTMOVE(s2, var->regoff);
 198
 199                                 } else {                             /* reg arg -> spilled    */
 200                                         M_LST(s2, REG_SP, var->regoff * 8);
 201                                 }
 202
 203                         } else {                                 /* stack arguments       */
 204                                 if (!(var->flags & INMEMORY)) {      /* stack arg -> register */
 205                                         M_LLD(var->regoff, REG_SP, (parentargs_base + s1) * 8);
 206
 207                                 } else {                             /* stack arg -> spilled  */
 208                                         var->regoff = parentargs_base + s1;
 209                                 }
 210                         }
 211
 212                 } else {                                     /* floating args         */
 213                         if (!md->params[p].inmemory) {           /* register arguments    */
 214                                 s2 = rd->argfltregs[s1];
 215                                 if (!(var->flags & INMEMORY)) {      /* reg arg -> register   */
 216                                         M_FLTMOVE(s2, var->regoff);
 217
 218                                 } else {                                         /* reg arg -> spilled    */
 219                                         M_DST(s2, REG_SP, var->regoff * 8);
 220                                 }
 221
 222                         } else {                                 /* stack arguments       */
 223                                 if (!(var->flags & INMEMORY)) {      /* stack-arg -> register */
 224                                         M_DLD(var->regoff, REG_SP, (parentargs_base + s1) * 8);
 225
 226                                 } else {                             /* stack-arg -> spilled  */
 227                                         var->regoff = parentargs_base + s1;
 228                                 }
 229                         }
 230                 }
 231         } /* end for */
 232
 233         /* call monitorenter function */
 234
 235 #if defined(USE_THREADS)
 236         if (checksync && (m->flags & ACC_SYNCHRONIZED)) {
 237                 /* stack offset for monitor argument */
 238
 239                 s1 = rd->memuse;
 240
 241                 if (opt_verbosecall) {
 242                         M_LDA(REG_SP, REG_SP, -(INT_ARG_CNT + FLT_ARG_CNT) * 8);
 243
 244                         for (p = 0; p < INT_ARG_CNT; p++)
 245                                 M_LST(rd->argintregs[p], REG_SP, p * 8);
 246
 247                         for (p = 0; p < FLT_ARG_CNT; p++)
 248                                 M_DST(rd->argfltregs[p], REG_SP, (INT_ARG_CNT + p) * 8);
 249
 250                         s1 += INT_ARG_CNT + FLT_ARG_CNT;
 251                 }
 252
 253                 /* decide which monitor enter function to call */
 254
 255                 if (m->flags & ACC_STATIC) {
 256                         disp = dseg_addaddress(cd, m->class);
 257                         M_ALD(rd->argintregs[0], REG_PV, disp);
 258                         M_AST(rd->argintregs[0], REG_SP, s1 * 8);
 259                         disp = dseg_addaddress(cd, BUILTIN_staticmonitorenter);
 260                         M_ALD(REG_PV, REG_PV, disp);
 261                         M_JSR(REG_RA, REG_PV);
 262                         disp = -(s4) ((u1 *) mcodeptr - cd->mcodebase);
 263                         M_LDA(REG_PV, REG_RA, disp);
 264
 265                 } else {
 266                         M_BEQZ(rd->argintregs[0], 0);
 267                         codegen_add_nullpointerexception_ref(cd, mcodeptr);
 268                         M_AST(rd->argintregs[0], REG_SP, s1 * 8);
 269                         disp = dseg_addaddress(cd, BUILTIN_monitorenter);
 270                         M_ALD(REG_PV, REG_PV, disp);
 271                         M_JSR(REG_RA, REG_PV);
 272                         disp = -(s4) ((u1 *) mcodeptr - cd->mcodebase);
 273                         M_LDA(REG_PV, REG_RA, disp);
 274                 }
 275
 276                 if (opt_verbosecall) {
 277                         for (p = 0; p < INT_ARG_CNT; p++)
 278                                 M_LLD(rd->argintregs[p], REG_SP, p * 8);
 279
 280                         for (p = 0; p < FLT_ARG_CNT; p++)
 281                                 M_DLD(rd->argfltregs[p], REG_SP, (INT_ARG_CNT + p) * 8);
 282
 283                         M_LDA(REG_SP, REG_SP, (INT_ARG_CNT + FLT_ARG_CNT) * 8);
 284                 }
 285         }
 286 #endif
 287
 288         /* call trace function */
 289
 290         if (opt_verbosecall) {
 291                 M_LDA(REG_SP, REG_SP, -((INT_ARG_CNT + FLT_ARG_CNT + 2) * 8));
 292                 M_AST(REG_RA, REG_SP, 1 * 8);
 293
 294                 /* save integer argument registers */
 295
 296                 for (p = 0; p < md->paramcount && p < INT_ARG_CNT; p++)
 297                         M_LST(rd->argintregs[p], REG_SP, (2 + p) * 8);
 298
 299                 /* save and copy float arguments into integer registers */
 300
 301                 for (p = 0; p < md->paramcount && p < FLT_ARG_CNT; p++) {
 302                         t = md->paramtypes[p].type;
 303
 304                         if (IS_FLT_DBL_TYPE(t)) {
 305                                 if (IS_2_WORD_TYPE(t)) {
 306                                         M_DST(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 307
 308                                 } else {
 309                                         M_FST(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 310                                 }
 311
 312                                 M_LLD(rd->argintregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 313
 314                         } else {
 315                                 M_DST(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 316                         }
 317                 }
 318
 319                 disp = dseg_addaddress(cd, m);
 320                 M_ALD(REG_ITMP1, REG_PV, disp);
 321                 M_AST(REG_ITMP1, REG_SP, 0 * 8);
 322                 disp = dseg_addaddress(cd, (void *) builtin_trace_args);
 323                 M_ALD(REG_PV, REG_PV, disp);
 324                 M_JSR(REG_RA, REG_PV);
 325                 disp = -(s4) ((u1 *) mcodeptr - cd->mcodebase);
 326                 M_LDA(REG_PV, REG_RA, disp);
 327                 M_ALD(REG_RA, REG_SP, 1 * 8);
 328
 329                 /* restore integer argument registers */
 330
 331                 for (p = 0; p < md->paramcount && p < INT_ARG_CNT; p++)
 332                         M_LLD(rd->argintregs[p], REG_SP, (2 + p) * 8);
 333
 334                 /* restore float argument registers */
 335
 336                 for (p = 0; p < md->paramcount && p < FLT_ARG_CNT; p++) {
 337                         t = md->paramtypes[p].type;
 338
 339                         if (IS_FLT_DBL_TYPE(t)) {
 340                                 if (IS_2_WORD_TYPE(t)) {
 341                                         M_DLD(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 342
 343                                 } else {
 344                                         M_FLD(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 345                                 }
 346
 347                         } else {
 348                                 M_DLD(rd->argfltregs[p], REG_SP, (2 + INT_ARG_CNT + p) * 8);
 349                         }
 350                 }
 351
 352                 M_LDA(REG_SP, REG_SP, (INT_ARG_CNT + FLT_ARG_CNT + 2) * 8);
 353         }
 354
 355         }
 356
 357         /* end of header generation */
 358
 359         replacementpoint = cd->code->rplpoints;
 360
 361         /* walk through all basic blocks */
 362
 363         for (bptr = m->basicblocks; bptr != NULL; bptr = bptr->next) {
 364
 365                 bptr->mpc = (s4) ((u1 *) mcodeptr - cd->mcodebase);
 366
 367                 if (bptr->flags >= BBREACHED) {
 368
 369                 /* branch resolving */
 370
 371                 {
 372                 branchref *brefs;
 373                 for (brefs = bptr->branchrefs; brefs != NULL; brefs = brefs->next) {
 374                         gen_resolvebranch((u1*) cd->mcodebase + brefs->branchpos,
 375                                           brefs->branchpos, bptr->mpc);
 376                         }
 377                 }
 378
 379                 /* handle replacement points */
 380
 381                 if (bptr->bitflags & BBFLAG_REPLACEMENT) {
 382                         replacementpoint->pc = (u1*)(ptrint)bptr->mpc; /* will be resolved later */
 383
 384                         replacementpoint++;
 385                 }
 386
 387                 /* copy interface registers to their destination */
 388
 389                 src = bptr->instack;
 390                 len = bptr->indepth;
 391                 MCODECHECK(64+len);
 392 #if defined(ENABLE_LSRA)
 393                 if (opt_lsra) {
 394                 while (src != NULL) {
 395                         len--;
 396                         if ((len == 0) && (bptr->type != BBTYPE_STD)) {
 397                                         /*                              d = reg_of_var(m, src, REG_ITMP1); */
 398                                         if (!(src->flags & INMEMORY))
 399                                                 d = src->regoff;
 400                                         else
 401                                                 d = REG_ITMP1;
 402                                         M_INTMOVE(REG_ITMP1, d);
 403                                         store_reg_to_var_int(src, d);
 404                                 }
 405                                 src = src->prev;
 406                         }
 407                 } else {
 408 #endif
 409                         while (src != NULL) {
 410                                 len--;
 411                                 if ((len == 0) && (bptr->type != BBTYPE_STD)) {
 412                                         d = reg_of_var(rd, src, REG_ITMP1);
 413                                         M_INTMOVE(REG_ITMP1, d);
 414                                         store_reg_to_var_int(src, d);
 415                                 } else {
 416                                         d = reg_of_var(rd, src, REG_IFTMP);
 417                                         if ((src->varkind != STACKVAR)) {
 418                                                 s2 = src->type;
 419                                                 if (IS_FLT_DBL_TYPE(s2)) {
 420                                                         if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
 421                                                                 s1 = rd->interfaces[len][s2].regoff;
 422                                                                 M_FLTMOVE(s1, d);
 423                                                         } else {
 424                                                                 M_DLD(d, REG_SP, rd->interfaces[len][s2].regoff * 8);
 425                                                         }
 426                                                         store_reg_to_var_flt(src, d);
 427                                                 }
 428                                                 else {
 429                                                         if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
 430                                                                 s1 = rd->interfaces[len][s2].regoff;
 431                                                                 M_INTMOVE(s1, d);
 432                                                         } else {
 433                                                                 M_LLD(d, REG_SP, rd->interfaces[len][s2].regoff * 8);
 434                                                         }
 435                                                         store_reg_to_var_int(src, d);
 436                                                 }
 437                                         }
 438                                 }
 439                                 src = src->prev;
 440                         }
 441 #if defined(ENABLE_LSRA)
 442                 }
 443 #endif
 444
 445                 /* walk through all instructions */
 446
 447                 src = bptr->instack;
 448                 len = bptr->icount;
 449
 450                 for (iptr = bptr->iinstr; len > 0; src = iptr->dst, len--, iptr++) {
 451                         if (iptr->line != currentline) {
 452                                 dseg_addlinenumber(cd, iptr->line, (u1 *) mcodeptr);
 453                                 currentline = iptr->line;
 454                         }
 455
 456                 MCODECHECK(64);       /* an instruction usually needs < 64 words      */
 457                 switch (iptr->opc) {
 458
 459                 case ICMD_INLINE_START:
 460                 case ICMD_INLINE_END:
 461                         break;
 462
 463                 case ICMD_NOP:        /* ...  ==> ...                                 */
 464                         break;
 465
 466                 case ICMD_CHECKNULL:  /* ..., objectref  ==> ..., objectref           */
 467
 468                         var_to_reg_int(s1, src, REG_ITMP1);
 469                         M_BEQZ(s1, 0);
 470                         codegen_add_nullpointerexception_ref(cd, mcodeptr);
 471                         break;
 472
 473                 /* constant operations ************************************************/
 474
 475                 case ICMD_ICONST:     /* ...  ==> ..., constant                       */
 476                                       /* op1 = 0, val.i = constant                    */
 477
 478                         d = reg_of_var(rd, iptr->dst, REG_ITMP1);
 479                         ICONST(d, iptr->val.i);
 480                         store_reg_to_var_int(iptr->dst, d);
 481                         break;
 482
 483                 case ICMD_LCONST:     /* ...  ==> ..., constant                       */
 484                                       /* op1 = 0, val.l = constant                    */
 485
 486                         d = reg_of_var(rd, iptr->dst, REG_ITMP1);
 487                         LCONST(d, iptr->val.l);
 488                         store_reg_to_var_int(iptr->dst, d);
 489                         break;
 490
 491                 case ICMD_FCONST:     /* ...  ==> ..., constant                       */
 492                                       /* op1 = 0, val.f = constant                    */
 493
 494                         d = reg_of_var(rd, iptr->dst, REG_FTMP1);
 495                         disp = dseg_addfloat(cd, iptr->val.f);
 496                         M_FLD(d, REG_PV, disp);
 497                         store_reg_to_var_flt(iptr->dst, d);
 498                         break;
 499
 500                 case ICMD_DCONST:     /* ...  ==> ..., constant                       */
 501                                       /* op1 = 0, val.d = constant                    */
 502
 503                         d = reg_of_var(rd, iptr->dst, REG_FTMP1);
 504                         disp = dseg_adddouble(cd, iptr->val.d);
 505                         M_DLD(d, REG_PV, disp);
 506                         store_reg_to_var_flt(iptr->dst, d);
 507                         break;
 508
 509                 case ICMD_ACONST:     /* ...  ==> ..., constant                       */
 510                                       /* op1 = 0, val.a = constant                    */
 511
 512                         d = reg_of_var(rd, iptr->dst, REG_ITMP1);
 513
 514                         if ((iptr->target != NULL) && (iptr->val.a == NULL)) {
 515                                 disp = dseg_addaddress(cd, iptr->val.a);
 516
 517                                 codegen_addpatchref(cd, mcodeptr,
 518                                                                         PATCHER_aconst,
 519                                                                         (unresolved_class *) iptr->target, disp);
 520
 521                                 if (opt_showdisassemble)
 522                                         M_NOP;
 523
 524                                 M_ALD(d, REG_PV, disp);
 525
 526                         } else {
 527                                 if (iptr->val.a == NULL) {
 528                                         M_INTMOVE(REG_ZERO, d);
 529                                 } else {
 530                                         disp = dseg_addaddress(cd, iptr->val.a);
 531                                         M_ALD(d, REG_PV, disp);
 532                                 }
 533                         }
 534                         store_reg_to_var_int(iptr->dst, d);
 535                         break;
 536
 537
 538                 /* load/store operations **********************************************/
 539
 540                 case ICMD_ILOAD:      /* ...  ==> ..., content of local variable      */
 541                 case ICMD_LLOAD:      /* op1 = local variable                         */
 542                 case ICMD_ALOAD:
 543
 544                         d = reg_of_var(rd, iptr->dst, REG_ITMP1);
 545                         if ((iptr->dst->varkind == LOCALVAR) &&
 546                             (iptr->dst->varnum == iptr->op1))
 547                                 break;
 548                         var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
 549                         if (var->flags & INMEMORY) {
 550                                 M_LLD(d, REG_SP, var->regoff * 8);
 551                         } else {
 552                                 M_INTMOVE(var->regoff, d);
 553                         }
 554                         store_reg_to_var_int(iptr->dst, d);
 555                         break;
 556
 557                 case ICMD_FLOAD:      /* ...  ==> ..., content of local variable      */
 558                 case ICMD_DLOAD:      /* op1 = local variable                         */
 559
 560                         d = reg_of_var(rd, iptr->dst, REG_FTMP1);
 561                         if ((iptr->dst->varkind == LOCALVAR) &&
 562                             (iptr->dst->varnum == iptr->op1))
 563                                 break;
 564                         var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
 565                         if (var->flags & INMEMORY) {
 566                                 M_DLD(d, REG_SP, var->regoff * 8);
 567                         } else {
 568                                 M_FLTMOVE(var->regoff, d);
 569                         }
 570                         store_reg_to_var_flt(iptr->dst, d);
 571                         break;
 572
 573
 574                 case ICMD_ISTORE:     /* ..., value  ==> ...                          */
 575                 case ICMD_LSTORE:     /* op1 = local variable                         */
 576                 case ICMD_ASTORE:
 577
 578                         if ((src->varkind == LOCALVAR) &&
 579                             (src->varnum == iptr->op1))
 580                                 break;
 581                         var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
 582                         if (var->flags & INMEMORY) {
 583                                 var_to_reg_int(s1, src, REG_ITMP1);
 584                                 M_LST(s1, REG_SP, var->regoff * 8);
 585                         } else {
 586                                 var_to_reg_int(s1, src, var->regoff);
 587                                 M_INTMOVE(s1, var->regoff);
 588                         }
 589                         break;
 590
 591                 case ICMD_FSTORE:     /* ..., value  ==> ...                          */
 592                 case ICMD_DSTORE:     /* op1 = local variable                         */
 593
 594                         if ((src->varkind == LOCALVAR) &&
 595                             (src->varnum == iptr->op1))
 596                                 break;
 597                         var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
 598                         if (var->flags & INMEMORY) {
 599                                 var_to_reg_flt(s1, src, REG_FTMP1);
 600                                 M_DST(s1, REG_SP, var->regoff * 8);
 601                         } else {
 602                                 var_to_reg_flt(s1, src, var->regoff);
 603                                 M_FLTMOVE(s1, var->regoff);
 604                         }
 605                         break;
 606
 607
 608                 /* pop/dup/swap operations ********************************************/
 609
 610                 /* attention: double and longs are only one entry in CACAO ICMDs      */
 611
 612                 case ICMD_POP:        /* ..., value  ==> ...                          */
 613                 case ICMD_POP2:       /* ..., value, value  ==> ...                   */
 614                         break;
 615
 616                 case ICMD_DUP:        /* ..., a ==> ..., a, a                         */
 617                         M_COPY(src, iptr->dst);
 618                         break;
 619
 620                 case ICMD_DUP_X1:     /* ..., a, b ==> ..., b, a, b                   */
 621
 622                         M_COPY(src,       iptr->dst);
 623                         M_COPY(src->prev, iptr->dst->prev);
 624                         M_COPY(iptr->dst, iptr->dst->prev->prev);
 625                         break;
 626
 627                 case ICMD_DUP_X2:     /* ..., a, b, c ==> ..., c, a, b, c             */
 628
 629                         M_COPY(src,             iptr->dst);
 630                         M_COPY(src->prev,       iptr->dst->prev);
 631                         M_COPY(src->prev->prev, iptr->dst->prev->prev);
 632                         M_COPY(iptr->dst,       iptr->dst->prev->prev->prev);
 633                         break;
 634
 635                 case ICMD_DUP2:       /* ..., a, b ==> ..., a, b, a, b                */
 636
 637                         M_COPY(src,       iptr->dst);
 638                         M_COPY(src->prev, iptr->dst->prev);
 639                         break;
 640
 641                 case ICMD_DUP2_X1:    /* ..., a, b, c ==> ..., b, c, a, b, c          */
 642
 643                         M_COPY(src,             iptr->dst);
 644                         M_COPY(src->prev,       iptr->dst->prev);
 645                         M_COPY(src->prev->prev, iptr->dst->prev->prev);
 646                         M_COPY(iptr->dst,       iptr->dst->prev->prev->prev);
 647                         M_COPY(iptr->dst->prev, iptr->dst->prev->prev->prev->prev);
 648                         break;
 649
 650                 case ICMD_DUP2_X2:    /* ..., a, b, c, d ==> ..., c, d, a, b, c, d    */
 651
 652                         M_COPY(src,                   iptr->dst);
 653                         M_COPY(src->prev,             iptr->dst->prev);
 654                         M_COPY(src->prev->prev,       iptr->dst->prev->prev);
 655                         M_COPY(src->prev->prev->prev, iptr->dst->prev->prev->prev);
 656                         M_COPY(iptr->dst,             iptr->dst->prev->prev->prev->prev);
 657                         M_COPY(iptr->dst->prev,       iptr->dst->prev->prev->prev->prev->prev);
 658                         break;
 659
 660                 case ICMD_SWAP:       /* ..., a, b ==> ..., b, a                      */
 661
 662                         M_COPY(src,       iptr->dst->prev);
 663                         M_COPY(src->prev, iptr->dst);
 664                         break;
 665
 666
 667                 /* integer operations *************************************************/
 668
 669                 case ICMD_INEG:       /* ..., value  ==> ..., - value                 */
 670
 671                         var_to_reg_int(s1, src, REG_ITMP1);
 672                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 673                         M_ISUB(REG_ZERO, s1, d);
 674                         store_reg_to_var_int(iptr->dst, d);
 675                         break;
 676
 677                 case ICMD_LNEG:       /* ..., value  ==> ..., - value                 */
 678
 679                         var_to_reg_int(s1, src, REG_ITMP1);
 680                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 681                         M_LSUB(REG_ZERO, s1, d);
 682                         store_reg_to_var_int(iptr->dst, d);
 683                         break;
 684
 685                 case ICMD_I2L:        /* ..., value  ==> ..., value                   */
 686
 687                         var_to_reg_int(s1, src, REG_ITMP1);
 688                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 689                         M_INTMOVE(s1, d);
 690                         store_reg_to_var_int(iptr->dst, d);
 691                         break;
 692
 693                 case ICMD_L2I:        /* ..., value  ==> ..., value                   */
 694
 695                         var_to_reg_int(s1, src, REG_ITMP1);
 696                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 697                         M_IADD(s1, REG_ZERO, d);
 698                         store_reg_to_var_int(iptr->dst, d);
 699                         break;
 700
 701                 case ICMD_INT2BYTE:   /* ..., value  ==> ..., value                   */
 702
 703                         var_to_reg_int(s1, src, REG_ITMP1);
 704                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 705                         if (has_ext_instr_set) {
 706                                 M_BSEXT(s1, d);
 707                         } else {
 708                                 M_SLL_IMM(s1, 56, d);
 709                                 M_SRA_IMM( d, 56, d);
 710                         }
 711                         store_reg_to_var_int(iptr->dst, d);
 712                         break;
 713
 714                 case ICMD_INT2CHAR:   /* ..., value  ==> ..., value                   */
 715
 716                         var_to_reg_int(s1, src, REG_ITMP1);
 717                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 718             M_CZEXT(s1, d);
 719                         store_reg_to_var_int(iptr->dst, d);
 720                         break;
 721
 722                 case ICMD_INT2SHORT:  /* ..., value  ==> ..., value                   */
 723
 724                         var_to_reg_int(s1, src, REG_ITMP1);
 725                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 726                         if (has_ext_instr_set) {
 727                                 M_SSEXT(s1, d);
 728                         } else {
 729                                 M_SLL_IMM(s1, 48, d);
 730                                 M_SRA_IMM( d, 48, d);
 731                         }
 732                         store_reg_to_var_int(iptr->dst, d);
 733                         break;
 734
 735
 736                 case ICMD_IADD:       /* ..., val1, val2  ==> ..., val1 + val2        */
 737
 738                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 739                         var_to_reg_int(s2, src, REG_ITMP2);
 740                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 741                         M_IADD(s1, s2, d);
 742                         store_reg_to_var_int(iptr->dst, d);
 743                         break;
 744
 745                 case ICMD_IADDCONST:  /* ..., value  ==> ..., value + constant        */
 746                                       /* val.i = constant                             */
 747
 748                         var_to_reg_int(s1, src, REG_ITMP1);
 749                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 750                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
 751                                 M_IADD_IMM(s1, iptr->val.i, d);
 752                         } else {
 753                                 ICONST(REG_ITMP2, iptr->val.i);
 754                                 M_IADD(s1, REG_ITMP2, d);
 755                         }
 756                         store_reg_to_var_int(iptr->dst, d);
 757                         break;
 758
 759                 case ICMD_LADD:       /* ..., val1, val2  ==> ..., val1 + val2        */
 760
 761                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 762                         var_to_reg_int(s2, src, REG_ITMP2);
 763                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 764                         M_LADD(s1, s2, d);
 765                         store_reg_to_var_int(iptr->dst, d);
 766                         break;
 767
 768                 case ICMD_LADDCONST:  /* ..., value  ==> ..., value + constant        */
 769                                       /* val.l = constant                             */
 770
 771                         var_to_reg_int(s1, src, REG_ITMP1);
 772                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 773                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
 774                                 M_LADD_IMM(s1, iptr->val.l, d);
 775                         } else {
 776                                 LCONST(REG_ITMP2, iptr->val.l);
 777                                 M_LADD(s1, REG_ITMP2, d);
 778                         }
 779                         store_reg_to_var_int(iptr->dst, d);
 780                         break;
 781
 782                 case ICMD_ISUB:       /* ..., val1, val2  ==> ..., val1 - val2        */
 783
 784                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 785                         var_to_reg_int(s2, src, REG_ITMP2);
 786                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 787                         M_ISUB(s1, s2, d);
 788                         store_reg_to_var_int(iptr->dst, d);
 789                         break;
 790
 791                 case ICMD_ISUBCONST:  /* ..., value  ==> ..., value + constant        */
 792                                       /* val.i = constant                             */
 793
 794                         var_to_reg_int(s1, src, REG_ITMP1);
 795                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 796                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
 797                                 M_ISUB_IMM(s1, iptr->val.i, d);
 798                         } else {
 799                                 ICONST(REG_ITMP2, iptr->val.i);
 800                                 M_ISUB(s1, REG_ITMP2, d);
 801                         }
 802                         store_reg_to_var_int(iptr->dst, d);
 803                         break;
 804
 805                 case ICMD_LSUB:       /* ..., val1, val2  ==> ..., val1 - val2        */
 806
 807                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 808                         var_to_reg_int(s2, src, REG_ITMP2);
 809                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 810                         M_LSUB(s1, s2, d);
 811                         store_reg_to_var_int(iptr->dst, d);
 812                         break;
 813
 814                 case ICMD_LSUBCONST:  /* ..., value  ==> ..., value - constant        */
 815                                       /* val.l = constant                             */
 816
 817                         var_to_reg_int(s1, src, REG_ITMP1);
 818                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 819                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
 820                                 M_LSUB_IMM(s1, iptr->val.l, d);
 821                         } else {
 822                                 LCONST(REG_ITMP2, iptr->val.l);
 823                                 M_LSUB(s1, REG_ITMP2, d);
 824                         }
 825                         store_reg_to_var_int(iptr->dst, d);
 826                         break;
 827
 828                 case ICMD_IMUL:       /* ..., val1, val2  ==> ..., val1 * val2        */
 829
 830                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 831                         var_to_reg_int(s2, src, REG_ITMP2);
 832                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 833                         M_IMUL(s1, s2, d);
 834                         store_reg_to_var_int(iptr->dst, d);
 835                         break;
 836
 837                 case ICMD_IMULCONST:  /* ..., value  ==> ..., value * constant        */
 838                                       /* val.i = constant                             */
 839
 840                         var_to_reg_int(s1, src, REG_ITMP1);
 841                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 842                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
 843                                 M_IMUL_IMM(s1, iptr->val.i, d);
 844                         } else {
 845                                 ICONST(REG_ITMP2, iptr->val.i);
 846                                 M_IMUL(s1, REG_ITMP2, d);
 847                         }
 848                         store_reg_to_var_int(iptr->dst, d);
 849                         break;
 850
 851                 case ICMD_LMUL:       /* ..., val1, val2  ==> ..., val1 * val2        */
 852
 853                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 854                         var_to_reg_int(s2, src, REG_ITMP2);
 855                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 856                         M_LMUL(s1, s2, d);
 857                         store_reg_to_var_int(iptr->dst, d);
 858                         break;
 859
 860                 case ICMD_LMULCONST:  /* ..., value  ==> ..., value * constant        */
 861                                       /* val.l = constant                             */
 862
 863                         var_to_reg_int(s1, src, REG_ITMP1);
 864                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 865                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
 866                                 M_LMUL_IMM(s1, iptr->val.l, d);
 867                         } else {
 868                                 LCONST(REG_ITMP2, iptr->val.l);
 869                                 M_LMUL(s1, REG_ITMP2, d);
 870                         }
 871                         store_reg_to_var_int(iptr->dst, d);
 872                         break;
 873
 874                 case ICMD_IDIV:       /* ..., val1, val2  ==> ..., val1 / val2        */
 875                 case ICMD_IREM:       /* ..., val1, val2  ==> ..., val1 % val2        */
 876
 877                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 878                         var_to_reg_int(s2, src, REG_ITMP2);
 879                         d = reg_of_var(rd, iptr->dst, REG_RESULT);
 880                         M_BEQZ(s2, 0);
 881                         codegen_add_arithmeticexception_ref(cd, mcodeptr);
 882
 883                         M_MOV(s1, rd->argintregs[0]);
 884                         M_MOV(s2, rd->argintregs[1]);
 885                         bte = iptr->val.a;
 886                         disp = dseg_addaddress(cd, bte->fp);
 887                         M_ALD(REG_PV, REG_PV, disp);
 888                         M_JSR(REG_RA, REG_PV);
 889                         disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
 890                         M_LDA(REG_PV, REG_RA, -disp);
 891
 892                         M_IADD(REG_RESULT, REG_ZERO, d); /* sign extend (bugfix for gcc -O2) */
 893                         store_reg_to_var_int(iptr->dst, d);
 894                         break;
 895
 896                 case ICMD_LDIV:       /* ..., val1, val2  ==> ..., val1 / val2        */
 897                 case ICMD_LREM:       /* ..., val1, val2  ==> ..., val1 % val2        */
 898
 899                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 900                         var_to_reg_int(s2, src, REG_ITMP2);
 901                         d = reg_of_var(rd, iptr->dst, REG_RESULT);
 902                         M_BEQZ(s2, 0);
 903                         codegen_add_arithmeticexception_ref(cd, mcodeptr);
 904
 905                         M_MOV(s1, rd->argintregs[0]);
 906                         M_MOV(s2, rd->argintregs[1]);
 907                         bte = iptr->val.a;
 908                         disp = dseg_addaddress(cd, bte->fp);
 909                         M_ALD(REG_PV, REG_PV, disp);
 910                         M_JSR(REG_RA, REG_PV);
 911                         disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
 912                         M_LDA(REG_PV, REG_RA, -disp);
 913
 914                         M_INTMOVE(REG_RESULT, d);
 915                         store_reg_to_var_int(iptr->dst, d);
 916                         break;
 917
 918                 case ICMD_IDIVPOW2:   /* ..., value  ==> ..., value << constant       */
 919                 case ICMD_LDIVPOW2:   /* val.i = constant                             */
 920
 921                         var_to_reg_int(s1, src, REG_ITMP1);
 922                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 923                         if (iptr->val.i <= 15) {
 924                                 M_LDA(REG_ITMP2, s1, (1 << iptr->val.i) -1);
 925                                 M_CMOVGE(s1, s1, REG_ITMP2);
 926                         } else {
 927                                 M_SRA_IMM(s1, 63, REG_ITMP2);
 928                                 M_SRL_IMM(REG_ITMP2, 64 - iptr->val.i, REG_ITMP2);
 929                                 M_LADD(s1, REG_ITMP2, REG_ITMP2);
 930                         }
 931                         M_SRA_IMM(REG_ITMP2, iptr->val.i, d);
 932                         store_reg_to_var_int(iptr->dst, d);
 933                         break;
 934
 935                 case ICMD_ISHL:       /* ..., val1, val2  ==> ..., val1 << val2       */
 936
 937                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 938                         var_to_reg_int(s2, src, REG_ITMP2);
 939                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 940                         M_AND_IMM(s2, 0x1f, REG_ITMP3);
 941                         M_SLL(s1, REG_ITMP3, d);
 942                         M_IADD(d, REG_ZERO, d);
 943                         store_reg_to_var_int(iptr->dst, d);
 944                         break;
 945
 946                 case ICMD_ISHLCONST:  /* ..., value  ==> ..., value << constant       */
 947                                       /* val.i = constant                             */
 948
 949                         var_to_reg_int(s1, src, REG_ITMP1);
 950                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 951                         M_SLL_IMM(s1, iptr->val.i & 0x1f, d);
 952                         M_IADD(d, REG_ZERO, d);
 953                         store_reg_to_var_int(iptr->dst, d);
 954                         break;
 955
 956                 case ICMD_ISHR:       /* ..., val1, val2  ==> ..., val1 >> val2       */
 957
 958                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 959                         var_to_reg_int(s2, src, REG_ITMP2);
 960                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 961                         M_AND_IMM(s2, 0x1f, REG_ITMP3);
 962                         M_SRA(s1, REG_ITMP3, d);
 963                         store_reg_to_var_int(iptr->dst, d);
 964                         break;
 965
 966                 case ICMD_ISHRCONST:  /* ..., value  ==> ..., value >> constant       */
 967                                       /* val.i = constant                             */
 968
 969                         var_to_reg_int(s1, src, REG_ITMP1);
 970                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 971                         M_SRA_IMM(s1, iptr->val.i & 0x1f, d);
 972                         store_reg_to_var_int(iptr->dst, d);
 973                         break;
 974
 975                 case ICMD_IUSHR:      /* ..., val1, val2  ==> ..., val1 >>> val2      */
 976
 977                         var_to_reg_int(s1, src->prev, REG_ITMP1);
 978                         var_to_reg_int(s2, src, REG_ITMP2);
 979                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 980                         M_AND_IMM(s2, 0x1f, REG_ITMP2);
 981             M_IZEXT(s1, d);
 982                         M_SRL(d, REG_ITMP2, d);
 983                         M_IADD(d, REG_ZERO, d);
 984                         store_reg_to_var_int(iptr->dst, d);
 985                         break;
 986
 987                 case ICMD_IUSHRCONST: /* ..., value  ==> ..., value >>> constant      */
 988                                       /* val.i = constant                             */
 989
 990                         var_to_reg_int(s1, src, REG_ITMP1);
 991                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
 992             M_IZEXT(s1, d);
 993                         M_SRL_IMM(d, iptr->val.i & 0x1f, d);
 994                         M_IADD(d, REG_ZERO, d);
 995                         store_reg_to_var_int(iptr->dst, d);
 996                         break;
 997
 998                 case ICMD_LSHL:       /* ..., val1, val2  ==> ..., val1 << val2       */
 999
1000                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1001                         var_to_reg_int(s2, src, REG_ITMP2);
1002                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1003                         M_SLL(s1, s2, d);
1004                         store_reg_to_var_int(iptr->dst, d);
1005                         break;
1006
1007                 case ICMD_LSHLCONST:  /* ..., value  ==> ..., value << constant       */
1008                                       /* val.i = constant                             */
1009
1010                         var_to_reg_int(s1, src, REG_ITMP1);
1011                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1012                         M_SLL_IMM(s1, iptr->val.i & 0x3f, d);
1013                         store_reg_to_var_int(iptr->dst, d);
1014                         break;
1015
1016                 case ICMD_LSHR:       /* ..., val1, val2  ==> ..., val1 >> val2       */
1017
1018                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1019                         var_to_reg_int(s2, src, REG_ITMP2);
1020                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1021                         M_SRA(s1, s2, d);
1022                         store_reg_to_var_int(iptr->dst, d);
1023                         break;
1024
1025                 case ICMD_LSHRCONST:  /* ..., value  ==> ..., value >> constant       */
1026                                       /* val.i = constant                             */
1027
1028                         var_to_reg_int(s1, src, REG_ITMP1);
1029                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1030                         M_SRA_IMM(s1, iptr->val.i & 0x3f, d);
1031                         store_reg_to_var_int(iptr->dst, d);
1032                         break;
1033
1034                 case ICMD_LUSHR:      /* ..., val1, val2  ==> ..., val1 >>> val2      */
1035
1036                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1037                         var_to_reg_int(s2, src, REG_ITMP2);
1038                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1039                         M_SRL(s1, s2, d);
1040                         store_reg_to_var_int(iptr->dst, d);
1041                         break;
1042
1043                 case ICMD_LUSHRCONST: /* ..., value  ==> ..., value >>> constant      */
1044                                       /* val.i = constant                             */
1045
1046                         var_to_reg_int(s1, src, REG_ITMP1);
1047                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1048                         M_SRL_IMM(s1, iptr->val.i & 0x3f, d);
1049                         store_reg_to_var_int(iptr->dst, d);
1050                         break;
1051
1052                 case ICMD_IAND:       /* ..., val1, val2  ==> ..., val1 & val2        */
1053                 case ICMD_LAND:
1054
1055                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1056                         var_to_reg_int(s2, src, REG_ITMP2);
1057                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1058                         M_AND(s1, s2, d);
1059                         store_reg_to_var_int(iptr->dst, d);
1060                         break;
1061
1062                 case ICMD_IANDCONST:  /* ..., value  ==> ..., value & constant        */
1063                                       /* val.i = constant                             */
1064
1065                         var_to_reg_int(s1, src, REG_ITMP1);
1066                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1067                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
1068                                 M_AND_IMM(s1, iptr->val.i, d);
1069                         } else if (iptr->val.i == 0xffff) {
1070                                 M_CZEXT(s1, d);
1071                         } else if (iptr->val.i == 0xffffff) {
1072                                 M_ZAPNOT_IMM(s1, 0x07, d);
1073                         } else {
1074                                 ICONST(REG_ITMP2, iptr->val.i);
1075                                 M_AND(s1, REG_ITMP2, d);
1076                         }
1077                         store_reg_to_var_int(iptr->dst, d);
1078                         break;
1079
1080                 case ICMD_IREMPOW2:   /* ..., value  ==> ..., value % constant        */
1081                                       /* val.i = constant                             */
1082
1083                         var_to_reg_int(s1, src, REG_ITMP1);
1084                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1085                         if (s1 == d) {
1086                                 M_MOV(s1, REG_ITMP1);
1087                                 s1 = REG_ITMP1;
1088                         }
1089                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
1090                                 M_AND_IMM(s1, iptr->val.i, d);
1091                                 M_BGEZ(s1, 3);
1092                                 M_ISUB(REG_ZERO, s1, d);
1093                                 M_AND_IMM(d, iptr->val.i, d);
1094                         } else if (iptr->val.i == 0xffff) {
1095                                 M_CZEXT(s1, d);
1096                                 M_BGEZ(s1, 3);
1097                                 M_ISUB(REG_ZERO, s1, d);
1098                                 M_CZEXT(d, d);
1099                         } else if (iptr->val.i == 0xffffff) {
1100                                 M_ZAPNOT_IMM(s1, 0x07, d);
1101                                 M_BGEZ(s1, 3);
1102                                 M_ISUB(REG_ZERO, s1, d);
1103                                 M_ZAPNOT_IMM(d, 0x07, d);
1104                         } else {
1105                                 ICONST(REG_ITMP2, iptr->val.i);
1106                                 M_AND(s1, REG_ITMP2, d);
1107                                 M_BGEZ(s1, 3);
1108                                 M_ISUB(REG_ZERO, s1, d);
1109                                 M_AND(d, REG_ITMP2, d);
1110                         }
1111                         M_ISUB(REG_ZERO, d, d);
1112                         store_reg_to_var_int(iptr->dst, d);
1113                         break;
1114
1115                 case ICMD_LANDCONST:  /* ..., value  ==> ..., value & constant        */
1116                                       /* val.l = constant                             */
1117
1118                         var_to_reg_int(s1, src, REG_ITMP1);
1119                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1120                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
1121                                 M_AND_IMM(s1, iptr->val.l, d);
1122                         } else if (iptr->val.l == 0xffffL) {
1123                                 M_CZEXT(s1, d);
1124                         } else if (iptr->val.l == 0xffffffL) {
1125                                 M_ZAPNOT_IMM(s1, 0x07, d);
1126                         } else if (iptr->val.l == 0xffffffffL) {
1127                                 M_IZEXT(s1, d);
1128                         } else if (iptr->val.l == 0xffffffffffL) {
1129                                 M_ZAPNOT_IMM(s1, 0x1f, d);
1130                         } else if (iptr->val.l == 0xffffffffffffL) {
1131                                 M_ZAPNOT_IMM(s1, 0x3f, d);
1132                         } else if (iptr->val.l == 0xffffffffffffffL) {
1133                                 M_ZAPNOT_IMM(s1, 0x7f, d);
1134                         } else {
1135                                 LCONST(REG_ITMP2, iptr->val.l);
1136                                 M_AND(s1, REG_ITMP2, d);
1137                         }
1138                         store_reg_to_var_int(iptr->dst, d);
1139                         break;
1140
1141                 case ICMD_LREMPOW2:   /* ..., value  ==> ..., value % constant        */
1142                                       /* val.l = constant                             */
1143
1144                         var_to_reg_int(s1, src, REG_ITMP1);
1145                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1146                         if (s1 == d) {
1147                                 M_MOV(s1, REG_ITMP1);
1148                                 s1 = REG_ITMP1;
1149                         }
1150                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
1151                                 M_AND_IMM(s1, iptr->val.l, d);
1152                                 M_BGEZ(s1, 3);
1153                                 M_LSUB(REG_ZERO, s1, d);
1154                                 M_AND_IMM(d, iptr->val.l, d);
1155                         } else if (iptr->val.l == 0xffffL) {
1156                                 M_CZEXT(s1, d);
1157                                 M_BGEZ(s1, 3);
1158                                 M_LSUB(REG_ZERO, s1, d);
1159                                 M_CZEXT(d, d);
1160                         } else if (iptr->val.l == 0xffffffL) {
1161                                 M_ZAPNOT_IMM(s1, 0x07, d);
1162                                 M_BGEZ(s1, 3);
1163                                 M_LSUB(REG_ZERO, s1, d);
1164                                 M_ZAPNOT_IMM(d, 0x07, d);
1165                         } else if (iptr->val.l == 0xffffffffL) {
1166                                 M_IZEXT(s1, d);
1167                                 M_BGEZ(s1, 3);
1168                                 M_LSUB(REG_ZERO, s1, d);
1169                                 M_IZEXT(d, d);
1170                         } else if (iptr->val.l == 0xffffffffffL) {
1171                                 M_ZAPNOT_IMM(s1, 0x1f, d);
1172                                 M_BGEZ(s1, 3);
1173                                 M_LSUB(REG_ZERO, s1, d);
1174                                 M_ZAPNOT_IMM(d, 0x1f, d);
1175                         } else if (iptr->val.l == 0xffffffffffffL) {
1176                                 M_ZAPNOT_IMM(s1, 0x3f, d);
1177                                 M_BGEZ(s1, 3);
1178                                 M_LSUB(REG_ZERO, s1, d);
1179                                 M_ZAPNOT_IMM(d, 0x3f, d);
1180                         } else if (iptr->val.l == 0xffffffffffffffL) {
1181                                 M_ZAPNOT_IMM(s1, 0x7f, d);
1182                                 M_BGEZ(s1, 3);
1183                                 M_LSUB(REG_ZERO, s1, d);
1184                                 M_ZAPNOT_IMM(d, 0x7f, d);
1185                         } else {
1186                                 LCONST(REG_ITMP2, iptr->val.l);
1187                                 M_AND(s1, REG_ITMP2, d);
1188                                 M_BGEZ(s1, 3);
1189                                 M_LSUB(REG_ZERO, s1, d);
1190                                 M_AND(d, REG_ITMP2, d);
1191                         }
1192                         M_LSUB(REG_ZERO, d, d);
1193                         store_reg_to_var_int(iptr->dst, d);
1194                         break;
1195
1196                 case ICMD_IOR:        /* ..., val1, val2  ==> ..., val1 | val2        */
1197                 case ICMD_LOR:
1198
1199                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1200                         var_to_reg_int(s2, src, REG_ITMP2);
1201                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1202                         M_OR( s1,s2, d);
1203                         store_reg_to_var_int(iptr->dst, d);
1204                         break;
1205
1206                 case ICMD_IORCONST:   /* ..., value  ==> ..., value | constant        */
1207                                       /* val.i = constant                             */
1208
1209                         var_to_reg_int(s1, src, REG_ITMP1);
1210                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1211                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
1212                                 M_OR_IMM(s1, iptr->val.i, d);
1213                         } else {
1214                                 ICONST(REG_ITMP2, iptr->val.i);
1215                                 M_OR(s1, REG_ITMP2, d);
1216                         }
1217                         store_reg_to_var_int(iptr->dst, d);
1218                         break;
1219
1220                 case ICMD_LORCONST:   /* ..., value  ==> ..., value | constant        */
1221                                       /* val.l = constant                             */
1222
1223                         var_to_reg_int(s1, src, REG_ITMP1);
1224                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1225                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
1226                                 M_OR_IMM(s1, iptr->val.l, d);
1227                         } else {
1228                                 LCONST(REG_ITMP2, iptr->val.l);
1229                                 M_OR(s1, REG_ITMP2, d);
1230                         }
1231                         store_reg_to_var_int(iptr->dst, d);
1232                         break;
1233
1234                 case ICMD_IXOR:       /* ..., val1, val2  ==> ..., val1 ^ val2        */
1235                 case ICMD_LXOR:
1236
1237                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1238                         var_to_reg_int(s2, src, REG_ITMP2);
1239                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1240                         M_XOR(s1, s2, d);
1241                         store_reg_to_var_int(iptr->dst, d);
1242                         break;
1243
1244                 case ICMD_IXORCONST:  /* ..., value  ==> ..., value ^ constant        */
1245                                       /* val.i = constant                             */
1246
1247                         var_to_reg_int(s1, src, REG_ITMP1);
1248                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1249                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
1250                                 M_XOR_IMM(s1, iptr->val.i, d);
1251                         } else {
1252                                 ICONST(REG_ITMP2, iptr->val.i);
1253                                 M_XOR(s1, REG_ITMP2, d);
1254                         }
1255                         store_reg_to_var_int(iptr->dst, d);
1256                         break;
1257
1258                 case ICMD_LXORCONST:  /* ..., value  ==> ..., value ^ constant        */
1259                                       /* val.l = constant                             */
1260
1261                         var_to_reg_int(s1, src, REG_ITMP1);
1262                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1263                         if ((iptr->val.l >= 0) && (iptr->val.l <= 255)) {
1264                                 M_XOR_IMM(s1, iptr->val.l, d);
1265                         } else {
1266                                 LCONST(REG_ITMP2, iptr->val.l);
1267                                 M_XOR(s1, REG_ITMP2, d);
1268                         }
1269                         store_reg_to_var_int(iptr->dst, d);
1270                         break;
1271
1272
1273                 case ICMD_LCMP:       /* ..., val1, val2  ==> ..., val1 cmp val2      */
1274
1275                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1276                         var_to_reg_int(s2, src, REG_ITMP2);
1277                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1278                         M_CMPLT(s1, s2, REG_ITMP3);
1279                         M_CMPLT(s2, s1, REG_ITMP1);
1280                         M_LSUB(REG_ITMP1, REG_ITMP3, d);
1281                         store_reg_to_var_int(iptr->dst, d);
1282                         break;
1283
1284
1285                 case ICMD_IINC:       /* ..., value  ==> ..., value + constant        */
1286                                       /* op1 = variable, val.i = constant             */
1287
1288                         var = &(rd->locals[iptr->op1][TYPE_INT]);
1289                         if (var->flags & INMEMORY) {
1290                                 s1 = REG_ITMP1;
1291                                 M_LLD(s1, REG_SP, var->regoff * 8);
1292                         } else
1293                                 s1 = var->regoff;
1294                         if ((iptr->val.i >= 0) && (iptr->val.i <= 255)) {
1295                                 M_IADD_IMM(s1, iptr->val.i, s1);
1296                         } else if ((iptr->val.i > -256) && (iptr->val.i < 0)) {
1297                                 M_ISUB_IMM(s1, (-iptr->val.i), s1);
1298                         } else {
1299                                 M_LDA (s1, s1, iptr->val.i);
1300                                 M_IADD(s1, REG_ZERO, s1);
1301                         }
1302                         if (var->flags & INMEMORY)
1303                                 M_LST(s1, REG_SP, var->regoff * 8);
1304                         break;
1305
1306
1307                 /* floating operations ************************************************/
1308
1309                 case ICMD_FNEG:       /* ..., value  ==> ..., - value                 */
1310
1311                         var_to_reg_flt(s1, src, REG_FTMP1);
1312                         d = reg_of_var(rd, iptr->dst, REG_FTMP2);
1313                         M_FMOVN(s1, d);
1314                         store_reg_to_var_flt(iptr->dst, d);
1315                         break;
1316
1317                 case ICMD_DNEG:       /* ..., value  ==> ..., - value                 */
1318
1319                         var_to_reg_flt(s1, src, REG_FTMP1);
1320                         d = reg_of_var(rd, iptr->dst, REG_FTMP2);
1321                         M_FMOVN(s1, d);
1322                         store_reg_to_var_flt(iptr->dst, d);
1323                         break;
1324
1325                 case ICMD_FADD:       /* ..., val1, val2  ==> ..., val1 + val2        */
1326
1327                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1328                         var_to_reg_flt(s2, src, REG_FTMP2);
1329                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1330                         if (opt_noieee) {
1331                                 M_FADD(s1, s2, d);
1332                         } else {
1333                                 if (d == s1 || d == s2) {
1334                                         M_FADDS(s1, s2, REG_FTMP3);
1335                                         M_TRAPB;
1336                                         M_FMOV(REG_FTMP3, d);
1337                                 } else {
1338                                         M_FADDS(s1, s2, d);
1339                                         M_TRAPB;
1340                                 }
1341                         }
1342                         store_reg_to_var_flt(iptr->dst, d);
1343                         break;
1344
1345                 case ICMD_DADD:       /* ..., val1, val2  ==> ..., val1 + val2        */
1346
1347                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1348                         var_to_reg_flt(s2, src, REG_FTMP2);
1349                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1350                         if (opt_noieee) {
1351                                 M_DADD(s1, s2, d);
1352                         } else {
1353                                 if (d == s1 || d == s2) {
1354                                         M_DADDS(s1, s2, REG_FTMP3);
1355                                         M_TRAPB;
1356                                         M_FMOV(REG_FTMP3, d);
1357                                 } else {
1358                                         M_DADDS(s1, s2, d);
1359                                         M_TRAPB;
1360                                 }
1361                         }
1362                         store_reg_to_var_flt(iptr->dst, d);
1363                         break;
1364
1365                 case ICMD_FSUB:       /* ..., val1, val2  ==> ..., val1 - val2        */
1366
1367                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1368                         var_to_reg_flt(s2, src, REG_FTMP2);
1369                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1370                         if (opt_noieee) {
1371                                 M_FSUB(s1, s2, d);
1372                         } else {
1373                                 if (d == s1 || d == s2) {
1374                                         M_FSUBS(s1, s2, REG_FTMP3);
1375                                         M_TRAPB;
1376                                         M_FMOV(REG_FTMP3, d);
1377                                 } else {
1378                                         M_FSUBS(s1, s2, d);
1379                                         M_TRAPB;
1380                                 }
1381                         }
1382                         store_reg_to_var_flt(iptr->dst, d);
1383                         break;
1384
1385                 case ICMD_DSUB:       /* ..., val1, val2  ==> ..., val1 - val2        */
1386
1387                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1388                         var_to_reg_flt(s2, src, REG_FTMP2);
1389                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1390                         if (opt_noieee) {
1391                                 M_DSUB(s1, s2, d);
1392                         } else {
1393                                 if (d == s1 || d == s2) {
1394                                         M_DSUBS(s1, s2, REG_FTMP3);
1395                                         M_TRAPB;
1396                                         M_FMOV(REG_FTMP3, d);
1397                                 } else {
1398                                         M_DSUBS(s1, s2, d);
1399                                         M_TRAPB;
1400                                 }
1401                         }
1402                         store_reg_to_var_flt(iptr->dst, d);
1403                         break;
1404
1405                 case ICMD_FMUL:       /* ..., val1, val2  ==> ..., val1 * val2        */
1406
1407                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1408                         var_to_reg_flt(s2, src, REG_FTMP2);
1409                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1410                         if (opt_noieee) {
1411                                 M_FMUL(s1, s2, d);
1412                         } else {
1413                                 if (d == s1 || d == s2) {
1414                                         M_FMULS(s1, s2, REG_FTMP3);
1415                                         M_TRAPB;
1416                                         M_FMOV(REG_FTMP3, d);
1417                                 } else {
1418                                         M_FMULS(s1, s2, d);
1419                                         M_TRAPB;
1420                                 }
1421                         }
1422                         store_reg_to_var_flt(iptr->dst, d);
1423                         break;
1424
1425                 case ICMD_DMUL:       /* ..., val1, val2  ==> ..., val1 *** val2      */
1426
1427                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1428                         var_to_reg_flt(s2, src, REG_FTMP2);
1429                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1430                         if (opt_noieee) {
1431                                 M_DMUL(s1, s2, d);
1432                         } else {
1433                                 if (d == s1 || d == s2) {
1434                                         M_DMULS(s1, s2, REG_FTMP3);
1435                                         M_TRAPB;
1436                                         M_FMOV(REG_FTMP3, d);
1437                                 } else {
1438                                         M_DMULS(s1, s2, d);
1439                                         M_TRAPB;
1440                                 }
1441                         }
1442                         store_reg_to_var_flt(iptr->dst, d);
1443                         break;
1444
1445                 case ICMD_FDIV:       /* ..., val1, val2  ==> ..., val1 / val2        */
1446
1447                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1448                         var_to_reg_flt(s2, src, REG_FTMP2);
1449                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1450                         if (opt_noieee) {
1451                                 M_FDIV(s1, s2, d);
1452                         } else {
1453                                 if (d == s1 || d == s2) {
1454                                         M_FDIVS(s1, s2, REG_FTMP3);
1455                                         M_TRAPB;
1456                                         M_FMOV(REG_FTMP3, d);
1457                                 } else {
1458                                         M_FDIVS(s1, s2, d);
1459                                         M_TRAPB;
1460                                 }
1461                         }
1462                         store_reg_to_var_flt(iptr->dst, d);
1463                         break;
1464
1465                 case ICMD_DDIV:       /* ..., val1, val2  ==> ..., val1 / val2        */
1466
1467                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1468                         var_to_reg_flt(s2, src, REG_FTMP2);
1469                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1470                         if (opt_noieee) {
1471                                 M_DDIV(s1, s2, d);
1472                         } else {
1473                                 if (d == s1 || d == s2) {
1474                                         M_DDIVS(s1, s2, REG_FTMP3);
1475                                         M_TRAPB;
1476                                         M_FMOV(REG_FTMP3, d);
1477                                 } else {
1478                                         M_DDIVS(s1, s2, d);
1479                                         M_TRAPB;
1480                                 }
1481                         }
1482                         store_reg_to_var_flt(iptr->dst, d);
1483                         break;
1484
1485                 case ICMD_I2F:       /* ..., value  ==> ..., (float) value            */
1486                 case ICMD_L2F:
1487                         var_to_reg_int(s1, src, REG_ITMP1);
1488                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1489                         disp = dseg_adddouble(cd, 0.0);
1490                         M_LST(s1, REG_PV, disp);
1491                         M_DLD(d, REG_PV, disp);
1492                         M_CVTLF(d, d);
1493                         store_reg_to_var_flt(iptr->dst, d);
1494                         break;
1495
1496                 case ICMD_I2D:       /* ..., value  ==> ..., (double) value           */
1497                 case ICMD_L2D:
1498                         var_to_reg_int(s1, src, REG_ITMP1);
1499                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1500                         disp = dseg_adddouble(cd, 0.0);
1501                         M_LST(s1, REG_PV, disp);
1502                         M_DLD(d, REG_PV, disp);
1503                         M_CVTLD(d, d);
1504                         store_reg_to_var_flt(iptr->dst, d);
1505                         break;
1506
1507                 case ICMD_F2I:       /* ..., value  ==> ..., (int) value              */
1508                 case ICMD_D2I:
1509                         var_to_reg_flt(s1, src, REG_FTMP1);
1510                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1511                         disp = dseg_adddouble(cd, 0.0);
1512                         M_CVTDL_C(s1, REG_FTMP2);
1513                         M_CVTLI(REG_FTMP2, REG_FTMP3);
1514                         M_DST(REG_FTMP3, REG_PV, disp);
1515                         M_ILD(d, REG_PV, disp);
1516                         store_reg_to_var_int(iptr->dst, d);
1517                         break;
1518
1519                 case ICMD_F2L:       /* ..., value  ==> ..., (long) value             */
1520                 case ICMD_D2L:
1521                         var_to_reg_flt(s1, src, REG_FTMP1);
1522                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1523                         disp = dseg_adddouble(cd, 0.0);
1524                         M_CVTDL_C(s1, REG_FTMP2);
1525                         M_DST(REG_FTMP2, REG_PV, disp);
1526                         M_LLD(d, REG_PV, disp);
1527                         store_reg_to_var_int(iptr->dst, d);
1528                         break;
1529
1530                 case ICMD_F2D:       /* ..., value  ==> ..., (double) value           */
1531
1532                         var_to_reg_flt(s1, src, REG_FTMP1);
1533                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1534                         M_CVTFDS(s1, d);
1535                         M_TRAPB;
1536                         store_reg_to_var_flt(iptr->dst, d);
1537                         break;
1538
1539                 case ICMD_D2F:       /* ..., value  ==> ..., (float) value            */
1540
1541                         var_to_reg_flt(s1, src, REG_FTMP1);
1542                         d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1543                         if (opt_noieee) {
1544                                 M_CVTDF(s1, d);
1545                         } else {
1546                                 M_CVTDFS(s1, d);
1547                                 M_TRAPB;
1548                         }
1549                         store_reg_to_var_flt(iptr->dst, d);
1550                         break;
1551
1552                 case ICMD_FCMPL:      /* ..., val1, val2  ==> ..., val1 fcmpl val2    */
1553                 case ICMD_DCMPL:
1554                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1555                         var_to_reg_flt(s2, src, REG_FTMP2);
1556                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1557                         if (opt_noieee) {
1558                                 M_LSUB_IMM(REG_ZERO, 1, d);
1559                                 M_FCMPEQ(s1, s2, REG_FTMP3);
1560                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instructions */
1561                                 M_CLR   (d);
1562                                 M_FCMPLT(s2, s1, REG_FTMP3);
1563                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instruction  */
1564                                 M_LADD_IMM(REG_ZERO, 1, d);
1565                         } else {
1566                                 M_LSUB_IMM(REG_ZERO, 1, d);
1567                                 M_FCMPEQS(s1, s2, REG_FTMP3);
1568                                 M_TRAPB;
1569                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instructions */
1570                                 M_CLR   (d);
1571                                 M_FCMPLTS(s2, s1, REG_FTMP3);
1572                                 M_TRAPB;
1573                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instruction  */
1574                                 M_LADD_IMM(REG_ZERO, 1, d);
1575                         }
1576                         store_reg_to_var_int(iptr->dst, d);
1577                         break;
1578
1579                 case ICMD_FCMPG:      /* ..., val1, val2  ==> ..., val1 fcmpg val2    */
1580                 case ICMD_DCMPG:
1581                         var_to_reg_flt(s1, src->prev, REG_FTMP1);
1582                         var_to_reg_flt(s2, src, REG_FTMP2);
1583                         d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1584                         if (opt_noieee) {
1585                                 M_LADD_IMM(REG_ZERO, 1, d);
1586                                 M_FCMPEQ(s1, s2, REG_FTMP3);
1587                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instruction  */
1588                                 M_CLR   (d);
1589                                 M_FCMPLT(s1, s2, REG_FTMP3);
1590                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instruction  */
1591                                 M_LSUB_IMM(REG_ZERO, 1, d);
1592                         } else {
1593                                 M_LADD_IMM(REG_ZERO, 1, d);
1594                                 M_FCMPEQS(s1, s2, REG_FTMP3);
1595                                 M_TRAPB;
1596                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instruction  */
1597                                 M_CLR   (d);
1598                                 M_FCMPLTS(s1, s2, REG_FTMP3);
1599                                 M_TRAPB;
1600                                 M_FBEQZ (REG_FTMP3, 1);        /* jump over next instruction  */
1601                                 M_LSUB_IMM(REG_ZERO, 1, d);
1602                         }
1603                         store_reg_to_var_int(iptr->dst, d);
1604                         break;
1605
1606
1607                 /* memory operations **************************************************/
1608
1609                 case ICMD_ARRAYLENGTH: /* ..., arrayref  ==> ..., length              */
1610
1611                         var_to_reg_int(s1, src, REG_ITMP1);
1612                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1613                         gen_nullptr_check(s1);
1614                         M_ILD(d, s1, OFFSET(java_arrayheader, size));
1615                         store_reg_to_var_int(iptr->dst, d);
1616                         break;
1617
1618                 case ICMD_BALOAD:     /* ..., arrayref, index  ==> ..., value         */
1619
1620                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1621                         var_to_reg_int(s2, src, REG_ITMP2);
1622                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1623                         if (iptr->op1 == 0) {
1624                                 gen_nullptr_check(s1);
1625                                 gen_bound_check;
1626                         }
1627                         if (has_ext_instr_set) {
1628                                 M_LADD   (s2, s1, REG_ITMP1);
1629                                 M_BLDU   (d, REG_ITMP1, OFFSET (java_bytearray, data[0]));
1630                                 M_BSEXT  (d, d);
1631                         } else {
1632                                 M_LADD(s2, s1, REG_ITMP1);
1633                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_bytearray, data[0]));
1634                                 M_LDA(REG_ITMP1, REG_ITMP1, OFFSET(java_bytearray, data[0])+1);
1635                                 M_EXTQH(REG_ITMP2, REG_ITMP1, d);
1636                                 M_SRA_IMM(d, 56, d);
1637                         }
1638                         store_reg_to_var_int(iptr->dst, d);
1639                         break;
1640
1641                 case ICMD_CALOAD:     /* ..., arrayref, index  ==> ..., value         */
1642
1643                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1644                         var_to_reg_int(s2, src, REG_ITMP2);
1645                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1646                         if (iptr->op1 == 0) {
1647                                 gen_nullptr_check(s1);
1648                                 gen_bound_check;
1649                         }
1650                         if (has_ext_instr_set) {
1651                                 M_LADD(s2, s1, REG_ITMP1);
1652                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1653                                 M_SLDU(d, REG_ITMP1, OFFSET(java_chararray, data[0]));
1654                         } else {
1655                                 M_LADD (s2, s1, REG_ITMP1);
1656                                 M_LADD (s2, REG_ITMP1, REG_ITMP1);
1657                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_chararray, data[0]));
1658                                 M_LDA  (REG_ITMP1, REG_ITMP1, OFFSET(java_chararray, data[0]));
1659                                 M_EXTWL(REG_ITMP2, REG_ITMP1, d);
1660                         }
1661                         store_reg_to_var_int(iptr->dst, d);
1662                         break;
1663
1664                 case ICMD_SALOAD:     /* ..., arrayref, index  ==> ..., value         */
1665
1666                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1667                         var_to_reg_int(s2, src, REG_ITMP2);
1668                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1669                         if (iptr->op1 == 0) {
1670                                 gen_nullptr_check(s1);
1671                                 gen_bound_check;
1672                         }
1673                         if (has_ext_instr_set) {
1674                                 M_LADD(s2, s1, REG_ITMP1);
1675                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1676                                 M_SLDU( d, REG_ITMP1, OFFSET (java_shortarray, data[0]));
1677                                 M_SSEXT(d, d);
1678                         } else {
1679                                 M_LADD(s2, s1, REG_ITMP1);
1680                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1681                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_shortarray, data[0]));
1682                                 M_LDA(REG_ITMP1, REG_ITMP1, OFFSET(java_shortarray, data[0])+2);
1683                                 M_EXTQH(REG_ITMP2, REG_ITMP1, d);
1684                                 M_SRA_IMM(d, 48, d);
1685                         }
1686                         store_reg_to_var_int(iptr->dst, d);
1687                         break;
1688
1689                 case ICMD_IALOAD:     /* ..., arrayref, index  ==> ..., value         */
1690
1691                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1692                         var_to_reg_int(s2, src, REG_ITMP2);
1693                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1694                         if (iptr->op1 == 0) {
1695                                 gen_nullptr_check(s1);
1696                                 gen_bound_check;
1697                         }
1698                         M_S4ADDQ(s2, s1, REG_ITMP1);
1699                         M_ILD(d, REG_ITMP1, OFFSET(java_intarray, data[0]));
1700                         store_reg_to_var_int(iptr->dst, d);
1701                         break;
1702
1703                 case ICMD_LALOAD:     /* ..., arrayref, index  ==> ..., value         */
1704
1705                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1706                         var_to_reg_int(s2, src, REG_ITMP2);
1707                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1708                         if (iptr->op1 == 0) {
1709                                 gen_nullptr_check(s1);
1710                                 gen_bound_check;
1711                         }
1712                         M_S8ADDQ(s2, s1, REG_ITMP1);
1713                         M_LLD(d, REG_ITMP1, OFFSET(java_longarray, data[0]));
1714                         store_reg_to_var_int(iptr->dst, d);
1715                         break;
1716
1717                 case ICMD_FALOAD:     /* ..., arrayref, index  ==> ..., value         */
1718
1719                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1720                         var_to_reg_int(s2, src, REG_ITMP2);
1721                         d = reg_of_var(rd, iptr->dst, REG_FTMP2);
1722                         if (iptr->op1 == 0) {
1723                                 gen_nullptr_check(s1);
1724                                 gen_bound_check;
1725                         }
1726                         M_S4ADDQ(s2, s1, REG_ITMP1);
1727                         M_FLD(d, REG_ITMP1, OFFSET(java_floatarray, data[0]));
1728                         store_reg_to_var_flt(iptr->dst, d);
1729                         break;
1730
1731                 case ICMD_DALOAD:     /* ..., arrayref, index  ==> ..., value         */
1732
1733                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1734                         var_to_reg_int(s2, src, REG_ITMP2);
1735                         d = reg_of_var(rd, iptr->dst, REG_FTMP2);
1736                         if (iptr->op1 == 0) {
1737                                 gen_nullptr_check(s1);
1738                                 gen_bound_check;
1739                         }
1740                         M_S8ADDQ(s2, s1, REG_ITMP1);
1741                         M_DLD(d, REG_ITMP1, OFFSET(java_doublearray, data[0]));
1742                         store_reg_to_var_flt(iptr->dst, d);
1743                         break;
1744
1745                 case ICMD_AALOAD:     /* ..., arrayref, index  ==> ..., value         */
1746
1747                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1748                         var_to_reg_int(s2, src, REG_ITMP2);
1749                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1750                         if (iptr->op1 == 0) {
1751                                 gen_nullptr_check(s1);
1752                                 gen_bound_check;
1753                         }
1754                         M_SAADDQ(s2, s1, REG_ITMP1);
1755                         M_ALD(d, REG_ITMP1, OFFSET(java_objectarray, data[0]));
1756                         store_reg_to_var_int(iptr->dst, d);
1757                         break;
1758
1759
1760                 case ICMD_BASTORE:    /* ..., arrayref, index, value  ==> ...         */
1761
1762                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1763                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1764                         if (iptr->op1 == 0) {
1765                                 gen_nullptr_check(s1);
1766                                 gen_bound_check;
1767                         }
1768                         var_to_reg_int(s3, src, REG_ITMP3);
1769                         if (has_ext_instr_set) {
1770                                 M_LADD(s2, s1, REG_ITMP1);
1771                                 M_BST(s3, REG_ITMP1, OFFSET(java_bytearray, data[0]));
1772                         } else {
1773                                 M_LADD(s2, s1, REG_ITMP1);
1774                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_bytearray, data[0]));
1775                                 M_LDA(REG_ITMP1, REG_ITMP1, OFFSET(java_bytearray, data[0]));
1776                                 M_INSBL(s3, REG_ITMP1, REG_ITMP3);
1777                                 M_MSKBL(REG_ITMP2, REG_ITMP1, REG_ITMP2);
1778                                 M_OR(REG_ITMP2, REG_ITMP3, REG_ITMP2);
1779                                 M_LST_U(REG_ITMP2, REG_ITMP1, 0);
1780                         }
1781                         break;
1782
1783                 case ICMD_CASTORE:    /* ..., arrayref, index, value  ==> ...         */
1784
1785                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1786                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1787                         if (iptr->op1 == 0) {
1788                                 gen_nullptr_check(s1);
1789                                 gen_bound_check;
1790                         }
1791                         var_to_reg_int(s3, src, REG_ITMP3);
1792                         if (has_ext_instr_set) {
1793                                 M_LADD(s2, s1, REG_ITMP1);
1794                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1795                                 M_SST(s3, REG_ITMP1, OFFSET(java_chararray, data[0]));
1796                         } else {
1797                                 M_LADD(s2, s1, REG_ITMP1);
1798                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1799                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_chararray, data[0]));
1800                                 M_LDA(REG_ITMP1, REG_ITMP1, OFFSET(java_chararray, data[0]));
1801                                 M_INSWL(s3, REG_ITMP1, REG_ITMP3);
1802                                 M_MSKWL(REG_ITMP2, REG_ITMP1, REG_ITMP2);
1803                                 M_OR(REG_ITMP2, REG_ITMP3, REG_ITMP2);
1804                                 M_LST_U(REG_ITMP2, REG_ITMP1, 0);
1805                         }
1806                         break;
1807
1808                 case ICMD_SASTORE:    /* ..., arrayref, index, value  ==> ...         */
1809
1810                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1811                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1812                         if (iptr->op1 == 0) {
1813                                 gen_nullptr_check(s1);
1814                                 gen_bound_check;
1815                         }
1816                         var_to_reg_int(s3, src, REG_ITMP3);
1817                         if (has_ext_instr_set) {
1818                                 M_LADD(s2, s1, REG_ITMP1);
1819                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1820                                 M_SST(s3, REG_ITMP1, OFFSET(java_shortarray, data[0]));
1821                         } else {
1822                                 M_LADD(s2, s1, REG_ITMP1);
1823                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1824                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_shortarray, data[0]));
1825                                 M_LDA(REG_ITMP1, REG_ITMP1, OFFSET(java_shortarray, data[0]));
1826                                 M_INSWL(s3, REG_ITMP1, REG_ITMP3);
1827                                 M_MSKWL(REG_ITMP2, REG_ITMP1, REG_ITMP2);
1828                                 M_OR(REG_ITMP2, REG_ITMP3, REG_ITMP2);
1829                                 M_LST_U(REG_ITMP2, REG_ITMP1, 0);
1830                         }
1831                         break;
1832
1833                 case ICMD_IASTORE:    /* ..., arrayref, index, value  ==> ...         */
1834
1835                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1836                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1837                         if (iptr->op1 == 0) {
1838                                 gen_nullptr_check(s1);
1839                                 gen_bound_check;
1840                         }
1841                         var_to_reg_int(s3, src, REG_ITMP3);
1842                         M_S4ADDQ(s2, s1, REG_ITMP1);
1843                         M_IST(s3, REG_ITMP1, OFFSET(java_intarray, data[0]));
1844                         break;
1845
1846                 case ICMD_LASTORE:    /* ..., arrayref, index, value  ==> ...         */
1847
1848                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1849                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1850                         if (iptr->op1 == 0) {
1851                                 gen_nullptr_check(s1);
1852                                 gen_bound_check;
1853                         }
1854                         var_to_reg_int(s3, src, REG_ITMP3);
1855                         M_S8ADDQ(s2, s1, REG_ITMP1);
1856                         M_LST(s3, REG_ITMP1, OFFSET(java_longarray, data[0]));
1857                         break;
1858
1859                 case ICMD_FASTORE:    /* ..., arrayref, index, value  ==> ...         */
1860
1861                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1862                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1863                         if (iptr->op1 == 0) {
1864                                 gen_nullptr_check(s1);
1865                                 gen_bound_check;
1866                         }
1867                         var_to_reg_flt(s3, src, REG_FTMP3);
1868                         M_S4ADDQ(s2, s1, REG_ITMP1);
1869                         M_FST(s3, REG_ITMP1, OFFSET(java_floatarray, data[0]));
1870                         break;
1871
1872                 case ICMD_DASTORE:    /* ..., arrayref, index, value  ==> ...         */
1873
1874                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1875                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1876                         if (iptr->op1 == 0) {
1877                                 gen_nullptr_check(s1);
1878                                 gen_bound_check;
1879                         }
1880                         var_to_reg_flt(s3, src, REG_FTMP3);
1881                         M_S8ADDQ(s2, s1, REG_ITMP1);
1882                         M_DST(s3, REG_ITMP1, OFFSET(java_doublearray, data[0]));
1883                         break;
1884
1885                 case ICMD_AASTORE:    /* ..., arrayref, index, value  ==> ...         */
1886
1887                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1888                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1889                         if (iptr->op1 == 0) {
1890                                 gen_nullptr_check(s1);
1891                                 gen_bound_check;
1892                         }
1893                         var_to_reg_int(s3, src, REG_ITMP3);
1894
1895                         M_MOV(s1, rd->argintregs[0]);
1896                         M_MOV(s3, rd->argintregs[1]);
1897                         disp = dseg_addaddress(cd, BUILTIN_canstore);
1898                         M_ALD(REG_PV, REG_PV, disp);
1899                         M_JSR(REG_RA, REG_PV);
1900                         disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
1901                         M_LDA(REG_PV, REG_RA, -disp);
1902
1903                         M_BEQZ(REG_RESULT, 0);
1904                         codegen_add_arraystoreexception_ref(cd, mcodeptr);
1905
1906                         var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1907                         var_to_reg_int(s2, src->prev, REG_ITMP2);
1908                         var_to_reg_int(s3, src, REG_ITMP3);
1909                         M_SAADDQ(s2, s1, REG_ITMP1);
1910                         M_AST(s3, REG_ITMP1, OFFSET(java_objectarray, data[0]));
1911                         break;
1912
1913
1914                 case ICMD_IASTORECONST:   /* ..., arrayref, index  ==> ...            */
1915
1916                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1917                         var_to_reg_int(s2, src, REG_ITMP2);
1918                         if (iptr->op1 == 0) {
1919                                 gen_nullptr_check(s1);
1920                                 gen_bound_check;
1921                         }
1922                         M_S4ADDQ(s2, s1, REG_ITMP1);
1923                         M_IST(REG_ZERO, REG_ITMP1, OFFSET(java_intarray, data[0]));
1924                         break;
1925
1926                 case ICMD_LASTORECONST:   /* ..., arrayref, index  ==> ...            */
1927
1928                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1929                         var_to_reg_int(s2, src, REG_ITMP2);
1930                         if (iptr->op1 == 0) {
1931                                 gen_nullptr_check(s1);
1932                                 gen_bound_check;
1933                         }
1934                         M_S8ADDQ(s2, s1, REG_ITMP1);
1935                         M_LST(REG_ZERO, REG_ITMP1, OFFSET(java_longarray, data[0]));
1936                         break;
1937
1938                 case ICMD_AASTORECONST:   /* ..., arrayref, index  ==> ...            */
1939
1940                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1941                         var_to_reg_int(s2, src, REG_ITMP2);
1942                         if (iptr->op1 == 0) {
1943                                 gen_nullptr_check(s1);
1944                                 gen_bound_check;
1945                         }
1946                         M_SAADDQ(s2, s1, REG_ITMP1);
1947                         M_AST(REG_ZERO, REG_ITMP1, OFFSET(java_objectarray, data[0]));
1948                         break;
1949
1950                 case ICMD_BASTORECONST:   /* ..., arrayref, index  ==> ...            */
1951
1952                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1953                         var_to_reg_int(s2, src, REG_ITMP2);
1954                         if (iptr->op1 == 0) {
1955                                 gen_nullptr_check(s1);
1956                                 gen_bound_check;
1957                         }
1958                         if (has_ext_instr_set) {
1959                                 M_LADD(s2, s1, REG_ITMP1);
1960                                 M_BST(REG_ZERO, REG_ITMP1, OFFSET(java_bytearray, data[0]));
1961
1962                         } else {
1963                                 M_LADD(s2, s1, REG_ITMP1);
1964                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_bytearray, data[0]));
1965                                 M_LDA(REG_ITMP1, REG_ITMP1, OFFSET(java_bytearray, data[0]));
1966                                 M_INSBL(REG_ZERO, REG_ITMP1, REG_ITMP3);
1967                                 M_MSKBL(REG_ITMP2, REG_ITMP1, REG_ITMP2);
1968                                 M_OR(REG_ITMP2, REG_ITMP3, REG_ITMP2);
1969                                 M_LST_U(REG_ITMP2, REG_ITMP1, 0);
1970                         }
1971                         break;
1972
1973                 case ICMD_CASTORECONST:   /* ..., arrayref, index  ==> ...            */
1974
1975                         var_to_reg_int(s1, src->prev, REG_ITMP1);
1976                         var_to_reg_int(s2, src, REG_ITMP2);
1977                         if (iptr->op1 == 0) {
1978                                 gen_nullptr_check(s1);
1979                                 gen_bound_check;
1980                         }
1981                         if (has_ext_instr_set) {
1982                                 M_LADD(s2, s1, REG_ITMP1);
1983                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1984                                 M_SST(REG_ZERO, REG_ITMP1, OFFSET(java_chararray, data[0]));
1985
1986                         } else {
1987                                 M_LADD(s2, s1, REG_ITMP1);
1988                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
1989                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_chararray, data[0]));
1990                                 M_LDA(REG_ITMP1, REG_ITMP1, OFFSET(java_chararray, data[0]));
1991                                 M_INSWL(REG_ZERO, REG_ITMP1, REG_ITMP3);
1992                                 M_MSKWL(REG_ITMP2, REG_ITMP1, REG_ITMP2);
1993                                 M_OR(REG_ITMP2, REG_ITMP3, REG_ITMP2);
1994                                 M_LST_U(REG_ITMP2, REG_ITMP1, 0);
1995                         }
1996                         break;
1997
1998                 case ICMD_SASTORECONST:   /* ..., arrayref, index  ==> ...            */
1999
2000                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2001                         var_to_reg_int(s2, src, REG_ITMP2);
2002                         if (iptr->op1 == 0) {
2003                                 gen_nullptr_check(s1);
2004                                 gen_bound_check;
2005                         }
2006                         if (has_ext_instr_set) {
2007                                 M_LADD(s2, s1, REG_ITMP1);
2008                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
2009                                 M_SST(REG_ZERO, REG_ITMP1, OFFSET(java_shortarray, data[0]));
2010
2011                         } else {
2012                                 M_LADD(s2, s1, REG_ITMP1);
2013                                 M_LADD(s2, REG_ITMP1, REG_ITMP1);
2014                                 M_LLD_U(REG_ITMP2, REG_ITMP1, OFFSET(java_shortarray, data[0]));
2015                                 M_LDA(REG_ITMP1, REG_ITMP1, OFFSET(java_shortarray, data[0]));
2016                                 M_INSWL(REG_ZERO, REG_ITMP1, REG_ITMP3);
2017                                 M_MSKWL(REG_ITMP2, REG_ITMP1, REG_ITMP2);
2018                                 M_OR(REG_ITMP2, REG_ITMP3, REG_ITMP2);
2019                                 M_LST_U(REG_ITMP2, REG_ITMP1, 0);
2020                         }
2021                         break;
2022
2023
2024                 case ICMD_GETSTATIC:  /* ...  ==> ..., value                          */
2025                                       /* op1 = type, val.a = field address            */
2026
2027                         if (iptr->val.a == NULL) {
2028                                 disp = dseg_addaddress(cd, 0);
2029
2030                                 codegen_addpatchref(cd, mcodeptr,
2031                                                                         PATCHER_get_putstatic,
2032                                                                         (unresolved_field *) iptr->target, disp);
2033
2034                                 if (opt_showdisassemble)
2035                                         M_NOP;
2036
2037
2038                         } else {
2039                                 fieldinfo *fi = iptr->val.a;
2040
2041                                 disp = dseg_addaddress(cd, &(fi->value));
2042
2043                                 if (!CLASS_IS_OR_ALMOST_INITIALIZED(fi->class)) {
2044                                         codegen_addpatchref(cd, mcodeptr,
2045                                                                                 PATCHER_clinit, fi->class, 0);
2046
2047                                         if (opt_showdisassemble)
2048                                                 M_NOP;
2049                                 }
2050                         }
2051
2052                         M_ALD(REG_ITMP1, REG_PV, disp);
2053                         switch (iptr->op1) {
2054                         case TYPE_INT:
2055                                 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
2056                                 M_ILD(d, REG_ITMP1, 0);
2057                                 store_reg_to_var_int(iptr->dst, d);
2058                                 break;
2059                         case TYPE_LNG:
2060                                 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
2061                                 M_LLD(d, REG_ITMP1, 0);
2062                                 store_reg_to_var_int(iptr->dst, d);
2063                                 break;
2064                         case TYPE_ADR:
2065                                 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
2066                                 M_ALD(d, REG_ITMP1, 0);
2067                                 store_reg_to_var_int(iptr->dst, d);
2068                                 break;
2069                         case TYPE_FLT:
2070                                 d = reg_of_var(rd, iptr->dst, REG_FTMP1);
2071                                 M_FLD(d, REG_ITMP1, 0);
2072                                 store_reg_to_var_flt(iptr->dst, d);
2073                                 break;
2074                         case TYPE_DBL:
2075                                 d = reg_of_var(rd, iptr->dst, REG_FTMP1);
2076                                 M_DLD(d, REG_ITMP1, 0);
2077                                 store_reg_to_var_flt(iptr->dst, d);
2078                                 break;
2079                         }
2080                         break;
2081
2082                 case ICMD_PUTSTATIC:  /* ..., value  ==> ...                          */
2083                                       /* op1 = type, val.a = field address            */
2084
2085                         if (iptr->val.a == NULL) {
2086                                 disp = dseg_addaddress(cd, 0);
2087
2088                                 codegen_addpatchref(cd, mcodeptr,
2089                                                                         PATCHER_get_putstatic,
2090                                                                         (unresolved_field *) iptr->target, disp);
2091
2092                                 if (opt_showdisassemble)
2093                                         M_NOP;
2094
2095                         } else {
2096                                 fieldinfo *fi = iptr->val.a;
2097
2098                                 disp = dseg_addaddress(cd, &(fi->value));
2099
2100                                 if (!CLASS_IS_OR_ALMOST_INITIALIZED(fi->class)) {
2101                                         codegen_addpatchref(cd, mcodeptr,
2102                                                                                 PATCHER_clinit, fi->class, 0);
2103
2104                                         if (opt_showdisassemble)
2105                                                 M_NOP;
2106                                 }
2107                         }
2108
2109                         M_ALD(REG_ITMP1, REG_PV, disp);
2110                         switch (iptr->op1) {
2111                         case TYPE_INT:
2112                                 var_to_reg_int(s2, src, REG_ITMP2);
2113                                 M_IST(s2, REG_ITMP1, 0);
2114                                 break;
2115                         case TYPE_LNG:
2116                                 var_to_reg_int(s2, src, REG_ITMP2);
2117                                 M_LST(s2, REG_ITMP1, 0);
2118                                 break;
2119                         case TYPE_ADR:
2120                                 var_to_reg_int(s2, src, REG_ITMP2);
2121                                 M_AST(s2, REG_ITMP1, 0);
2122                                 break;
2123                         case TYPE_FLT:
2124                                 var_to_reg_flt(s2, src, REG_FTMP2);
2125                                 M_FST(s2, REG_ITMP1, 0);
2126                                 break;
2127                         case TYPE_DBL:
2128                                 var_to_reg_flt(s2, src, REG_FTMP2);
2129                                 M_DST(s2, REG_ITMP1, 0);
2130                                 break;
2131                         }
2132                         break;
2133
2134                 case ICMD_PUTSTATICCONST: /* ...  ==> ...                             */
2135                                           /* val = value (in current instruction)     */
2136                                           /* op1 = type, val.a = field address (in    */
2137                                           /* following NOP)                           */
2138
2139                         if (iptr[1].val.a == NULL) {
2140                                 disp = dseg_addaddress(cd, 0);
2141
2142                                 codegen_addpatchref(cd, mcodeptr,
2143                                                                         PATCHER_get_putstatic,
2144                                                                         (unresolved_field *) iptr[1].target, disp);
2145
2146                                 if (opt_showdisassemble)
2147                                         M_NOP;
2148
2149                         } else {
2150                                 fieldinfo *fi = iptr[1].val.a;
2151
2152                                 disp = dseg_addaddress(cd, &(fi->value));
2153
2154                                 if (!CLASS_IS_OR_ALMOST_INITIALIZED(fi->class)) {
2155                                         codegen_addpatchref(cd, mcodeptr,
2156                                                                                 PATCHER_clinit, fi->class, 0);
2157
2158                                         if (opt_showdisassemble)
2159                                                 M_NOP;
2160                                 }
2161                         }
2162
2163                         M_ALD(REG_ITMP1, REG_PV, disp);
2164                         switch (iptr->op1) {
2165                         case TYPE_INT:
2166                                 M_IST(REG_ZERO, REG_ITMP1, 0);
2167                                 break;
2168                         case TYPE_LNG:
2169                                 M_LST(REG_ZERO, REG_ITMP1, 0);
2170                                 break;
2171                         case TYPE_ADR:
2172                                 M_AST(REG_ZERO, REG_ITMP1, 0);
2173                                 break;
2174                         case TYPE_FLT:
2175                                 M_FST(REG_ZERO, REG_ITMP1, 0);
2176                                 break;
2177                         case TYPE_DBL:
2178                                 M_DST(REG_ZERO, REG_ITMP1, 0);
2179                                 break;
2180                         }
2181                         break;
2182
2183
2184                 case ICMD_GETFIELD:   /* ...  ==> ..., value                          */
2185                                       /* op1 = type, val.i = field offset             */
2186
2187                         var_to_reg_int(s1, src, REG_ITMP1);
2188                         gen_nullptr_check(s1);
2189
2190                         if (iptr->val.a == NULL) {
2191                                 codegen_addpatchref(cd, mcodeptr,
2192                                                                         PATCHER_get_putfield,
2193                                                                         (unresolved_field *) iptr->target, 0);
2194
2195                                 if (opt_showdisassemble)
2196                                         M_NOP;
2197
2198                                 disp = 0;
2199
2200                         } else {
2201                                 disp = ((fieldinfo *) (iptr->val.a))->offset;
2202                         }
2203
2204                         switch (iptr->op1) {
2205                         case TYPE_INT:
2206                                 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
2207                                 M_ILD(d, s1, disp);
2208                                 store_reg_to_var_int(iptr->dst, d);
2209                                 break;
2210                         case TYPE_LNG:
2211                                 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
2212                                 M_LLD(d, s1, disp);
2213                                 store_reg_to_var_int(iptr->dst, d);
2214                                 break;
2215                         case TYPE_ADR:
2216                                 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
2217                                 M_ALD(d, s1, disp);
2218                                 store_reg_to_var_int(iptr->dst, d);
2219                                 break;
2220                         case TYPE_FLT:
2221                                 d = reg_of_var(rd, iptr->dst, REG_FTMP1);
2222                                 M_FLD(d, s1, disp);
2223                                 store_reg_to_var_flt(iptr->dst, d);
2224                                 break;
2225                         case TYPE_DBL:
2226                                 d = reg_of_var(rd, iptr->dst, REG_FTMP1);
2227                                 M_DLD(d, s1, disp);
2228                                 store_reg_to_var_flt(iptr->dst, d);
2229                                 break;
2230                         }
2231                         break;
2232
2233                 case ICMD_PUTFIELD:   /* ..., objectref, value  ==> ...               */
2234                                       /* op1 = type, val.a = field address            */
2235
2236                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2237                         gen_nullptr_check(s1);
2238
2239                         if (!IS_FLT_DBL_TYPE(iptr->op1)) {
2240                                 var_to_reg_int(s2, src, REG_ITMP2);
2241                         } else {
2242                                 var_to_reg_flt(s2, src, REG_FTMP2);
2243                         }
2244
2245                         if (iptr->val.a == NULL) {
2246                                 codegen_addpatchref(cd, mcodeptr,
2247                                                                         PATCHER_get_putfield,
2248                                                                         (unresolved_field *) iptr->target, 0);
2249
2250                                 if (opt_showdisassemble)
2251                                         M_NOP;
2252
2253                                 disp = 0;
2254
2255                         } else {
2256                                 disp = ((fieldinfo *) (iptr->val.a))->offset;
2257                         }
2258
2259                         switch (iptr->op1) {
2260                         case TYPE_INT:
2261                                 M_IST(s2, s1, disp);
2262                                 break;
2263                         case TYPE_LNG:
2264                                 M_LST(s2, s1, disp);
2265                                 break;
2266                         case TYPE_ADR:
2267                                 M_AST(s2, s1, disp);
2268                                 break;
2269                         case TYPE_FLT:
2270                                 M_FST(s2, s1, disp);
2271                                 break;
2272                         case TYPE_DBL:
2273                                 M_DST(s2, s1, disp);
2274                                 break;
2275                         }
2276                         break;
2277
2278                 case ICMD_PUTFIELDCONST:  /* ..., objectref  ==> ...                  */
2279                                           /* val = value (in current instruction)     */
2280                                           /* op1 = type, val.a = field address (in    */
2281                                           /* following NOP)                           */
2282
2283                         var_to_reg_int(s1, src, REG_ITMP1);
2284                         gen_nullptr_check(s1);
2285
2286                         if (iptr[1].val.a == NULL) {
2287                                 codegen_addpatchref(cd, mcodeptr,
2288                                                                         PATCHER_get_putfield,
2289                                                                         (unresolved_field *) iptr[1].target, 0);
2290
2291                                 if (opt_showdisassemble)
2292                                         M_NOP;
2293
2294                                 disp = 0;
2295
2296                         } else {
2297                                 disp = ((fieldinfo *) (iptr[1].val.a))->offset;
2298                         }
2299
2300                         switch (iptr[1].op1) {
2301                         case TYPE_INT:
2302                                 M_IST(REG_ZERO, s1, disp);
2303                                 break;
2304                         case TYPE_LNG:
2305                                 M_LST(REG_ZERO, s1, disp);
2306                                 break;
2307                         case TYPE_ADR:
2308                                 M_AST(REG_ZERO, s1, disp);
2309                                 break;
2310                         case TYPE_FLT:
2311                                 M_FST(REG_ZERO, s1, disp);
2312                                 break;
2313                         case TYPE_DBL:
2314                                 M_DST(REG_ZERO, s1, disp);
2315                                 break;
2316                         }
2317                         break;
2318
2319
2320                 /* branch operations **************************************************/
2321
2322                 case ICMD_ATHROW:       /* ..., objectref ==> ... (, objectref)       */
2323
2324                         var_to_reg_int(s1, src, REG_ITMP1);
2325                         M_INTMOVE(s1, REG_ITMP1_XPTR);
2326
2327 #ifdef ENABLE_VERIFIER
2328                         if (iptr->val.a) {
2329                                 codegen_addpatchref(cd, mcodeptr,
2330                                                                         PATCHER_athrow_areturn,
2331                                                                         (unresolved_class *) iptr->val.a, 0);
2332
2333                                 if (opt_showdisassemble)
2334                                         M_NOP;
2335                         }
2336 #endif /* ENABLE_VERIFIER */
2337
2338                         disp = dseg_addaddress(cd, asm_handle_exception);
2339                         M_ALD(REG_ITMP2, REG_PV, disp);
2340                         M_JMP(REG_ITMP2_XPC, REG_ITMP2);
2341                         M_NOP;              /* nop ensures that XPC is less than the end */
2342                                             /* of basic block                            */
2343                         ALIGNCODENOP;
2344                         break;
2345
2346                 case ICMD_GOTO:         /* ... ==> ...                                */
2347                                         /* op1 = target JavaVM pc                     */
2348                         M_BR(0);
2349                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2350                         ALIGNCODENOP;
2351                         break;
2352
2353                 case ICMD_JSR:          /* ... ==> ...                                */
2354                                         /* op1 = target JavaVM pc                     */
2355
2356                         M_BSR(REG_ITMP1, 0);
2357                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2358                         break;
2359
2360                 case ICMD_RET:          /* ... ==> ...                                */
2361                                         /* op1 = local variable                       */
2362
2363                         var = &(rd->locals[iptr->op1][TYPE_ADR]);
2364                         if (var->flags & INMEMORY) {
2365                                 M_ALD(REG_ITMP1, REG_SP, 8 * var->regoff);
2366                                 M_RET(REG_ZERO, REG_ITMP1);
2367                                 }
2368                         else
2369                                 M_RET(REG_ZERO, var->regoff);
2370                         ALIGNCODENOP;
2371                         break;
2372
2373                 case ICMD_IFNULL:       /* ..., value ==> ...                         */
2374                                         /* op1 = target JavaVM pc                     */
2375
2376                         var_to_reg_int(s1, src, REG_ITMP1);
2377                         M_BEQZ(s1, 0);
2378                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2379                         break;
2380
2381                 case ICMD_IFNONNULL:    /* ..., value ==> ...                         */
2382                                         /* op1 = target JavaVM pc                     */
2383
2384                         var_to_reg_int(s1, src, REG_ITMP1);
2385                         M_BNEZ(s1, 0);
2386                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2387                         break;
2388
2389                 case ICMD_IFEQ:         /* ..., value ==> ...                         */
2390                                         /* op1 = target JavaVM pc, val.i = constant   */
2391
2392                         var_to_reg_int(s1, src, REG_ITMP1);
2393                         if (iptr->val.i == 0) {
2394                                 M_BEQZ(s1, 0);
2395                                 }
2396                         else {
2397                                 if ((iptr->val.i > 0) && (iptr->val.i <= 255)) {
2398                                         M_CMPEQ_IMM(s1, iptr->val.i, REG_ITMP1);
2399                                         }
2400                                 else {
2401                                         ICONST(REG_ITMP2, iptr->val.i);
2402                                         M_CMPEQ(s1, REG_ITMP2, REG_ITMP1);
2403                                         }
2404                                 M_BNEZ(REG_ITMP1, 0);
2405                                 }
2406                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2407                         break;
2408
2409                 case ICMD_IFLT:         /* ..., value ==> ...                         */
2410                                         /* op1 = target JavaVM pc, val.i = constant   */
2411
2412                         var_to_reg_int(s1, src, REG_ITMP1);
2413                         if (iptr->val.i == 0) {
2414                                 M_BLTZ(s1, 0);
2415                                 }
2416                         else {
2417                                 if ((iptr->val.i > 0) && (iptr->val.i <= 255)) {
2418                                         M_CMPLT_IMM(s1, iptr->val.i, REG_ITMP1);
2419                                         }
2420                                 else {
2421                                         ICONST(REG_ITMP2, iptr->val.i);
2422                                         M_CMPLT(s1, REG_ITMP2, REG_ITMP1);
2423                                         }
2424                                 M_BNEZ(REG_ITMP1, 0);
2425                                 }
2426                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2427                         break;
2428
2429                 case ICMD_IFLE:         /* ..., value ==> ...                         */
2430                                         /* op1 = target JavaVM pc, val.i = constant   */
2431
2432                         var_to_reg_int(s1, src, REG_ITMP1);
2433                         if (iptr->val.i == 0) {
2434                                 M_BLEZ(s1, 0);
2435                                 }
2436                         else {
2437                                 if ((iptr->val.i > 0) && (iptr->val.i <= 255)) {
2438                                         M_CMPLE_IMM(s1, iptr->val.i, REG_ITMP1);
2439                                         }
2440                                 else {
2441                                         ICONST(REG_ITMP2, iptr->val.i);
2442                                         M_CMPLE(s1, REG_ITMP2, REG_ITMP1);
2443                                         }
2444                                 M_BNEZ(REG_ITMP1, 0);
2445                                 }
2446                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2447                         break;
2448
2449                 case ICMD_IFNE:         /* ..., value ==> ...                         */
2450                                         /* op1 = target JavaVM pc, val.i = constant   */
2451
2452                         var_to_reg_int(s1, src, REG_ITMP1);
2453                         if (iptr->val.i == 0) {
2454                                 M_BNEZ(s1, 0);
2455                                 }
2456                         else {
2457                                 if ((iptr->val.i > 0) && (iptr->val.i <= 255)) {
2458                                         M_CMPEQ_IMM(s1, iptr->val.i, REG_ITMP1);
2459                                         }
2460                                 else {
2461                                         ICONST(REG_ITMP2, iptr->val.i);
2462                                         M_CMPEQ(s1, REG_ITMP2, REG_ITMP1);
2463                                         }
2464                                 M_BEQZ(REG_ITMP1, 0);
2465                                 }
2466                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2467                         break;
2468
2469                 case ICMD_IFGT:         /* ..., value ==> ...                         */
2470                                         /* op1 = target JavaVM pc, val.i = constant   */
2471
2472                         var_to_reg_int(s1, src, REG_ITMP1);
2473                         if (iptr->val.i == 0) {
2474                                 M_BGTZ(s1, 0);
2475                                 }
2476                         else {
2477                                 if ((iptr->val.i > 0) && (iptr->val.i <= 255)) {
2478                                         M_CMPLE_IMM(s1, iptr->val.i, REG_ITMP1);
2479                                         }
2480                                 else {
2481                                         ICONST(REG_ITMP2, iptr->val.i);
2482                                         M_CMPLE(s1, REG_ITMP2, REG_ITMP1);
2483                                         }
2484                                 M_BEQZ(REG_ITMP1, 0);
2485                                 }
2486                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2487                         break;
2488
2489                 case ICMD_IFGE:         /* ..., value ==> ...                         */
2490                                         /* op1 = target JavaVM pc, val.i = constant   */
2491
2492                         var_to_reg_int(s1, src, REG_ITMP1);
2493                         if (iptr->val.i == 0) {
2494                                 M_BGEZ(s1, 0);
2495                                 }
2496                         else {
2497                                 if ((iptr->val.i > 0) && (iptr->val.i <= 255)) {
2498                                         M_CMPLT_IMM(s1, iptr->val.i, REG_ITMP1);
2499                                         }
2500                                 else {
2501                                         ICONST(REG_ITMP2, iptr->val.i);
2502                                         M_CMPLT(s1, REG_ITMP2, REG_ITMP1);
2503                                         }
2504                                 M_BEQZ(REG_ITMP1, 0);
2505                                 }
2506                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2507                         break;
2508
2509                 case ICMD_IF_LEQ:       /* ..., value ==> ...                         */
2510                                         /* op1 = target JavaVM pc, val.l = constant   */
2511
2512                         var_to_reg_int(s1, src, REG_ITMP1);
2513                         if (iptr->val.l == 0) {
2514                                 M_BEQZ(s1, 0);
2515                                 }
2516                         else {
2517                                 if ((iptr->val.l > 0) && (iptr->val.l <= 255)) {
2518                                         M_CMPEQ_IMM(s1, iptr->val.l, REG_ITMP1);
2519                                         }
2520                                 else {
2521                                         LCONST(REG_ITMP2, iptr->val.l);
2522                                         M_CMPEQ(s1, REG_ITMP2, REG_ITMP1);
2523                                         }
2524                                 M_BNEZ(REG_ITMP1, 0);
2525                                 }
2526                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2527                         break;
2528
2529                 case ICMD_IF_LLT:       /* ..., value ==> ...                         */
2530                                         /* op1 = target JavaVM pc, val.l = constant   */
2531
2532                         var_to_reg_int(s1, src, REG_ITMP1);
2533                         if (iptr->val.l == 0) {
2534                                 M_BLTZ(s1, 0);
2535                                 }
2536                         else {
2537                                 if ((iptr->val.l > 0) && (iptr->val.l <= 255)) {
2538                                         M_CMPLT_IMM(s1, iptr->val.l, REG_ITMP1);
2539                                         }
2540                                 else {
2541                                         LCONST(REG_ITMP2, iptr->val.l);
2542                                         M_CMPLT(s1, REG_ITMP2, REG_ITMP1);
2543                                         }
2544                                 M_BNEZ(REG_ITMP1, 0);
2545                                 }
2546                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2547                         break;
2548
2549                 case ICMD_IF_LLE:       /* ..., value ==> ...                         */
2550                                         /* op1 = target JavaVM pc, val.l = constant   */
2551
2552                         var_to_reg_int(s1, src, REG_ITMP1);
2553                         if (iptr->val.l == 0) {
2554                                 M_BLEZ(s1, 0);
2555                                 }
2556                         else {
2557                                 if ((iptr->val.l > 0) && (iptr->val.l <= 255)) {
2558                                         M_CMPLE_IMM(s1, iptr->val.l, REG_ITMP1);
2559                                         }
2560                                 else {
2561                                         LCONST(REG_ITMP2, iptr->val.l);
2562                                         M_CMPLE(s1, REG_ITMP2, REG_ITMP1);
2563                                         }
2564                                 M_BNEZ(REG_ITMP1, 0);
2565                                 }
2566                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2567                         break;
2568
2569                 case ICMD_IF_LNE:       /* ..., value ==> ...                         */
2570                                         /* op1 = target JavaVM pc, val.l = constant   */
2571
2572                         var_to_reg_int(s1, src, REG_ITMP1);
2573                         if (iptr->val.l == 0) {
2574                                 M_BNEZ(s1, 0);
2575                                 }
2576                         else {
2577                                 if ((iptr->val.l > 0) && (iptr->val.l <= 255)) {
2578                                         M_CMPEQ_IMM(s1, iptr->val.l, REG_ITMP1);
2579                                         }
2580                                 else {
2581                                         LCONST(REG_ITMP2, iptr->val.l);
2582                                         M_CMPEQ(s1, REG_ITMP2, REG_ITMP1);
2583                                         }
2584                                 M_BEQZ(REG_ITMP1, 0);
2585                                 }
2586                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2587                         break;
2588
2589                 case ICMD_IF_LGT:       /* ..., value ==> ...                         */
2590                                         /* op1 = target JavaVM pc, val.l = constant   */
2591
2592                         var_to_reg_int(s1, src, REG_ITMP1);
2593                         if (iptr->val.l == 0) {
2594                                 M_BGTZ(s1, 0);
2595                                 }
2596                         else {
2597                                 if ((iptr->val.l > 0) && (iptr->val.l <= 255)) {
2598                                         M_CMPLE_IMM(s1, iptr->val.l, REG_ITMP1);
2599                                         }
2600                                 else {
2601                                         LCONST(REG_ITMP2, iptr->val.l);
2602                                         M_CMPLE(s1, REG_ITMP2, REG_ITMP1);
2603                                         }
2604                                 M_BEQZ(REG_ITMP1, 0);
2605                                 }
2606                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2607                         break;
2608
2609                 case ICMD_IF_LGE:       /* ..., value ==> ...                         */
2610                                         /* op1 = target JavaVM pc, val.l = constant   */
2611
2612                         var_to_reg_int(s1, src, REG_ITMP1);
2613                         if (iptr->val.l == 0) {
2614                                 M_BGEZ(s1, 0);
2615                                 }
2616                         else {
2617                                 if ((iptr->val.l > 0) && (iptr->val.l <= 255)) {
2618                                         M_CMPLT_IMM(s1, iptr->val.l, REG_ITMP1);
2619                                         }
2620                                 else {
2621                                         LCONST(REG_ITMP2, iptr->val.l);
2622                                         M_CMPLT(s1, REG_ITMP2, REG_ITMP1);
2623                                         }
2624                                 M_BEQZ(REG_ITMP1, 0);
2625                                 }
2626                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2627                         break;
2628
2629                 case ICMD_IF_ICMPEQ:    /* ..., value, value ==> ...                  */
2630                 case ICMD_IF_LCMPEQ:    /* op1 = target JavaVM pc                     */
2631                 case ICMD_IF_ACMPEQ:
2632
2633                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2634                         var_to_reg_int(s2, src, REG_ITMP2);
2635                         M_CMPEQ(s1, s2, REG_ITMP1);
2636                         M_BNEZ(REG_ITMP1, 0);
2637                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2638                         break;
2639
2640                 case ICMD_IF_ICMPNE:    /* ..., value, value ==> ...                  */
2641                 case ICMD_IF_LCMPNE:    /* op1 = target JavaVM pc                     */
2642                 case ICMD_IF_ACMPNE:
2643
2644                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2645                         var_to_reg_int(s2, src, REG_ITMP2);
2646                         M_CMPEQ(s1, s2, REG_ITMP1);
2647                         M_BEQZ(REG_ITMP1, 0);
2648                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2649                         break;
2650
2651                 case ICMD_IF_ICMPLT:    /* ..., value, value ==> ...                  */
2652                 case ICMD_IF_LCMPLT:    /* op1 = target JavaVM pc                     */
2653
2654                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2655                         var_to_reg_int(s2, src, REG_ITMP2);
2656                         M_CMPLT(s1, s2, REG_ITMP1);
2657                         M_BNEZ(REG_ITMP1, 0);
2658                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2659                         break;
2660
2661                 case ICMD_IF_ICMPGT:    /* ..., value, value ==> ...                  */
2662                 case ICMD_IF_LCMPGT:    /* op1 = target JavaVM pc                     */
2663
2664                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2665                         var_to_reg_int(s2, src, REG_ITMP2);
2666                         M_CMPLE(s1, s2, REG_ITMP1);
2667                         M_BEQZ(REG_ITMP1, 0);
2668                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2669                         break;
2670
2671                 case ICMD_IF_ICMPLE:    /* ..., value, value ==> ...                  */
2672                 case ICMD_IF_LCMPLE:    /* op1 = target JavaVM pc                     */
2673
2674                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2675                         var_to_reg_int(s2, src, REG_ITMP2);
2676                         M_CMPLE(s1, s2, REG_ITMP1);
2677                         M_BNEZ(REG_ITMP1, 0);
2678                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2679                         break;
2680
2681                 case ICMD_IF_ICMPGE:    /* ..., value, value ==> ...                  */
2682                 case ICMD_IF_LCMPGE:    /* op1 = target JavaVM pc                     */
2683
2684                         var_to_reg_int(s1, src->prev, REG_ITMP1);
2685                         var_to_reg_int(s2, src, REG_ITMP2);
2686                         M_CMPLT(s1, s2, REG_ITMP1);
2687                         M_BEQZ(REG_ITMP1, 0);
2688                         codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2689                         break;
2690
2691                 /* (value xx 0) ? IFxx_ICONST : ELSE_ICONST                           */
2692
2693                 case ICMD_ELSE_ICONST:  /* handled by IFxx_ICONST                     */
2694                         break;
2695
2696                 case ICMD_IFEQ_ICONST:  /* ..., value ==> ..., constant               */
2697                                         /* val.i = constant                           */
2698
2699                         var_to_reg_int(s1, src, REG_ITMP1);
2700                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
2701                         s3 = iptr->val.i;
2702                         if (iptr[1].opc == ICMD_ELSE_ICONST) {
2703                                 if ((s3 == 1) && (iptr[1].val.i == 0)) {
2704                                         M_CMPEQ(s1, REG_ZERO, d);
2705                                         store_reg_to_var_int(iptr->dst, d);
2706                                         break;
2707                                 }
2708                                 if ((s3 == 0) && (iptr[1].val.i == 1)) {
2709                                         M_CMPEQ(s1, REG_ZERO, d);
2710                                         M_XOR_IMM(d, 1, d);
2711                                         store_reg_to_var_int(iptr->dst, d);
2712                                         break;
2713                                 }
2714                                 if (s1 == d) {
2715                                         M_MOV(s1, REG_ITMP1);
2716                                         s1 = REG_ITMP1;
2717                                 }
2718                                 ICONST(d, iptr[1].val.i);
2719                         }
2720                         if ((s3 >= 0) && (s3 <= 255)) {
2721                                 M_CMOVEQ_IMM(s1, s3, d);
2722                         } else {
2723                                 ICONST(REG_ITMP3, s3);
2724                                 M_CMOVEQ(s1, REG_ITMP3, d);
2725                         }
2726                         store_reg_to_var_int(iptr->dst, d);
2727                         break;
2728
2729                 case ICMD_IFNE_ICONST:  /* ..., value ==> ..., constant               */
2730                                         /* val.i = constant                           */
2731
2732                         var_to_reg_int(s1, src, REG_ITMP1);
2733                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
2734                         s3 = iptr->val.i;
2735                         if (iptr[1].opc == ICMD_ELSE_ICONST) {
2736                                 if ((s3 == 0) && (iptr[1].val.i == 1)) {
2737                                         M_CMPEQ(s1, REG_ZERO, d);
2738                                         store_reg_to_var_int(iptr->dst, d);
2739                                         break;
2740                                 }
2741                                 if ((s3 == 1) && (iptr[1].val.i == 0)) {
2742                                         M_CMPEQ(s1, REG_ZERO, d);
2743                                         M_XOR_IMM(d, 1, d);
2744                                         store_reg_to_var_int(iptr->dst, d);
2745                                         break;
2746                                 }
2747                                 if (s1 == d) {
2748                                         M_MOV(s1, REG_ITMP1);
2749                                         s1 = REG_ITMP1;
2750                                 }
2751                                 ICONST(d, iptr[1].val.i);
2752                         }
2753                         if ((s3 >= 0) && (s3 <= 255)) {
2754                                 M_CMOVNE_IMM(s1, s3, d);
2755                         } else {
2756                                 ICONST(REG_ITMP3, s3);
2757                                 M_CMOVNE(s1, REG_ITMP3, d);
2758                         }
2759                         store_reg_to_var_int(iptr->dst, d);
2760                         break;
2761
2762                 case ICMD_IFLT_ICONST:  /* ..., value ==> ..., constant               */
2763                                         /* val.i = constant                           */
2764
2765                         var_to_reg_int(s1, src, REG_ITMP1);
2766                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
2767                         s3 = iptr->val.i;
2768                         if ((iptr[1].opc == ICMD_ELSE_ICONST)) {
2769                                 if ((s3 == 1) && (iptr[1].val.i == 0)) {
2770                                         M_CMPLT(s1, REG_ZERO, d);
2771                                         store_reg_to_var_int(iptr->dst, d);
2772                                         break;
2773                                 }
2774                                 if ((s3 == 0) && (iptr[1].val.i == 1)) {
2775                                         M_CMPLE(REG_ZERO, s1, d);
2776                                         store_reg_to_var_int(iptr->dst, d);
2777                                         break;
2778                                 }
2779                                 if (s1 == d) {
2780                                         M_MOV(s1, REG_ITMP1);
2781                                         s1 = REG_ITMP1;
2782                                 }
2783                                 ICONST(d, iptr[1].val.i);
2784                         }
2785                         if ((s3 >= 0) && (s3 <= 255)) {
2786                                 M_CMOVLT_IMM(s1, s3, d);
2787                         } else {
2788                                 ICONST(REG_ITMP3, s3);
2789                                 M_CMOVLT(s1, REG_ITMP3, d);
2790                         }
2791                         store_reg_to_var_int(iptr->dst, d);
2792                         break;
2793
2794                 case ICMD_IFGE_ICONST:  /* ..., value ==> ..., constant               */
2795                                         /* val.i = constant                           */
2796
2797                         var_to_reg_int(s1, src, REG_ITMP1);
2798                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
2799                         s3 = iptr->val.i;
2800                         if ((iptr[1].opc == ICMD_ELSE_ICONST)) {
2801                                 if ((s3 == 1) && (iptr[1].val.i == 0)) {
2802                                         M_CMPLE(REG_ZERO, s1, d);
2803                                         store_reg_to_var_int(iptr->dst, d);
2804                                         break;
2805                                 }
2806                                 if ((s3 == 0) && (iptr[1].val.i == 1)) {
2807                                         M_CMPLT(s1, REG_ZERO, d);
2808                                         store_reg_to_var_int(iptr->dst, d);
2809                                         break;
2810                                 }
2811                                 if (s1 == d) {
2812                                         M_MOV(s1, REG_ITMP1);
2813                                         s1 = REG_ITMP1;
2814                                 }
2815                                 ICONST(d, iptr[1].val.i);
2816                         }
2817                         if ((s3 >= 0) && (s3 <= 255)) {
2818                                 M_CMOVGE_IMM(s1, s3, d);
2819                         } else {
2820                                 ICONST(REG_ITMP3, s3);
2821                                 M_CMOVGE(s1, REG_ITMP3, d);
2822                         }
2823                         store_reg_to_var_int(iptr->dst, d);
2824                         break;
2825
2826                 case ICMD_IFGT_ICONST:  /* ..., value ==> ..., constant               */
2827                                         /* val.i = constant                           */
2828
2829                         var_to_reg_int(s1, src, REG_ITMP1);
2830                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
2831                         s3 = iptr->val.i;
2832                         if ((iptr[1].opc == ICMD_ELSE_ICONST)) {
2833                                 if ((s3 == 1) && (iptr[1].val.i == 0)) {
2834                                         M_CMPLT(REG_ZERO, s1, d);
2835                                         store_reg_to_var_int(iptr->dst, d);
2836                                         break;
2837                                 }
2838                                 if ((s3 == 0) && (iptr[1].val.i == 1)) {
2839                                         M_CMPLE(s1, REG_ZERO, d);
2840                                         store_reg_to_var_int(iptr->dst, d);
2841                                         break;
2842                                 }
2843                                 if (s1 == d) {
2844                                         M_MOV(s1, REG_ITMP1);
2845                                         s1 = REG_ITMP1;
2846                                 }
2847                                 ICONST(d, iptr[1].val.i);
2848                         }
2849                         if ((s3 >= 0) && (s3 <= 255)) {
2850                                 M_CMOVGT_IMM(s1, s3, d);
2851                         } else {
2852                                 ICONST(REG_ITMP3, s3);
2853                                 M_CMOVGT(s1, REG_ITMP3, d);
2854                         }
2855                         store_reg_to_var_int(iptr->dst, d);
2856                         break;
2857
2858                 case ICMD_IFLE_ICONST:  /* ..., value ==> ..., constant               */
2859                                         /* val.i = constant                           */
2860
2861                         var_to_reg_int(s1, src, REG_ITMP1);
2862                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
2863                         s3 = iptr->val.i;
2864                         if ((iptr[1].opc == ICMD_ELSE_ICONST)) {
2865                                 if ((s3 == 1) && (iptr[1].val.i == 0)) {
2866                                         M_CMPLE(s1, REG_ZERO, d);
2867                                         store_reg_to_var_int(iptr->dst, d);
2868                                         break;
2869                                 }
2870                                 if ((s3 == 0) && (iptr[1].val.i == 1)) {
2871                                         M_CMPLT(REG_ZERO, s1, d);
2872                                         store_reg_to_var_int(iptr->dst, d);
2873                                         break;
2874                                 }
2875                                 if (s1 == d) {
2876                                         M_MOV(s1, REG_ITMP1);
2877                                         s1 = REG_ITMP1;
2878                                 }
2879                                 ICONST(d, iptr[1].val.i);
2880                         }
2881                         if ((s3 >= 0) && (s3 <= 255)) {
2882                                 M_CMOVLE_IMM(s1, s3, d);
2883                         } else {
2884                                 ICONST(REG_ITMP3, s3);
2885                                 M_CMOVLE(s1, REG_ITMP3, d);
2886                         }
2887                         store_reg_to_var_int(iptr->dst, d);
2888                         break;
2889
2890
2891                 case ICMD_IRETURN:      /* ..., retvalue ==> ...                      */
2892                 case ICMD_LRETURN:
2893
2894                         var_to_reg_int(s1, src, REG_RESULT);
2895                         M_INTMOVE(s1, REG_RESULT);
2896                         goto nowperformreturn;
2897
2898                 case ICMD_ARETURN:      /* ..., retvalue ==> ...                      */
2899
2900                         var_to_reg_int(s1, src, REG_RESULT);
2901                         M_INTMOVE(s1, REG_RESULT);
2902
2903 #ifdef ENABLE_VERIFIER
2904                         if (iptr->val.a) {
2905                                 codegen_addpatchref(cd, mcodeptr,
2906                                                                         PATCHER_athrow_areturn,
2907                                                                         (unresolved_class *) iptr->val.a, 0);
2908
2909                                 if (opt_showdisassemble)
2910                                         M_NOP;
2911                         }
2912 #endif /* ENABLE_VERIFIER */
2913                         goto nowperformreturn;
2914
2915                 case ICMD_FRETURN:      /* ..., retvalue ==> ...                      */
2916                 case ICMD_DRETURN:
2917
2918                         var_to_reg_flt(s1, src, REG_FRESULT);
2919                         M_FLTMOVE(s1, REG_FRESULT);
2920                         goto nowperformreturn;
2921
2922                 case ICMD_RETURN:       /* ...  ==> ...                               */
2923
2924 nowperformreturn:
2925                         {
2926                         s4 i, p;
2927
2928                         p = parentargs_base;
2929
2930                         /* call trace function */
2931
2932                         if (opt_verbosecall) {
2933                                 M_LDA(REG_SP, REG_SP, -3 * 8);
2934                                 M_AST(REG_RA, REG_SP, 0 * 8);
2935                                 M_LST(REG_RESULT, REG_SP, 1 * 8);
2936                                 M_DST(REG_FRESULT, REG_SP, 2 * 8);
2937
2938                                 disp = dseg_addaddress(cd, m);
2939                                 M_ALD(rd->argintregs[0], REG_PV, disp);
2940                                 M_MOV(REG_RESULT, rd->argintregs[1]);
2941                                 M_FLTMOVE(REG_FRESULT, rd->argfltregs[2]);
2942                                 M_FLTMOVE(REG_FRESULT, rd->argfltregs[3]);
2943
2944                                 disp = dseg_addaddress(cd, (void *) builtin_displaymethodstop);
2945                                 M_ALD(REG_PV, REG_PV, disp);
2946                                 M_JSR(REG_RA, REG_PV);
2947                                 disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
2948                                 M_LDA(REG_PV, REG_RA, -disp);
2949
2950                                 M_DLD(REG_FRESULT, REG_SP, 2 * 8);
2951                                 M_LLD(REG_RESULT, REG_SP, 1 * 8);
2952                                 M_ALD(REG_RA, REG_SP, 0 * 8);
2953                                 M_LDA(REG_SP, REG_SP, 3 * 8);
2954                         }
2955
2956 #if defined(USE_THREADS)
2957                         if (checksync && (m->flags & ACC_SYNCHRONIZED)) {
2958                                 M_ALD(rd->argintregs[0], REG_SP, rd->memuse * 8);
2959
2960                                 switch (iptr->opc) {
2961                                 case ICMD_IRETURN:
2962                                 case ICMD_LRETURN:
2963                                 case ICMD_ARETURN:
2964                                         M_LST(REG_RESULT, REG_SP, rd->memuse * 8);
2965                                         break;
2966                                 case ICMD_FRETURN:
2967                                 case ICMD_DRETURN:
2968                                         M_DST(REG_FRESULT, REG_SP, rd->memuse * 8);
2969                                         break;
2970                                 }
2971
2972                                 disp = dseg_addaddress(cd, BUILTIN_monitorexit);
2973                                 M_ALD(REG_PV, REG_PV, disp);
2974                                 M_JSR(REG_RA, REG_PV);
2975                                 disp = -(s4) ((u1 *) mcodeptr - cd->mcodebase);
2976                                 M_LDA(REG_PV, REG_RA, disp);
2977
2978                                 switch (iptr->opc) {
2979                                 case ICMD_IRETURN:
2980                                 case ICMD_LRETURN:
2981                                 case ICMD_ARETURN:
2982                                         M_LLD(REG_RESULT, REG_SP, rd->memuse * 8);
2983                                         break;
2984                                 case ICMD_FRETURN:
2985                                 case ICMD_DRETURN:
2986                                         M_DLD(REG_FRESULT, REG_SP, rd->memuse * 8);
2987                                         break;
2988                                 }
2989                         }
2990 #endif
2991
2992                         /* restore return address                                         */
2993
2994                         if (!m->isleafmethod) {
2995                                 p--; M_LLD(REG_RA, REG_SP, p * 8);
2996                         }
2997
2998                         /* restore saved registers                                        */
2999
3000                         for (i = INT_SAV_CNT - 1; i >= rd->savintreguse; i--) {
3001                                 p--; M_LLD(rd->savintregs[i], REG_SP, p * 8);
3002                         }
3003                         for (i = FLT_SAV_CNT - 1; i >= rd->savfltreguse; i--) {
3004                                 p--; M_DLD(rd->savfltregs[i], REG_SP, p * 8);
3005                         }
3006
3007                         /* deallocate stack                                               */
3008
3009                         if (parentargs_base) {
3010                                 M_LDA(REG_SP, REG_SP, parentargs_base * 8);
3011                         }
3012
3013                         M_RET(REG_ZERO, REG_RA);
3014                         ALIGNCODENOP;
3015                         }
3016                         break;
3017
3018
3019                 case ICMD_TABLESWITCH:  /* ..., index ==> ...                         */
3020                         {
3021                         s4 i, l, *s4ptr;
3022                         void **tptr;
3023
3024                         tptr = (void **) iptr->target;
3025
3026                         s4ptr = iptr->val.a;
3027                         l = s4ptr[1];                          /* low     */
3028                         i = s4ptr[2];                          /* high    */
3029
3030                         var_to_reg_int(s1, src, REG_ITMP1);
3031                         if (l == 0) {
3032                                 M_INTMOVE(s1, REG_ITMP1);
3033                         } else if (l <= 32768) {
3034                                 M_LDA(REG_ITMP1, s1, -l);
3035                         } else {
3036                                 ICONST(REG_ITMP2, l);
3037                                 M_ISUB(s1, REG_ITMP2, REG_ITMP1);
3038                         }
3039                         i = i - l + 1;
3040
3041                         /* range check */
3042
3043                         if (i <= 256)
3044                                 M_CMPULE_IMM(REG_ITMP1, i - 1, REG_ITMP2);
3045                         else {
3046                                 M_LDA(REG_ITMP2, REG_ZERO, i - 1);
3047                                 M_CMPULE(REG_ITMP1, REG_ITMP2, REG_ITMP2);
3048                         }
3049                         M_BEQZ(REG_ITMP2, 0);
3050                         codegen_addreference(cd, (basicblock *) tptr[0], mcodeptr);
3051
3052                         /* build jump table top down and use address of lowest entry */
3053
3054                         /* s4ptr += 3 + i; */
3055                         tptr += i;
3056
3057                         while (--i >= 0) {
3058                                 dseg_addtarget(cd, (basicblock *) tptr[0]);
3059                                 --tptr;
3060                         }
3061                         }
3062
3063                         /* length of dataseg after last dseg_addtarget is used by load */
3064
3065                         M_SAADDQ(REG_ITMP1, REG_PV, REG_ITMP2);
3066                         M_ALD(REG_ITMP2, REG_ITMP2, -(cd->dseglen));
3067                         M_JMP(REG_ZERO, REG_ITMP2);
3068                         ALIGNCODENOP;
3069                         break;
3070
3071
3072                 case ICMD_LOOKUPSWITCH: /* ..., key ==> ...                           */
3073                         {
3074                         s4 i, l, val, *s4ptr;
3075                         void **tptr;
3076
3077                         tptr = (void **) iptr->target;
3078
3079                         s4ptr = iptr->val.a;
3080                         l = s4ptr[0];                          /* default  */
3081                         i = s4ptr[1];                          /* count    */
3082
3083                         MCODECHECK((i<<2)+8);
3084                         var_to_reg_int(s1, src, REG_ITMP1);
3085                         while (--i >= 0) {
3086                                 s4ptr += 2;
3087                                 ++tptr;
3088
3089                                 val = s4ptr[0];
3090                                 if ((val >= 0) && (val <= 255)) {
3091                                         M_CMPEQ_IMM(s1, val, REG_ITMP2);
3092                                 } else {
3093                                         if ((val >= -32768) && (val <= 32767)) {
3094                                                 M_LDA(REG_ITMP2, REG_ZERO, val);
3095                                         } else {
3096                                                 disp = dseg_adds4(cd, val);
3097                                                 M_ILD(REG_ITMP2, REG_PV, disp);
3098                                         }
3099                                         M_CMPEQ(s1, REG_ITMP2, REG_ITMP2);
3100                                 }
3101                                 M_BNEZ(REG_ITMP2, 0);
3102                                 codegen_addreference(cd, (basicblock *) tptr[0], mcodeptr);
3103                         }
3104
3105                         M_BR(0);
3106
3107                         tptr = (void **) iptr->target;
3108                         codegen_addreference(cd, (basicblock *) tptr[0], mcodeptr);
3109
3110                         ALIGNCODENOP;
3111                         break;
3112                         }
3113
3114
3115                 case ICMD_BUILTIN:      /* ..., arg1, arg2, arg3 ==> ...              */
3116                                         /* op1 = arg count val.a = builtintable entry */
3117
3118                         bte = iptr->val.a;
3119                         md = bte->md;
3120                         goto gen_method;
3121
3122                 case ICMD_INVOKESTATIC: /* ..., [arg1, [arg2 ...]] ==> ...            */
3123                                         /* op1 = arg count, val.a = method pointer    */
3124
3125                 case ICMD_INVOKESPECIAL:/* ..., objectref, [arg1, [arg2 ...]] ==> ... */
3126                 case ICMD_INVOKEVIRTUAL:/* op1 = arg count, val.a = method pointer    */
3127                 case ICMD_INVOKEINTERFACE:
3128
3129                         lm = iptr->val.a;
3130
3131                         if (lm == NULL) {
3132                                 unresolved_method *um = iptr->target;
3133                                 md = um->methodref->parseddesc.md;
3134                         } else {
3135                                 md = lm->parseddesc;
3136                         }
3137
3138 gen_method:
3139                         s3 = md->paramcount;
3140
3141                         MCODECHECK((s3 << 1) + 64);
3142
3143                         /* copy arguments to registers or stack location                  */
3144
3145                         for (s3 = s3 - 1; s3 >= 0; s3--, src = src->prev) {
3146                                 if (src->varkind == ARGVAR)
3147                                         continue;
3148                                 if (IS_INT_LNG_TYPE(src->type)) {
3149                                         if (!md->params[s3].inmemory) {
3150                                                 s1 = rd->argintregs[md->params[s3].regoff];
3151                                                 var_to_reg_int(d, src, s1);
3152                                                 M_INTMOVE(d, s1);
3153                                         } else {
3154                                                 var_to_reg_int(d, src, REG_ITMP1);
3155                                                 M_LST(d, REG_SP, md->params[s3].regoff * 8);
3156                                         }
3157
3158                                 } else {
3159                                         if (!md->params[s3].inmemory) {
3160                                                 s1 = rd->argfltregs[md->params[s3].regoff];
3161                                                 var_to_reg_flt(d, src, s1);
3162                                                 M_FLTMOVE(d, s1);
3163                                         } else {
3164                                                 var_to_reg_flt(d, src, REG_FTMP1);
3165                                                 M_DST(d, REG_SP, md->params[s3].regoff * 8);
3166                                         }
3167                                 }
3168                         }
3169
3170                         switch (iptr->opc) {
3171                         case ICMD_BUILTIN:
3172                                 disp = dseg_addaddress(cd, bte->fp);
3173                                 d = md->returntype.type;
3174
3175                                 M_ALD(REG_PV, REG_PV, disp);  /* Pointer to built-in-function */
3176                                 M_JSR(REG_RA, REG_PV);
3177                                 disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3178                                 M_LDA(REG_PV, REG_RA, -disp);
3179
3180                                 /* if op1 == true, we need to check for an exception */
3181
3182                                 if (iptr->op1 == true) {
3183                                         M_BEQZ(REG_RESULT, 0);
3184                                         codegen_add_fillinstacktrace_ref(cd, mcodeptr);
3185                                 }
3186                                 break;
3187
3188                         case ICMD_INVOKESPECIAL:
3189                                 M_BEQZ(rd->argintregs[0], 0);
3190                                 codegen_add_nullpointerexception_ref(cd, mcodeptr);
3191                                 /* fall through */
3192
3193                         case ICMD_INVOKESTATIC:
3194                                 if (!lm) {
3195                                         unresolved_method *um = iptr->target;
3196
3197                                         disp = dseg_addaddress(cd, NULL);
3198
3199                                         codegen_addpatchref(cd, mcodeptr,
3200                                                                                 PATCHER_invokestatic_special, um, disp);
3201
3202                                         if (opt_showdisassemble)
3203                                                 M_NOP;
3204
3205                                         d = um->methodref->parseddesc.md->returntype.type;
3206
3207                                 } else {
3208                                         disp = dseg_addaddress(cd, lm->stubroutine);
3209                                         d = lm->parseddesc->returntype.type;
3210                                 }
3211
3212                                 M_ALD(REG_PV, REG_PV, disp);         /* method pointer in r27 */
3213                                 M_JSR(REG_RA, REG_PV);
3214                                 disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3215                                 M_LDA(REG_PV, REG_RA, -disp);
3216                                 break;
3217
3218                         case ICMD_INVOKEVIRTUAL:
3219                                 gen_nullptr_check(rd->argintregs[0]);
3220
3221                                 if (!lm) {
3222                                         unresolved_method *um = iptr->target;
3223
3224                                         codegen_addpatchref(cd, mcodeptr,
3225                                                                                 PATCHER_invokevirtual, um, 0);
3226
3227                                         if (opt_showdisassemble)
3228                                                 M_NOP;
3229
3230                                         s1 = 0;
3231                                         d = um->methodref->parseddesc.md->returntype.type;
3232
3233                                 } else {
3234                                         s1 = OFFSET(vftbl_t, table[0]) +
3235                                                 sizeof(methodptr) * lm->vftblindex;
3236                                         d = lm->parseddesc->returntype.type;
3237                                 }
3238
3239                                 M_ALD(REG_METHODPTR, rd->argintregs[0],
3240                                           OFFSET(java_objectheader, vftbl));
3241                                 M_ALD(REG_PV, REG_METHODPTR, s1);
3242                                 M_JSR(REG_RA, REG_PV);
3243                                 disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3244                                 M_LDA(REG_PV, REG_RA, -disp);
3245                                 break;
3246
3247                         case ICMD_INVOKEINTERFACE:
3248                                 gen_nullptr_check(rd->argintregs[0]);
3249
3250                                 if (!lm) {
3251                                         unresolved_method *um = iptr->target;
3252
3253                                         codegen_addpatchref(cd, mcodeptr,
3254                                                                                 PATCHER_invokeinterface, um, 0);
3255
3256                                         if (opt_showdisassemble)
3257                                                 M_NOP;
3258
3259                                         s1 = 0;
3260                                         s2 = 0;
3261                                         d = um->methodref->parseddesc.md->returntype.type;
3262
3263                                 } else {
3264                                         s1 = OFFSET(vftbl_t, interfacetable[0]) -
3265                                                 sizeof(methodptr*) * lm->class->index;
3266
3267                                         s2 = sizeof(methodptr) * (lm - lm->class->methods);
3268
3269                                         d = lm->parseddesc->returntype.type;
3270                                 }
3271
3272                                 M_ALD(REG_METHODPTR, rd->argintregs[0],
3273                                           OFFSET(java_objectheader, vftbl));
3274                                 M_ALD(REG_METHODPTR, REG_METHODPTR, s1);
3275                                 M_ALD(REG_PV, REG_METHODPTR, s2);
3276                                 M_JSR(REG_RA, REG_PV);
3277                                 disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3278                                 M_LDA(REG_PV, REG_RA, -disp);
3279                                 break;
3280                         }
3281
3282                         /* d contains return type */
3283
3284                         if (d != TYPE_VOID) {
3285                                 if (IS_INT_LNG_TYPE(iptr->dst->type)) {
3286                                         s1 = reg_of_var(rd, iptr->dst, REG_RESULT);
3287                                         M_INTMOVE(REG_RESULT, s1);
3288                                         store_reg_to_var_int(iptr->dst, s1);
3289                                 } else {
3290                                         s1 = reg_of_var(rd, iptr->dst, REG_FRESULT);
3291                                         M_FLTMOVE(REG_FRESULT, s1);
3292                                         store_reg_to_var_flt(iptr->dst, s1);
3293                                 }
3294                         }
3295                         break;
3296
3297
3298                 case ICMD_CHECKCAST:  /* ..., objectref ==> ..., objectref            */
3299
3300                                       /* op1:   0 == array, 1 == class                */
3301                                       /* val.a: (classinfo*) superclass               */
3302
3303                         /*  superclass is an interface:
3304                          *
3305                          *  OK if ((sub == NULL) ||
3306                          *         (sub->vftbl->interfacetablelength > super->index) &&
3307                          *         (sub->vftbl->interfacetable[-super->index] != NULL));
3308                          *
3309                          *  superclass is a class:
3310                          *
3311                          *  OK if ((sub == NULL) || (0
3312                          *         <= (sub->vftbl->baseval - super->vftbl->baseval) <=
3313                          *         super->vftbl->diffval));
3314                          */
3315
3316                         if (iptr->op1 == 1) {
3317                                 /* object type cast-check */
3318
3319                                 classinfo *super;
3320                                 vftbl_t   *supervftbl;
3321                                 s4         superindex;
3322
3323                                 super = (classinfo *) iptr->val.a;
3324
3325                                 if (!super) {
3326                                         superindex = 0;
3327                                         supervftbl = NULL;
3328
3329                                 } else {
3330                                         superindex = super->index;
3331                                         supervftbl = super->vftbl;
3332                                 }
3333
3334 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3335                                 codegen_threadcritrestart(cd, (u1 *) mcodeptr - cd->mcodebase);
3336 #endif
3337                                 var_to_reg_int(s1, src, REG_ITMP1);
3338
3339                                 /* calculate interface checkcast code size */
3340
3341                                 s2 = 6;
3342                                 if (!super)
3343                                         s2 += opt_showdisassemble ? 1 : 0;
3344
3345                                 /* calculate class checkcast code size */
3346
3347                                 s3 = 9 /* 8 + (s1 == REG_ITMP1) */;
3348                                 if (!super)
3349                                         s3 += opt_showdisassemble ? 1 : 0;
3350
3351                                 /* if class is not resolved, check which code to call */
3352
3353                                 if (!super) {
3354                                         M_BEQZ(s1, 4 + (opt_showdisassemble ? 1 : 0) + s2 + 1 + s3);
3355
3356                                         disp = dseg_adds4(cd, 0);                 /* super->flags */
3357
3358                                         codegen_addpatchref(cd, mcodeptr,
3359                                                                                 PATCHER_checkcast_instanceof_flags,
3360                                                                                 (constant_classref *) iptr->target,
3361                                                                                 disp);
3362
3363                                         if (opt_showdisassemble)
3364                                                 M_NOP;
3365
3366                                         M_ILD(REG_ITMP2, REG_PV, disp);
3367                                         disp = dseg_adds4(cd, ACC_INTERFACE);
3368                                         M_ILD(REG_ITMP3, REG_PV, disp);
3369                                         M_AND(REG_ITMP2, REG_ITMP3, REG_ITMP2);
3370                                         M_BEQZ(REG_ITMP2, s2 + 1);
3371                                 }
3372
3373                                 /* interface checkcast code */
3374
3375                                 if (!super || (super->flags & ACC_INTERFACE)) {
3376                                         if (super) {
3377                                                 M_BEQZ(s1, s2);
3378
3379                                         } else {
3380                                                 codegen_addpatchref(cd, mcodeptr,
3381                                                                                         PATCHER_checkcast_instanceof_interface,
3382                                                                                         (constant_classref *) iptr->target,
3383                                                                                         0);
3384
3385                                                 if (opt_showdisassemble)
3386                                                         M_NOP;
3387                                         }
3388
3389                                         M_ALD(REG_ITMP2, s1, OFFSET(java_objectheader, vftbl));
3390                                         M_ILD(REG_ITMP3, REG_ITMP2,
3391                                                   OFFSET(vftbl_t, interfacetablelength));
3392                                         M_LDA(REG_ITMP3, REG_ITMP3, -superindex);
3393                                         M_BLEZ(REG_ITMP3, 0);
3394                                         codegen_add_classcastexception_ref(cd, mcodeptr);
3395                                         M_ALD(REG_ITMP3, REG_ITMP2,
3396                                                   (s4) (OFFSET(vftbl_t, interfacetable[0]) -
3397                                                                 superindex * sizeof(methodptr*)));
3398                                         M_BEQZ(REG_ITMP3, 0);
3399                                         codegen_add_classcastexception_ref(cd, mcodeptr);
3400
3401                                         if (!super)
3402                                                 M_BR(s3);
3403                                 }
3404
3405                                 /* class checkcast code */
3406
3407                                 if (!super || !(super->flags & ACC_INTERFACE)) {
3408                                         disp = dseg_addaddress(cd, supervftbl);
3409
3410                                         if (super) {
3411                                                 M_BEQZ(s1, s3);
3412
3413                                         } else {
3414                                                 codegen_addpatchref(cd, mcodeptr,
3415                                                                                         PATCHER_checkcast_instanceof_class,
3416                                                                                         (constant_classref *) iptr->target,
3417                                                                                         disp);
3418
3419                                                 if (opt_showdisassemble)
3420                                                         M_NOP;
3421                                         }
3422
3423                                         M_ALD(REG_ITMP2, s1, OFFSET(java_objectheader, vftbl));
3424                                         M_ALD(REG_ITMP3, REG_PV, disp);
3425 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3426                                         codegen_threadcritstart(cd, (u1 *) mcodeptr - cd->mcodebase);
3427 #endif
3428                                         M_ILD(REG_ITMP2, REG_ITMP2, OFFSET(vftbl_t, baseval));
3429                                         /*                              if (s1 != REG_ITMP1) { */
3430                                         /*                                      M_ILD(REG_ITMP1, REG_ITMP3, OFFSET(vftbl_t, baseval)); */
3431                                         /*                                      M_ILD(REG_ITMP3, REG_ITMP3, OFFSET(vftbl_t, diffval)); */
3432                                         /*  #if defined(USE_THREADS) && defined(NATIVE_THREADS) */
3433                                         /*                                      codegen_threadcritstop(cd, (u1 *) mcodeptr - cd->mcodebase); */
3434                                         /*  #endif */
3435                                         /*                                      M_ISUB(REG_ITMP2, REG_ITMP1, REG_ITMP2); */
3436
3437                                         /*                              } else { */
3438                                         M_ILD(REG_ITMP3, REG_ITMP3, OFFSET(vftbl_t, baseval));
3439                                         M_ISUB(REG_ITMP2, REG_ITMP3, REG_ITMP2);
3440                                         M_ALD(REG_ITMP3, REG_PV, disp);
3441                                         M_ILD(REG_ITMP3, REG_ITMP3, OFFSET(vftbl_t, diffval));
3442 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3443                                         codegen_threadcritstop(cd, (u1 *) mcodeptr - cd->mcodebase);
3444 #endif
3445                                         /*                              } */
3446                                         M_CMPULE(REG_ITMP2, REG_ITMP3, REG_ITMP3);
3447                                         M_BEQZ(REG_ITMP3, 0);
3448                                         codegen_add_classcastexception_ref(cd, mcodeptr);
3449                                 }
3450                                 d = reg_of_var(rd, iptr->dst, s1);
3451
3452                         } else {
3453                                 /* array type cast-check */
3454
3455                                 var_to_reg_int(s1, src, rd->argintregs[0]);
3456                                 M_INTMOVE(s1, rd->argintregs[0]);
3457
3458                                 disp = dseg_addaddress(cd, iptr->val.a);
3459
3460                                 if (iptr->val.a == NULL) {
3461                                         codegen_addpatchref(cd, mcodeptr,
3462                                                                                 PATCHER_builtin_arraycheckcast,
3463                                                                                 (constant_classref *) iptr->target,
3464                                                                                 disp);
3465
3466                                         if (opt_showdisassemble)
3467                                                 M_NOP;
3468                                 }
3469
3470                                 M_ALD(rd->argintregs[1], REG_PV, disp);
3471                                 disp = dseg_addaddress(cd, BUILTIN_arraycheckcast);
3472                                 M_ALD(REG_PV, REG_PV, disp);
3473                                 M_JSR(REG_RA, REG_PV);
3474                                 disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3475                                 M_LDA(REG_PV, REG_RA, -disp);
3476
3477                                 M_BEQZ(REG_RESULT, 0);
3478                                 codegen_add_classcastexception_ref(cd, mcodeptr);
3479
3480                                 var_to_reg_int(s1, src, REG_ITMP1);
3481                                 d = reg_of_var(rd, iptr->dst, s1);
3482                         }
3483                         M_INTMOVE(s1, d);
3484                         store_reg_to_var_int(iptr->dst, d);
3485                         break;
3486
3487                 case ICMD_INSTANCEOF: /* ..., objectref ==> ..., intresult            */
3488
3489                                       /* op1:   0 == array, 1 == class                */
3490                                       /* val.a: (classinfo*) superclass               */
3491
3492                         /*  superclass is an interface:
3493                          *
3494                          *  return (sub != NULL) &&
3495                          *         (sub->vftbl->interfacetablelength > super->index) &&
3496                          *         (sub->vftbl->interfacetable[-super->index] != NULL);
3497                          *
3498                          *  superclass is a class:
3499                          *
3500                          *  return ((sub != NULL) && (0
3501                          *          <= (sub->vftbl->baseval - super->vftbl->baseval) <=
3502                          *          super->vftbl->diffvall));
3503                          */
3504
3505                         {
3506                         classinfo *super;
3507                         vftbl_t   *supervftbl;
3508                         s4         superindex;
3509
3510                         super = (classinfo *) iptr->val.a;
3511
3512                         if (!super) {
3513                                 superindex = 0;
3514                                 supervftbl = NULL;
3515
3516                         } else {
3517                                 superindex = super->index;
3518                                 supervftbl = super->vftbl;
3519                         }
3520
3521 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3522                         codegen_threadcritrestart(cd, (u1 *) mcodeptr - cd->mcodebase);
3523 #endif
3524                         var_to_reg_int(s1, src, REG_ITMP1);
3525                         d = reg_of_var(rd, iptr->dst, REG_ITMP2);
3526                         if (s1 == d) {
3527                                 M_MOV(s1, REG_ITMP1);
3528                                 s1 = REG_ITMP1;
3529                         }
3530
3531                         /* calculate interface instanceof code size */
3532
3533                         s2 = 6;
3534                         if (!super)
3535                                 s2 += (d == REG_ITMP2 ? 1 : 0) + (opt_showdisassemble ? 1 : 0);
3536
3537                         /* calculate class instanceof code size */
3538
3539                         s3 = 7;
3540                         if (!super)
3541                                 s3 += (opt_showdisassemble ? 1 : 0);
3542
3543                         /* if class is not resolved, check which code to call */
3544
3545                         if (!super) {
3546                                 M_CLR(d);
3547                                 M_BEQZ(s1, 4 + (opt_showdisassemble ? 1 : 0) + s2 + 1 + s3);
3548
3549                                 disp = dseg_adds4(cd, 0);                     /* super->flags */
3550
3551                                 codegen_addpatchref(cd, mcodeptr,
3552                                                                         PATCHER_checkcast_instanceof_flags,
3553                                                                         (constant_classref *) iptr->target, disp);
3554
3555                                 if (opt_showdisassemble)
3556                                         M_NOP;
3557
3558                                 M_ILD(REG_ITMP3, REG_PV, disp);
3559
3560                                 disp = dseg_adds4(cd, ACC_INTERFACE);
3561                                 M_ILD(REG_ITMP2, REG_PV, disp);
3562                                 M_AND(REG_ITMP3, REG_ITMP2, REG_ITMP3);
3563                                 M_BEQZ(REG_ITMP3, s2 + 1);
3564                         }
3565
3566                         /* interface instanceof code */
3567
3568                         if (!super || (super->flags & ACC_INTERFACE)) {
3569                                 if (super) {
3570                                         M_CLR(d);
3571                                         M_BEQZ(s1, s2);
3572
3573                                 } else {
3574                                         /* If d == REG_ITMP2, then it's destroyed in check code   */
3575                                         /* above.                                                 */
3576                                         if (d == REG_ITMP2)
3577                                                 M_CLR(d);
3578
3579                                         codegen_addpatchref(cd, mcodeptr,
3580                                                                                 PATCHER_checkcast_instanceof_interface,
3581                                                                                 (constant_classref *) iptr->target, 0);
3582
3583                                         if (opt_showdisassemble)
3584                                                 M_NOP;
3585                                 }
3586
3587                                 M_ALD(REG_ITMP1, s1, OFFSET(java_objectheader, vftbl));
3588                                 M_ILD(REG_ITMP3, REG_ITMP1, OFFSET(vftbl_t, interfacetablelength));
3589                                 M_LDA(REG_ITMP3, REG_ITMP3, -superindex);
3590                                 M_BLEZ(REG_ITMP3, 2);
3591                                 M_ALD(REG_ITMP1, REG_ITMP1,
3592                                           (s4) (OFFSET(vftbl_t, interfacetable[0]) -
3593                                                         superindex * sizeof(methodptr*)));
3594                                 M_CMPULT(REG_ZERO, REG_ITMP1, d);      /* REG_ITMP1 != 0  */
3595
3596                                 if (!super)
3597                                         M_BR(s3);
3598                         }
3599
3600                         /* class instanceof code */
3601
3602                         if (!super || !(super->flags & ACC_INTERFACE)) {
3603                                 disp = dseg_addaddress(cd, supervftbl);
3604
3605                                 if (super) {
3606                                         M_CLR(d);
3607                                         M_BEQZ(s1, s3);
3608
3609                                 } else {
3610                                         codegen_addpatchref(cd, mcodeptr,
3611                                                                                 PATCHER_checkcast_instanceof_class,
3612                                                                                 (constant_classref *) iptr->target,
3613                                                                                 disp);
3614
3615                                         if (opt_showdisassemble)
3616                                                 M_NOP;
3617                                 }
3618
3619                                 M_ALD(REG_ITMP1, s1, OFFSET(java_objectheader, vftbl));
3620                                 M_ALD(REG_ITMP2, REG_PV, disp);
3621 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3622                                 codegen_threadcritstart(cd, (u1 *) mcodeptr - cd->mcodebase);
3623 #endif
3624                                 M_ILD(REG_ITMP1, REG_ITMP1, OFFSET(vftbl_t, baseval));
3625                                 M_ILD(REG_ITMP3, REG_ITMP2, OFFSET(vftbl_t, baseval));
3626                                 M_ILD(REG_ITMP2, REG_ITMP2, OFFSET(vftbl_t, diffval));
3627 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3628                                 codegen_threadcritstop(cd, (u1 *) mcodeptr - cd->mcodebase);
3629 #endif
3630                                 M_ISUB(REG_ITMP1, REG_ITMP3, REG_ITMP1);
3631                                 M_CMPULE(REG_ITMP1, REG_ITMP2, d);
3632                         }
3633                         store_reg_to_var_int(iptr->dst, d);
3634                         }
3635                         break;
3636
3637                 case ICMD_MULTIANEWARRAY:/* ..., cnt1, [cnt2, ...] ==> ..., arrayref  */
3638                                       /* op1 = dimension, val.a = class               */
3639
3640                         /* check for negative sizes and copy sizes to stack if necessary  */
3641
3642                         MCODECHECK((iptr->op1 << 1) + 64);
3643
3644                         for (s1 = iptr->op1; --s1 >= 0; src = src->prev) {
3645                                 /* copy SAVEDVAR sizes to stack */
3646
3647                                 if (src->varkind != ARGVAR) {
3648                                         var_to_reg_int(s2, src, REG_ITMP1);
3649                                         M_LST(s2, REG_SP, s1 * 8);
3650                                 }
3651                         }
3652
3653                         /* a0 = dimension count */
3654
3655                         ICONST(rd->argintregs[0], iptr->op1);
3656
3657                         /* is patcher function set? */
3658
3659                         if (iptr->val.a == NULL) {
3660                                 disp = dseg_addaddress(cd, 0);
3661
3662                                 codegen_addpatchref(cd, mcodeptr,
3663                                                                         PATCHER_builtin_multianewarray,
3664                                                                         (constant_classref *) iptr->target,
3665                                                                         disp);
3666
3667                                 if (opt_showdisassemble)
3668                                         M_NOP;
3669
3670                         } else {
3671                                 disp = dseg_addaddress(cd, iptr->val.a);
3672                         }
3673
3674                         /* a1 = arraydescriptor */
3675
3676                         M_ALD(rd->argintregs[1], REG_PV, disp);
3677
3678                         /* a2 = pointer to dimensions = stack pointer */
3679
3680                         M_INTMOVE(REG_SP, rd->argintregs[2]);
3681
3682                         disp = dseg_addaddress(cd, BUILTIN_multianewarray);
3683                         M_ALD(REG_PV, REG_PV, disp);
3684                         M_JSR(REG_RA, REG_PV);
3685                         disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3686                         M_LDA(REG_PV, REG_RA, -disp);
3687
3688                         /* check for exception before result assignment */
3689
3690                         M_BEQZ(REG_RESULT, 0);
3691                         codegen_add_fillinstacktrace_ref(cd, mcodeptr);
3692
3693                         d = reg_of_var(rd, iptr->dst, REG_RESULT);
3694                         M_INTMOVE(REG_RESULT, d);
3695                         store_reg_to_var_int(iptr->dst, d);
3696                         break;
3697
3698                 default:
3699                         *exceptionptr =
3700                                 new_internalerror("Unknown ICMD %d", iptr->opc);
3701                         return false;
3702         } /* switch */
3703
3704         } /* for instruction */
3705
3706         /* copy values to interface registers */
3707
3708         src = bptr->outstack;
3709         len = bptr->outdepth;
3710         MCODECHECK(64+len);
3711 #if defined(ENABLE_LSRA)
3712         if (!opt_lsra)
3713 #endif
3714         while (src) {
3715                 len--;
3716                 if ((src->varkind != STACKVAR)) {
3717                         s2 = src->type;
3718                         if (IS_FLT_DBL_TYPE(s2)) {
3719                                 var_to_reg_flt(s1, src, REG_FTMP1);
3720                                 if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
3721                                         M_FLTMOVE(s1,rd->interfaces[len][s2].regoff);
3722                                         }
3723                                 else {
3724                                         M_DST(s1, REG_SP, 8 * rd->interfaces[len][s2].regoff);
3725                                         }
3726                                 }
3727                         else {
3728                                 var_to_reg_int(s1, src, REG_ITMP1);
3729                                 if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
3730                                         M_INTMOVE(s1,rd->interfaces[len][s2].regoff);
3731                                         }
3732                                 else {
3733                                         M_LST(s1, REG_SP, 8 * rd->interfaces[len][s2].regoff);
3734                                         }
3735                                 }
3736                         }
3737                 src = src->prev;
3738                 }
3739         } /* if (bptr -> flags >= BBREACHED) */
3740         } /* for basic block */
3741
3742         dseg_createlinenumbertable(cd);
3743
3744
3745         /* generate exception and patcher stubs */
3746
3747         {
3748                 exceptionref *eref;
3749                 patchref     *pref;
3750                 u4            mcode;
3751                 s4           *savedmcodeptr;
3752                 s4           *tmpmcodeptr;
3753
3754                 savedmcodeptr = NULL;
3755
3756                 /* generate exception stubs */
3757
3758                 for (eref = cd->exceptionrefs; eref != NULL; eref = eref->next) {
3759                         gen_resolvebranch((u1 *) cd->mcodebase + eref->branchpos,
3760                                                           eref->branchpos,
3761                                                           (u1 *) mcodeptr - cd->mcodebase);
3762
3763                         MCODECHECK(100);
3764
3765                         /* move index register into REG_ITMP1 */
3766
3767                         /* Check if the exception is an
3768                            ArrayIndexOutOfBoundsException.  If so, move index register
3769                            into REG_ITMP1. */
3770
3771                         if (eref->reg != -1)
3772                                 M_MOV(eref->reg, REG_ITMP1);
3773
3774                         /* calcuate exception address */
3775
3776                         M_LDA(REG_ITMP2_XPC, REG_PV, eref->branchpos - 4);
3777
3778                         /* move function to call into REG_ITMP3 */
3779
3780                         disp = dseg_addaddress(cd, eref->function);
3781                         M_ALD(REG_ITMP3, REG_PV, disp);
3782
3783                         if (savedmcodeptr != NULL) {
3784                                 disp = savedmcodeptr - mcodeptr - 1;
3785                                 M_BR(disp);
3786
3787                         } else {
3788                                 savedmcodeptr = mcodeptr;
3789
3790                                 M_MOV(REG_PV, rd->argintregs[0]);
3791                                 M_MOV(REG_SP, rd->argintregs[1]);
3792
3793                                 if (m->isleafmethod)
3794                                         M_MOV(REG_RA, rd->argintregs[2]);
3795                                 else
3796                                         M_ALD(rd->argintregs[2],
3797                                                   REG_SP, parentargs_base * 8 - SIZEOF_VOID_P);
3798
3799                                 M_MOV(REG_ITMP2_XPC, rd->argintregs[3]);
3800                                 M_MOV(REG_ITMP1, rd->argintregs[4]);
3801
3802                                 M_LDA(REG_SP, REG_SP, -2 * 8);
3803                                 M_AST(REG_ITMP2_XPC, REG_SP, 0 * 8);
3804
3805                                 if (m->isleafmethod)
3806                                         M_AST(REG_RA, REG_SP, 1 * 8);
3807
3808                                 M_MOV(REG_ITMP3, REG_PV);
3809                                 M_JSR(REG_RA, REG_PV);
3810                                 disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
3811                                 M_LDA(REG_PV, REG_RA, -disp);
3812
3813                                 M_MOV(REG_RESULT, REG_ITMP1_XPTR);
3814
3815                                 if (m->isleafmethod)
3816                                         M_ALD(REG_RA, REG_SP, 1 * 8);
3817
3818                                 M_ALD(REG_ITMP2_XPC, REG_SP, 0 * 8);
3819                                 M_LDA(REG_SP, REG_SP, 2 * 8);
3820
3821                                 disp = dseg_addaddress(cd, asm_handle_exception);
3822                                 M_ALD(REG_ITMP3, REG_PV, disp);
3823                                 M_JMP(REG_ZERO, REG_ITMP3);
3824                         }
3825                 }
3826
3827
3828                 /* generate code patching stub call code */
3829
3830                 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
3831                         /* check code segment size */
3832
3833                         MCODECHECK(100);
3834
3835                         /* Get machine code which is patched back in later. The
3836                            call is 1 instruction word long. */
3837
3838                         savedmcodeptr = (s4 *) (cd->mcodebase + pref->branchpos);
3839                         mcode = *savedmcodeptr;
3840
3841                         /* Patch in the call to call the following code (done at
3842                            compile time). */
3843
3844                         tmpmcodeptr = mcodeptr;         /* save current mcodeptr          */
3845                         mcodeptr    = savedmcodeptr;    /* set mcodeptr to patch position */
3846
3847                         M_BSR(REG_ITMP3, tmpmcodeptr - (savedmcodeptr + 1));
3848
3849                         mcodeptr = tmpmcodeptr;         /* restore the current mcodeptr   */
3850
3851                         /* create stack frame */
3852
3853                         M_LSUB_IMM(REG_SP, 6 * 8, REG_SP);
3854
3855                         /* move return address onto stack */
3856
3857                         M_AST(REG_ITMP3, REG_SP, 5 * 8);
3858
3859                         /* move pointer to java_objectheader onto stack */
3860
3861 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3862                         /* create a virtual java_objectheader */
3863
3864                         (void) dseg_addaddress(cd, get_dummyLR());          /* monitorPtr */
3865                         disp = dseg_addaddress(cd, NULL);                   /* vftbl      */
3866
3867                         M_LDA(REG_ITMP3, REG_PV, disp);
3868                         M_AST(REG_ITMP3, REG_SP, 4 * 8);
3869 #else
3870                         /* do nothing */
3871 #endif
3872
3873                         /* move machine code onto stack */
3874
3875                         disp = dseg_adds4(cd, mcode);
3876                         M_ILD(REG_ITMP3, REG_PV, disp);
3877                         M_IST(REG_ITMP3, REG_SP, 3 * 8);
3878
3879                         /* move class/method/field reference onto stack */
3880
3881                         disp = dseg_addaddress(cd, pref->ref);
3882                         M_ALD(REG_ITMP3, REG_PV, disp);
3883                         M_AST(REG_ITMP3, REG_SP, 2 * 8);
3884
3885                         /* move data segment displacement onto stack */
3886
3887                         disp = dseg_adds4(cd, pref->disp);
3888                         M_ILD(REG_ITMP3, REG_PV, disp);
3889                         M_IST(REG_ITMP3, REG_SP, 1 * 8);
3890
3891                         /* move patcher function pointer onto stack */
3892
3893                         disp = dseg_addaddress(cd, pref->patcher);
3894                         M_ALD(REG_ITMP3, REG_PV, disp);
3895                         M_AST(REG_ITMP3, REG_SP, 0 * 8);
3896
3897                         disp = dseg_addaddress(cd, asm_wrapper_patcher);
3898                         M_ALD(REG_ITMP3, REG_PV, disp);
3899                         M_JMP(REG_ZERO, REG_ITMP3);
3900                 }
3901
3902                 /* generate replacement-out stubs */
3903
3904                 {
3905                         int i;
3906
3907                         replacementpoint = cd->code->rplpoints;
3908                         for (i=0; i<cd->code->rplpointcount; ++i, ++replacementpoint) {
3909                                 /* check code segment size */
3910
3911                                 MCODECHECK(100);
3912
3913                                 /* note start of stub code */
3914
3915                                 replacementpoint->outcode = (u1*) (ptrint)((u1*)mcodeptr - cd->mcodebase);
3916
3917                                 /* make machine code for patching */
3918
3919                                 tmpmcodeptr = mcodeptr;
3920                                 mcodeptr = (s4*) &(replacementpoint->mcode);
3921
3922                                 disp = (ptrint)((s4*)replacementpoint->outcode - (s4*)replacementpoint->pc) - 1;
3923                                 M_BR(disp);
3924
3925                                 mcodeptr = tmpmcodeptr;
3926
3927                                 /* create stack frame */
3928
3929                                 M_LSUB_IMM(REG_SP, 1 * 8, REG_SP);
3930
3931                                 /* push address of `rplpoint` struct */
3932
3933                                 disp = dseg_addaddress(cd, replacementpoint);
3934                                 M_ALD(REG_ITMP3, REG_PV, disp);
3935                                 M_AST(REG_ITMP3, REG_SP, 0 * 8);
3936
3937                                 /* jump to replacement function */
3938
3939                                 disp = dseg_addaddress(cd, asm_replacement_out);
3940                                 M_ALD(REG_ITMP3, REG_PV, disp);
3941                                 M_JMP(REG_ZERO, REG_ITMP3);
3942                         }
3943                 }
3944         }
3945
3946         codegen_finish(m, cd, (s4) ((u1 *) mcodeptr - cd->mcodebase));
3947
3948         /* everything's ok */
3949
3950         return true;
3951 }
3952
3953
3954 /* createcompilerstub **********************************************************
3955
3956    Creates a stub routine which calls the compiler.
3957
3958 *******************************************************************************/
3959
3960 #define COMPILERSTUB_DATASIZE    2 * SIZEOF_VOID_P
3961 #define COMPILERSTUB_CODESIZE    3 * 4
3962
3963 #define COMPILERSTUB_SIZE        COMPILERSTUB_DATASIZE + COMPILERSTUB_CODESIZE
3964
3965
3966 u1 *createcompilerstub(methodinfo *m)
3967 {
3968         u1     *s;                          /* memory to hold the stub            */
3969         ptrint *d;
3970         s4     *mcodeptr;                   /* code generation pointer            */
3971
3972         s = CNEW(u1, COMPILERSTUB_SIZE);
3973
3974         /* set data pointer and code pointer */
3975
3976         d = (ptrint *) s;
3977         s = s + COMPILERSTUB_DATASIZE;
3978
3979         mcodeptr = (s4 *) s;
3980
3981         /* Store the methodinfo* in the same place as in the methodheader
3982            for compiled methods. */
3983
3984         d[0] = (ptrint) asm_call_jit_compiler;
3985         d[1] = (ptrint) m;
3986
3987         /* code for the stub */
3988
3989         M_ALD(REG_ITMP1, REG_PV, -1 * 8);   /* load methodinfo pointer            */
3990         M_ALD(REG_PV, REG_PV, -2 * 8);      /* load pointer to the compiler       */
3991         M_JMP(REG_ZERO, REG_PV);            /* jump to the compiler               */
3992
3993 #if defined(ENABLE_STATISTICS)
3994         if (opt_stat)
3995                 count_cstub_len += COMPILERSTUB_SIZE;
3996 #endif
3997
3998         return s;
3999 }
4000
4001
4002 /* createnativestub ************************************************************
4003
4004    Creates a stub routine which calls a native method.
4005
4006 *******************************************************************************/
4007
4008 u1 *createnativestub(functionptr f, methodinfo *m, codegendata *cd,
4009                                          registerdata *rd, methoddesc *nmd)
4010 {
4011         s4         *mcodeptr;               /* code generation pointer            */
4012         s4          stackframesize;         /* size of stackframe if needed       */
4013         methoddesc *md;
4014         s4          nativeparams;
4015         s4          i, j;                   /* count variables                    */
4016         s4          t;
4017         s4          s1, s2, disp;
4018         s4          funcdisp;               /* displacement of the function       */
4019
4020         /* initialize variables */
4021
4022         md = m->parseddesc;
4023         nativeparams = (m->flags & ACC_STATIC) ? 2 : 1;
4024
4025
4026         /* calculate stack frame size */
4027
4028         stackframesize =
4029                 1 +                             /* return address                     */
4030                 sizeof(stackframeinfo) / SIZEOF_VOID_P +
4031                 sizeof(localref_table) / SIZEOF_VOID_P +
4032                 1 +                             /* methodinfo for call trace          */
4033                 (md->paramcount > INT_ARG_CNT ? INT_ARG_CNT : md->paramcount) +
4034                 nmd->memuse;
4035
4036
4037         /* create method header */
4038
4039         (void) dseg_addaddress(cd, m);                          /* MethodPointer  */
4040         (void) dseg_adds4(cd, stackframesize * 8);              /* FrameSize      */
4041         (void) dseg_adds4(cd, 0);                               /* IsSync         */
4042         (void) dseg_adds4(cd, 0);                               /* IsLeaf         */
4043         (void) dseg_adds4(cd, 0);                               /* IntSave        */
4044         (void) dseg_adds4(cd, 0);                               /* FltSave        */
4045         (void) dseg_addlinenumbertablesize(cd);
4046         (void) dseg_adds4(cd, 0);                               /* ExTableSize    */
4047
4048
4049         /* initialize mcode variables */
4050
4051         mcodeptr = (s4 *) cd->mcodeptr;
4052
4053
4054         /* generate stub code */
4055
4056         M_LDA(REG_SP, REG_SP, -stackframesize * 8);
4057         M_AST(REG_RA, REG_SP, stackframesize * 8 - SIZEOF_VOID_P);
4058
4059
4060         /* call trace function */
4061
4062         if (opt_verbosecall) {
4063                 /* save integer argument registers */
4064
4065                 for (i = 0, j = 1; i < md->paramcount && i < INT_ARG_CNT; i++) {
4066                         if (IS_INT_LNG_TYPE(md->paramtypes[i].type)) {
4067                                 M_LST(rd->argintregs[i], REG_SP, j * 8);
4068                                 j++;
4069                         }
4070                 }
4071
4072                 /* save and copy float arguments into integer registers */
4073
4074                 for (i = 0; i < md->paramcount && i < FLT_ARG_CNT; i++) {
4075                         t = md->paramtypes[i].type;
4076
4077                         if (IS_FLT_DBL_TYPE(t)) {
4078                                 if (IS_2_WORD_TYPE(t)) {
4079                                         M_DST(rd->argfltregs[i], REG_SP, j * 8);
4080                                         M_LLD(rd->argintregs[i], REG_SP, j * 8);
4081                                 } else {
4082                                         M_FST(rd->argfltregs[i], REG_SP, j * 8);
4083                                         M_ILD(rd->argintregs[i], REG_SP, j * 8);
4084                                 }
4085                                 j++;
4086                         }
4087                 }
4088
4089                 disp = dseg_addaddress(cd, m);
4090                 M_ALD(REG_ITMP1, REG_PV, disp);
4091                 M_AST(REG_ITMP1, REG_SP, 0 * 8);
4092                 disp = dseg_addaddress(cd, builtin_trace_args);
4093                 M_ALD(REG_PV, REG_PV, disp);
4094                 M_JSR(REG_RA, REG_PV);
4095                 disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
4096                 M_LDA(REG_PV, REG_RA, -disp);
4097
4098                 for (i = 0, j = 1; i < md->paramcount && i < INT_ARG_CNT; i++) {
4099                         if (IS_INT_LNG_TYPE(md->paramtypes[i].type)) {
4100                                 M_LLD(rd->argintregs[i], REG_SP, j * 8);
4101                                 j++;
4102                         }
4103                 }
4104
4105                 for (i = 0; i < md->paramcount && i < FLT_ARG_CNT; i++) {
4106                         t = md->paramtypes[i].type;
4107
4108                         if (IS_FLT_DBL_TYPE(t)) {
4109                                 if (IS_2_WORD_TYPE(t)) {
4110                                         M_DLD(rd->argfltregs[i], REG_SP, j * 8);
4111                                 } else {
4112                                         M_FLD(rd->argfltregs[i], REG_SP, j * 8);
4113                                 }
4114                                 j++;
4115                         }
4116                 }
4117         }
4118
4119         /* get function address (this must happen before the stackframeinfo) */
4120
4121         funcdisp = dseg_addaddress(cd, f);
4122
4123 #if !defined(WITH_STATIC_CLASSPATH)
4124         if (f == NULL) {
4125                 codegen_addpatchref(cd, mcodeptr, PATCHER_resolve_native, m, funcdisp);
4126
4127                 if (opt_showdisassemble)
4128                         M_NOP;
4129         }
4130 #endif
4131
4132         /* save integer and float argument registers */
4133
4134         for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++) {
4135                 if (IS_INT_LNG_TYPE(md->paramtypes[i].type)) {
4136                         M_LST(rd->argintregs[i], REG_SP, j * 8);
4137                         j++;
4138                 }
4139         }
4140
4141         for (i = 0; i < md->paramcount && i < FLT_ARG_CNT; i++) {
4142                 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
4143                         M_DST(rd->argfltregs[i], REG_SP, j * 8);
4144                         j++;
4145                 }
4146         }
4147
4148         /* prepare data structures for native function call */
4149
4150         M_LDA(rd->argintregs[0], REG_SP, stackframesize * 8 - SIZEOF_VOID_P);
4151         M_MOV(REG_PV, rd->argintregs[1]);
4152         M_LDA(rd->argintregs[2], REG_SP, stackframesize * 8);
4153         M_ALD(rd->argintregs[3], REG_SP, stackframesize * 8 - SIZEOF_VOID_P);
4154         disp = dseg_addaddress(cd, codegen_start_native_call);
4155         M_ALD(REG_PV, REG_PV, disp);
4156         M_JSR(REG_RA, REG_PV);
4157         disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
4158         M_LDA(REG_PV, REG_RA, -disp);
4159
4160         /* restore integer and float argument registers */
4161
4162         for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++) {
4163                 if (IS_INT_LNG_TYPE(md->paramtypes[i].type)) {
4164                         M_LLD(rd->argintregs[i], REG_SP, j * 8);
4165                         j++;
4166                 }
4167         }
4168
4169         for (i = 0; i < md->paramcount && i < FLT_ARG_CNT; i++) {
4170                 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
4171                         M_DLD(rd->argfltregs[i], REG_SP, j * 8);
4172                         j++;
4173                 }
4174         }
4175
4176         /* copy or spill arguments to new locations */
4177
4178         for (i = md->paramcount - 1, j = i + nativeparams; i >= 0; i--, j--) {
4179                 t = md->paramtypes[i].type;
4180
4181                 if (IS_INT_LNG_TYPE(t)) {
4182                         if (!md->params[i].inmemory) {
4183                                 s1 = rd->argintregs[md->params[i].regoff];
4184
4185                                 if (!nmd->params[j].inmemory) {
4186                                         s2 = rd->argintregs[nmd->params[j].regoff];
4187                                         M_INTMOVE(s1, s2);
4188
4189                                 } else {
4190                                         s2 = nmd->params[j].regoff;
4191                                         M_LST(s1, REG_SP, s2 * 8);
4192                                 }
4193
4194                         } else {
4195                                 s1 = md->params[i].regoff + stackframesize;
4196                                 s2 = nmd->params[j].regoff;
4197                                 M_LLD(REG_ITMP1, REG_SP, s1 * 8);
4198                                 M_LST(REG_ITMP1, REG_SP, s2 * 8);
4199                         }
4200
4201                 } else {
4202                         if (!md->params[i].inmemory) {
4203                                 s1 = rd->argfltregs[md->params[i].regoff];
4204
4205                                 if (!nmd->params[j].inmemory) {
4206                                         s2 = rd->argfltregs[nmd->params[j].regoff];
4207                                         M_FLTMOVE(s1, s2);
4208
4209                                 } else {
4210                                         s2 = nmd->params[j].regoff;
4211                                         if (IS_2_WORD_TYPE(t))
4212                                                 M_DST(s1, REG_SP, s2 * 8);
4213                                         else
4214                                                 M_FST(s1, REG_SP, s2 * 8);
4215                                 }
4216
4217                         } else {
4218                                 s1 = md->params[i].regoff + stackframesize;
4219                                 s2 = nmd->params[j].regoff;
4220                                 M_DLD(REG_FTMP1, REG_SP, s1 * 8);
4221                                 if (IS_2_WORD_TYPE(t))
4222                                         M_DST(REG_FTMP1, REG_SP, s2 * 8);
4223                                 else
4224                                         M_FST(REG_FTMP1, REG_SP, s2 * 8);
4225                         }
4226                 }
4227         }
4228
4229         /* put class into second argument register */
4230
4231         if (m->flags & ACC_STATIC) {
4232                 disp = dseg_addaddress(cd, m->class);
4233                 M_ALD(rd->argintregs[1], REG_PV, disp);
4234         }
4235
4236         /* put env into first argument register */
4237
4238         disp = dseg_addaddress(cd, _Jv_env);
4239         M_ALD(rd->argintregs[0], REG_PV, disp);
4240
4241         /* do the native function call */
4242
4243         M_ALD(REG_PV, REG_PV, funcdisp);
4244         M_JSR(REG_RA, REG_PV);              /* call native method                 */
4245         disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
4246         M_LDA(REG_PV, REG_RA, -disp);       /* recompute pv from ra               */
4247
4248         /* save return value */
4249
4250         if (IS_INT_LNG_TYPE(md->returntype.type))
4251                 M_LST(REG_RESULT, REG_SP, 0 * 8);
4252         else
4253                 M_DST(REG_FRESULT, REG_SP, 0 * 8);
4254
4255         /* remove native stackframe info */
4256
4257         M_LDA(rd->argintregs[0], REG_SP, stackframesize * 8 - SIZEOF_VOID_P);
4258         disp = dseg_addaddress(cd, codegen_finish_native_call);
4259         M_ALD(REG_PV, REG_PV, disp);
4260         M_JSR(REG_RA, REG_PV);
4261         disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
4262         M_LDA(REG_PV, REG_RA, -disp);
4263
4264         /* call finished trace */
4265
4266         if (opt_verbosecall) {
4267                 /* just restore the value we need, don't care about the other */
4268
4269                 if (IS_INT_LNG_TYPE(md->returntype.type))
4270                         M_LLD(REG_RESULT, REG_SP, 0 * 8);
4271                 else
4272                         M_DLD(REG_FRESULT, REG_SP, 0 * 8);
4273
4274                 disp = dseg_addaddress(cd, m);
4275                 M_ALD(rd->argintregs[0], REG_PV, disp);
4276
4277                 M_MOV(REG_RESULT, rd->argintregs[1]);
4278                 M_FMOV(REG_FRESULT, rd->argfltregs[2]);
4279                 M_FMOV(REG_FRESULT, rd->argfltregs[3]);
4280
4281                 disp = dseg_addaddress(cd, builtin_displaymethodstop);
4282                 M_ALD(REG_PV, REG_PV, disp);
4283                 M_JSR(REG_RA, REG_PV);
4284                 disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
4285                 M_LDA(REG_PV, REG_RA, -disp);
4286         }
4287
4288         /* check for exception */
4289
4290 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
4291         disp = dseg_addaddress(cd, builtin_get_exceptionptrptr);
4292         M_ALD(REG_PV, REG_PV, disp);
4293         M_JSR(REG_RA, REG_PV);
4294         disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
4295         M_LDA(REG_PV, REG_RA, -disp);
4296         M_MOV(REG_RESULT, REG_ITMP3);
4297 #else
4298         disp = dseg_addaddress(cd, &_exceptionptr);
4299         M_ALD(REG_RESULT, REG_PV, disp);    /* get address of exceptionptr        */
4300 #endif
4301         M_ALD(REG_ITMP1, REG_ITMP3, 0);     /* load exception into reg. itmp1     */
4302
4303         /* restore return value */
4304
4305         if (IS_INT_LNG_TYPE(md->returntype.type))
4306                 M_LLD(REG_RESULT, REG_SP, 0 * 8);
4307         else
4308                 M_DLD(REG_FRESULT, REG_SP, 0 * 8);
4309
4310         M_BNEZ(REG_ITMP1, 3);               /* if no exception then return        */
4311
4312         M_ALD(REG_RA, REG_SP, (stackframesize - 1) * 8); /* load return address   */
4313         M_LDA(REG_SP, REG_SP, stackframesize * 8);
4314         M_RET(REG_ZERO, REG_RA);            /* return to caller                   */
4315
4316         /* handle exception */
4317
4318         M_AST(REG_ZERO, REG_ITMP3, 0);      /* store NULL into exceptionptr       */
4319
4320         M_ALD(REG_RA, REG_SP, (stackframesize - 1) * 8); /* load return address   */
4321         M_LDA(REG_ITMP2, REG_RA, -4);       /* move fault address into reg. itmp2 */
4322
4323         M_LDA(REG_SP, REG_SP, stackframesize * 8);
4324
4325         disp = dseg_addaddress(cd, asm_handle_nat_exception);
4326         M_ALD(REG_ITMP3, REG_PV, disp);     /* load asm exception handler address */
4327         M_JMP(REG_ZERO, REG_ITMP3);         /* jump to asm exception handler      */
4328
4329
4330         /* process patcher calls **************************************************/
4331
4332         {
4333                 patchref *pref;
4334                 u4        mcode;
4335                 s4       *savedmcodeptr;
4336                 s4       *tmpmcodeptr;
4337
4338                 /* there can only be one <clinit> ref entry */
4339
4340                 pref = cd->patchrefs;
4341
4342                 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
4343                         /* Get machine code which is patched back in later. The
4344                            call is 1 instruction word long. */
4345
4346                         savedmcodeptr = (s4 *) (cd->mcodebase + pref->branchpos);
4347                         mcode = (u4) *savedmcodeptr;
4348
4349                         /* patch in the call to call the following code (done at compile  */
4350                         /* time)                                                          */
4351
4352                         tmpmcodeptr = mcodeptr;         /* save current mcodeptr          */
4353                         mcodeptr    = savedmcodeptr;    /* set mcodeptr to patch position */
4354
4355                         M_BSR(REG_ITMP3, tmpmcodeptr - (savedmcodeptr + 1));
4356
4357                         mcodeptr = tmpmcodeptr;         /* restore the current mcodeptr   */
4358
4359                         /* create stack frame */
4360
4361                         M_LSUB_IMM(REG_SP, 6 * 8, REG_SP);
4362
4363                         /* move return address onto stack */
4364
4365                         M_AST(REG_ITMP3, REG_SP, 5 * 8);
4366
4367                         /* move pointer to java_objectheader onto stack */
4368
4369 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
4370                         /* create a virtual java_objectheader */
4371
4372                         (void) dseg_addaddress(cd, get_dummyLR());          /* monitorPtr */
4373                         disp = dseg_addaddress(cd, NULL);                   /* vftbl      */
4374
4375                         M_LDA(REG_ITMP3, REG_PV, disp);
4376                         M_AST(REG_ITMP3, REG_SP, 4 * 8);
4377 #else
4378                         M_AST(REG_ZERO, REG_SP, 4 * 8);
4379 #endif
4380
4381                         /* move machine code onto stack */
4382
4383                         disp = dseg_adds4(cd, mcode);
4384                         M_ILD(REG_ITMP3, REG_PV, disp);
4385                         M_IST(REG_ITMP3, REG_SP, 3 * 8);
4386
4387                         /* move class/method/field reference onto stack */
4388
4389                         disp = dseg_addaddress(cd, pref->ref);
4390                         M_ALD(REG_ITMP3, REG_PV, disp);
4391                         M_AST(REG_ITMP3, REG_SP, 2 * 8);
4392
4393                         /* move data segment displacement onto stack */
4394
4395                         disp = dseg_adds4(cd, pref->disp);
4396                         M_ILD(REG_ITMP3, REG_PV, disp);
4397                         M_IST(REG_ITMP3, REG_SP, 1 * 8);
4398
4399                         /* move patcher function pointer onto stack */
4400
4401                         disp = dseg_addaddress(cd, pref->patcher);
4402                         M_ALD(REG_ITMP3, REG_PV, disp);
4403                         M_AST(REG_ITMP3, REG_SP, 0 * 8);
4404
4405                         disp = dseg_addaddress(cd, asm_wrapper_patcher);
4406                         M_ALD(REG_ITMP3, REG_PV, disp);
4407                         M_JMP(REG_ZERO, REG_ITMP3);
4408                 }
4409         }
4410
4411         codegen_finish(m, cd, (s4) ((u1 *) mcodeptr - cd->mcodebase));
4412
4413         return cd->code->entrypoint;
4414 }
4415
4416
4417 /*
4418  * These are local overrides for various environment variables in Emacs.
4419  * Please do not remove this and leave it at the end of the file, where
4420  * Emacs will automagically detect them.
4421  * ---------------------------------------------------------------------
4422  * Local variables:
4423  * mode: c
4424  * indent-tabs-mode: t
4425  * c-basic-offset: 4
4426  * tab-width: 4
4427  * End:
4428  * vim:noexpandtab:sw=4:ts=4:
4429  */