5 * Config Southbridge EC Controller
9 * @xrefitem bom "File Content Label" "Release Content"
12 * @e \$Revision:$ @e \$Date:$
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42 ;*********************************************************************************/
44 #include "SbPlatform.h"
50 * Config EC controller during power-on
54 * @param[in] pConfig Southbridge configuration structure pointer.
65 //Do settings for mailbox - logical device 0x09
66 RWEC8 (0x07, 0x00, 0x09); //switch to device 9 (Mailbox)
67 RWEC8 (0x60, 0x00, (MailBoxPort >> 8)); //set MSB of Mailbox port
68 RWEC8 (0x61, 0x00, (MailBoxPort & 0xFF)); //set LSB of Mailbox port
69 RWEC8 (0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1
71 if ( pConfig->BuildParameters.EcKbd == ENABLED) {
72 //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
73 RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6, AccWidthUint8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3);
75 //Disable LPC Decoding of port 60/64
76 RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~BIT5, 0);
78 //Enable logical device 0x07 (Keyboard controller)
79 RWEC8 (0x07, 0x00, 0x07);
80 RWEC8 (0x30, 0x00, 0x01);
83 if (isImcEnabled () && ( pConfig->BuildParameters.EcChannel0 == ENABLED)) {
85 RWEC8 (0x07, 0x00, 0x03);
86 RWEC8 (0x60, 0x00, 0x00);
87 RWEC8 (0x61, 0x00, 0x62);
88 RWEC8 (0x30, 0x00, 0x01); //;Enable Device 3
91 //Enable EC (IMC) to generate SMI to BIOS
92 RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB3, AccWidthUint8, ~BIT6, BIT6);
97 * Config EC controller before PCI emulation
101 * @param[in] pConfig Southbridge configuration structure pointer.
105 ecInitBeforePciEnum (
109 AMDSBCFG* pTmp; // dummy code
114 * Prepare EC controller to boot to OS.
117 * @param[in] pConfig Southbridge configuration structure pointer.
125 AMDSBCFG* pTmp; // dummy code