7 * A sub-engine which extracts max. frequency limit value.
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/Ps)
12 * @e \$Revision: 52790 $ @e \$Date: 2011-05-11 15:31:24 -0600 (Wed, 11 May 2011) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
18 * All rights reserved.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are met:
22 * * Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
28 * its contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
37 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
38 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
40 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 * ***************************************************************************
46 *----------------------------------------------------------------------------
49 *----------------------------------------------------------------------------
55 #include "AdvancedApi.h"
58 #include "cpuFamRegisters.h"
59 #include "cpuRegisters.h"
60 #include "OptionMemory.h"
61 #include "PlatformMemoryConfiguration.h"
65 #include "GeneralServices.h"
69 #define FILECODE PROC_MEM_PS_MPMAXFREQ_FILECODE
72 /*----------------------------------------------------------------------------
73 * DEFINITIONS AND MACROS
75 *----------------------------------------------------------------------------
78 /*----------------------------------------------------------------------------
79 * TYPEDEFS AND STRUCTURES
81 *----------------------------------------------------------------------------
96 /*----------------------------------------------------------------------------
97 * PROTOTYPES OF LOCAL FUNCTIONS
99 *----------------------------------------------------------------------------
102 MemPGetMaxFreqSupported (
103 IN OUT MEM_NB_BLOCK *NBPtr,
104 IN MEM_PSC_TABLE_BLOCK *EntryOfTables
107 /*----------------------------------------------------------------------------
110 *----------------------------------------------------------------------------
113 /* -----------------------------------------------------------------------------*/
116 * A sub-function which extracts the value of max frequency supported from a input table and
117 * compares it with DCTPtr->Timings.TargetSpeed
119 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
120 * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK
122 * @return TRUE - Succeed in extracting the table value
123 * @return FALSE - Fail to extract the table value
127 MemPGetMaxFreqSupported (
128 IN OUT MEM_NB_BLOCK *NBPtr,
129 IN MEM_PSC_TABLE_BLOCK *EntryOfTables
138 UINT16 MaxFreqSupported;
141 UINT8 CurrentVoltage;
143 CPU_LOGICAL_ID LogicalCpuid;
145 PSCFG_MAXFREQ_ENTRY *TblPtr;
146 CH_DEF_STRUCT *CurrentChannel;
148 UINT8 PsoMaskMaxFreq;
149 UINT16 PsoMaskMaxFreq16;
150 PSC_TBL_ENTRY **TblEntryOfMaxFreq;
152 CurrentChannel = NBPtr->ChannelPtr;
155 Type = PSCFG_MAXFREQ;
159 LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
162 MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
163 NOD = (UINT8) 1 << (MaxDimmPerCh - 1);
165 if (CurrentChannel->RegDimmPresent != 0) {
166 DimmType = RDIMM_TYPE;
167 } else if (CurrentChannel->SODimmPresent != 0) {
168 DimmType = SODIMM_TYPE;
169 if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) {
170 DimmType = SODWN_SODIMM_TYPE;
172 } else if (CurrentChannel->LrDimmPresent != 0) {
173 DimmType = LRDIMM_TYPE;
175 DimmType = UDIMM_TYPE;
178 TblEntryOfMaxFreq = EntryOfTables->TblEntryOfMaxFreq;
179 IDS_OPTION_HOOK (IDS_GET_STRETCH_FREQUENCY_LIMIT, &TblEntryOfMaxFreq, &NBPtr->MemPtr->StdHeader);
182 // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type.
183 while (TblEntryOfMaxFreq[i] != NULL) {
184 if (((TblEntryOfMaxFreq[i])->Header.DimmType & DimmType) != 0) {
185 if (((TblEntryOfMaxFreq[i])->Header.NumOfDimm & NOD) != 0) {
187 // Determine if this is the expected NB Type
189 LogicalCpuid = (TblEntryOfMaxFreq[i])->Header.LogicalCpuid;
190 PackageType = (TblEntryOfMaxFreq[i])->Header.PackageType;
191 if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
192 TblPtr = (PSCFG_MAXFREQ_ENTRY *) ((TblEntryOfMaxFreq[i])->TBLPtr);
193 TableSize = (TblEntryOfMaxFreq[i])->TableSize;
194 Type = (TblEntryOfMaxFreq[i])->Header.PSCType;
202 // Check whether no table entry is found.
203 if (TblEntryOfMaxFreq[i] == NULL) {
204 IDS_HDT_CONSOLE (MEM_FLOW, "\nDCT %d: No MaxFreq table. This channel will be disabled.\n", NBPtr->Dct);
208 MaxFreqSupported = UNSUPPORTED_DDR_FREQUENCY;
210 DDR3Voltage = (UINT8) CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage);
212 // Construct the condition value
213 ((CDNMaxFreq *)&CDN)->DimmPerCh = MaxDimmPerCh;
214 ((CDNMaxFreq *)&CDN)->Dimms = CurrentChannel->Dimms;
215 if (Type == PSCFG_MAXFREQ) {
216 for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
217 if ((CurrentChannel->DimmSRPresent & (UINT8) (1 << i)) != 0) {
218 ((CDNMaxFreq *)&CDN)->SR += 1;
220 if ((CurrentChannel->DimmDrPresent & (UINT16) (1 << i)) != 0) {
221 ((CDNMaxFreq *)&CDN)->DR += 1;
223 if ((CurrentChannel->DimmQrPresent & (UINT16) (1 << i)) != 0) {
225 ((CDNMaxFreq *)&CDN)->QR += 1;
230 ((CDNLMaxFreq *)&CDN)->LR = CurrentChannel->Dimms;
233 for (i = 0; i < TableSize; i++) {
234 if (CDN == ((Type == PSCFG_MAXFREQ) ? TblPtr->MAXFREQ_ENTRY.CDN :
235 ((PSCFG_LR_MAXFREQ_ENTRY *)TblPtr)->LR_MAXFREQ_ENTRY.CDN)) {
236 if (Type == PSCFG_MAXFREQ) {
237 SpeedArray = TblPtr->MAXFREQ_ENTRY.Speed;
239 SpeedArray = ((PSCFG_LR_MAXFREQ_ENTRY *)TblPtr)->LR_MAXFREQ_ENTRY.Speed;
246 PsoMaskMaxFreq16 = MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_SPEEDLIMIT);
247 if ((PsoMaskMaxFreq16 & INVALID_CONFIG_FLAG) == 0) {
248 PsoMaskMaxFreq = (UINT8) PsoMaskMaxFreq16;
249 if (PsoMaskMaxFreq != 0) {
250 SpeedArray = NBPtr->PsPtr->SpeedLimit;
256 if (SpeedArray != NULL) {
257 if (NBPtr->SharedPtr->VoltageMap != VDDIO_DETERMINED) {
258 IDS_HDT_CONSOLE (MEM_FLOW, "\nCheck speed supported for each VDDIO for Node%d DCT%d: ", NBPtr->Node, NBPtr->Dct);
259 for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) {
260 if (NBPtr->SharedPtr->VoltageMap & (1 << CurrentVoltage)) {
261 IDS_HDT_CONSOLE (MEM_FLOW, "%s -> %dMHz ", (CurrentVoltage == VOLT1_5_ENCODED_VAL) ? "1.5V" : ((CurrentVoltage == VOLT1_35_ENCODED_VAL) ? "1.35V" : "1.25V"), SpeedArray[CurrentVoltage]);
262 if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedArray[CurrentVoltage]) {
263 MaxFreqSupported = SpeedArray[CurrentVoltage];
265 MaxFreqSupported = NBPtr->DCTPtr->Timings.TargetSpeed;
267 if (NBPtr->MaxFreqVDDIO[CurrentVoltage] > MaxFreqSupported) {
268 NBPtr->MaxFreqVDDIO[CurrentVoltage] = MaxFreqSupported;
271 NBPtr->MaxFreqVDDIO[CurrentVoltage] = 0;
274 IDS_HDT_CONSOLE (MEM_FLOW, "\n");
276 ASSERT (DDR3Voltage <= VOLT1_25_ENCODED_VAL);
277 MaxFreqSupported = SpeedArray[DDR3Voltage];
280 if (MaxFreqSupported == UNSUPPORTED_DDR_FREQUENCY) {
281 // No entry in the table for current dimm population is found
282 IDS_HDT_CONSOLE (MEM_FLOW, "\nDCT %d: No entry is found in the Max Frequency table\n", NBPtr->Dct);
284 } else if (MaxFreqSupported != 0) {
285 if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxFreqSupported) {
286 NBPtr->DCTPtr->Timings.TargetSpeed = MaxFreqSupported;
288 } else if (NBPtr->SharedPtr->VoltageMap == VDDIO_DETERMINED) {
289 // Dimm population is not supported at current voltage
290 // Also if there is no performance optimization, disable the DCT
295 NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
296 PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
297 SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
298 // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
299 NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;