7 * Common Northbridge initializer flow for MCT and DCT
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/NB)
12 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
18 * All rights reserved.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are met:
22 * * Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
28 * its contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
37 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
38 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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40 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 * ***************************************************************************
47 *----------------------------------------------------------------------------
50 *----------------------------------------------------------------------------
58 #include "OptionMemory.h"
66 #define FILECODE PROC_MEM_NB_MNFLOW_FILECODE
70 extern MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[];
71 /*----------------------------------------------------------------------------
72 * DEFINITIONS AND MACROS
74 *----------------------------------------------------------------------------
77 /*----------------------------------------------------------------------------
78 * TYPEDEFS AND STRUCTURES
80 *----------------------------------------------------------------------------
83 /*----------------------------------------------------------------------------
84 * PROTOTYPES OF LOCAL FUNCTIONS
86 *----------------------------------------------------------------------------
92 IN OUT MEM_NB_BLOCK *NBPtr
97 MemNCleanupDctRegsNb (
98 IN OUT MEM_NB_BLOCK *NBPtr
103 MemNGetPORFreqLimitTblDrvNb (
104 IN OUT MEM_NB_BLOCK *NBPtr
106 /*----------------------------------------------------------------------------
109 *----------------------------------------------------------------------------
112 /* -----------------------------------------------------------------------------*/
116 * This function programs the MCT with initial values
119 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
121 * @return TRUE - AGESA_FATAL error did not occur (it is possible to have an Error that is not AGESA_SUCCESS)
122 * @return FALSE - AGESA_FATAL error occurred
127 IN OUT MEM_NB_BLOCK *NBPtr
130 MEM_TECH_BLOCK *TechPtr;
133 ID_INFO CallOutIdInfo;
135 TechPtr = NBPtr->TechPtr;
136 // Switch Tech functions for Nb
137 NBPtr->TechBlockSwitch (NBPtr);
138 // Start Memory controller initialization sequence
140 if (TechPtr->DimmPresence (TechPtr)) {
141 AGESA_TESTPOINT (TpProcMemPlatformSpecificInit, &(NBPtr->MemPtr->StdHeader));
142 if (NBPtr->MemNPlatformSpecificFormFactorInitNb (NBPtr)) {
143 AGESA_TESTPOINT (TpProcMemSpdTiming, &(NBPtr->MemPtr->StdHeader));
144 if (TechPtr->SpdCalcWidth (TechPtr)) {
145 AGESA_TESTPOINT (TpProcMemSpeedTclConfig, &(NBPtr->MemPtr->StdHeader));
146 if (TechPtr->SpdGetTargetSpeed (TechPtr)) {
147 for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
148 NBPtr->SwitchDCT (NBPtr, Dct);
150 Flag |= MemNInitDCTNb (NBPtr);
153 if (Flag && !NBPtr->IsSupported[TwoStageDramInit] && (NBPtr->MCTPtr->ErrCode != AGESA_FATAL)) {
154 MemFInitTableDrive (NBPtr, MTBeforeDInit);
155 AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader));
156 CallOutIdInfo.IdField.SocketId = NBPtr->MCTPtr->SocketId;
157 CallOutIdInfo.IdField.ModuleId = NBPtr->MCTPtr->DieId;
158 IDS_HDT_CONSOLE (MEM_FLOW, "\nCalling out to Platform BIOS on Socket %d Module %d...\n", CallOutIdInfo.IdField.SocketId, CallOutIdInfo.IdField.ModuleId);
159 AgesaHookBeforeDramInit ((UINTN) CallOutIdInfo.IdInformation, NBPtr->MemPtr);
160 IDS_HDT_CONSOLE (MEM_FLOW, "\nVDDIO = 1.%dV\n", (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) ? 5 :
161 (NBPtr->RefPtr->DDR3Voltage == VOLT1_35) ? 35 :
162 (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) ? 25 : 999);
163 AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader));
164 IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, NBPtr, &(NBPtr->MemPtr->StdHeader));
165 NBPtr->StartupDCT (NBPtr);
171 return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL);
174 /* -----------------------------------------------------------------------------*/
178 * This function initializes the platform specific block for families that support
179 * table driven form factor
182 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
184 * @return TRUE - AGESA_SUCCESS
188 MemNPlatformSpecificFormFactorInitTblDrvNb (
189 IN OUT MEM_NB_BLOCK *NBPtr
194 for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
195 NBPtr->SwitchDCT (NBPtr, Dct);
196 NBPtr->PsPtr->MemPDoPs = MemPPSCFlow;
197 NBPtr->PsPtr->MemPGetPORFreqLimit = MemNGetPORFreqLimitTblDrvNb;
198 NBPtr->PsPtr->MemPGetPass1Seeds = MemPGetPSCPass1Seed;
204 /* -----------------------------------------------------------------------------*/
207 * This function selects appropriate Tech functions for the NB.
209 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
214 MemNTechBlockSwitchNb (
215 IN OUT MEM_NB_BLOCK *NBPtr
218 MEM_TECH_BLOCK *TechPtr;
220 TechPtr = NBPtr->TechPtr;
222 // Specify Dimm-Byte training for Nb
223 MemTDimmByteTrainInit (TechPtr);
225 // Filter included for RcvrEn training.
226 // note: If you'd like to drop the filter, you have to comment out these two lines together.
227 TechPtr->MaxFilterDly = MAX_FILTER_DLY_DDR3;
228 TechPtr->SaveRcvrEnDly = MemTSaveRcvrEnDlyByteFilter;
231 /*----------------------------------------------------------------------------
234 *----------------------------------------------------------------------------
237 /* -----------------------------------------------------------------------------*/
241 * This function programs the DCT with initial values
244 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
246 * @return TRUE - Error did not occur
247 * @return FALSE - Error occurred
253 IN OUT MEM_NB_BLOCK *NBPtr
256 MEM_TECH_BLOCK *TechPtr;
257 TechPtr = NBPtr->TechPtr;
258 TechPtr->SetDramMode (TechPtr);
260 if (!NBPtr->MCTPtr->GangedMode || (NBPtr->MCTPtr->Dct == 0)) {
261 if (NBPtr->DCTPtr->Timings.DctDimmValid == 0) {
262 NBPtr->DisableDCT (NBPtr);
264 MemNCleanupDctRegsNb (NBPtr);
265 if (TechPtr->AutoCycTiming (TechPtr)) {
266 if (TechPtr->SpdSetBanks (TechPtr)) {
267 if (NBPtr->StitchMemory (NBPtr)) {
268 // if all dimms on a DCT are disabled, the DCT needs to be disabled.
269 if (NBPtr->DCTPtr->Timings.CsEnabled != 0) {
270 if (NBPtr->AutoConfig (NBPtr)) {
271 if (NBPtr->PlatformSpec (NBPtr)) {
276 NBPtr->DisableDCT (NBPtr);
286 /*-----------------------------------------------------------------------------*/
289 * This function clears DCT registers
290 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
296 MemNCleanupDctRegsNb (
297 IN OUT MEM_NB_BLOCK *NBPtr
300 BIT_FIELD_NAME BitField;
302 for (BitField = BFCSBaseAddr0Reg; BitField <= BFCSBaseAddr7Reg; BitField++) {
303 MemNSetBitFieldNb (NBPtr, BitField, 0);
307 /* -----------------------------------------------------------------------------*/
311 * This is function gets the POR speed limit for families supports table driven form factor
314 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
320 MemNGetPORFreqLimitTblDrvNb (
321 IN OUT MEM_NB_BLOCK *NBPtr
327 while (memPlatSpecFlowArray[i] != NULL) {
328 if ((memPlatSpecFlowArray[i])->MaxFrequency (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {