7 * Common Northbridge S3
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/NB)
12 * @e \$Revision: 51373 $ @e \$Date: 2011-04-21 13:10:59 -0600 (Thu, 21 Apr 2011) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
18 * All rights reserved.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are met:
22 * * Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
28 * its contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
37 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
38 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
40 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 * ***************************************************************************
47 *----------------------------------------------------------------------------
50 *----------------------------------------------------------------------------
54 #include "AdvancedApi.h"
57 #include "OptionMemory.h"
62 #include "cpuFamilyTranslation.h"
63 #include "heapManager.h"
68 #define FILECODE PROC_MEM_NB_MNS3_FILECODE
69 /*----------------------------------------------------------------------------
70 * DEFINITIONS AND MACROS
72 *----------------------------------------------------------------------------
75 /*----------------------------------------------------------------------------
76 * TYPEDEFS AND STRUCTURES
78 *----------------------------------------------------------------------------
81 /*----------------------------------------------------------------------------
82 * PROTOTYPES OF LOCAL FUNCTIONS
84 *----------------------------------------------------------------------------
88 MemNS3GetSetBitField (
89 IN ACCESS_WIDTH AccessWidth,
93 IN OUT VOID *ConfigPtr
98 MemNS3GetDummyReadAddr (
99 IN OUT MEM_NB_BLOCK *NBPtr,
102 /*----------------------------------------------------------------------------
105 *----------------------------------------------------------------------------
108 /* -----------------------------------------------------------------------------*/
112 * This function executes the S3 resume for a node
114 * @param[in,out] *S3NBPtr - Pointer to the S3_MEM_NB_BLOCK
115 * @param[in] NodeID - The Node id of the target die
118 * TRUE - This is the correct constructor for the targeted node.
119 * FALSE - This isn't the correct constructor for the targeted node.
124 IN OUT S3_MEM_NB_BLOCK *S3NBPtr,
132 MEM_DATA_STRUCT *MemPtr;
134 NBPtr = S3NBPtr->NBPtr;
135 MemPtr = NBPtr->MemPtr;
136 GangedEn = (MemNGetBitFieldNb (NBPtr, BFDctGangEn) == 1) ? TRUE : FALSE;
138 // Errata before S3 resume sequence
141 // 1. Program F2x[1,0]9C_x08[DisAutoComp]=1
142 MemNSwitchDCTNb (NBPtr, 0);
143 MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1);
145 // Program F2x[1, 0]94[MemClkFreqVal] = 1.
146 // 2. Wait for F2x[1,0]94[FreqChgInPrg]=0
147 for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
148 MemNSwitchDCTNb (NBPtr, DCT);
149 if ((MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) && !((DCT == 1) && GangedEn)) {
150 MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1);
151 while (MemNGetBitFieldNb (NBPtr, BFFreqChgInProg) != 0) {}
155 // Program F2x9C_x08[DisAutoComp]=0
156 MemNSwitchDCTNb (NBPtr, 0);
157 MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0);
158 // BIOS must wait 750 us for the phy compensation engine
160 MemFS3Wait10ns (75000, NBPtr->MemPtr);
162 // 3. Restore F2x[1,0]90_x00, F2x9C_x0A, and F2x[1,0]9C_x0C
163 // 4. Restore F2x[1,0]9C_x04
164 // Get the register value from the heap.
165 S3NBPtr->MemS3ExitSelfRefReg (NBPtr, &MemPtr->StdHeader);
168 AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader);
169 if (AgesaHookBeforeExitSelfRefresh (0, MemPtr) == AGESA_SUCCESS) {
171 AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader);
173 // 5. Set F2x[1,0]90[ExitSelfRef]
174 // 6. Wait for F2x[1,0]90[ExitSelfRef]=0
175 for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
176 MemNSwitchDCTNb (NBPtr, DCT);
177 if ((MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) && !((DCT == 1) && GangedEn)) {
178 MemNSetBitFieldNb (NBPtr, BFExitSelfRef, 1);
179 while (MemNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {}
181 if ((MemNGetBitFieldNb (NBPtr, BFMemClkFreq) == DDR1333_FREQUENCY) && (NBPtr->IsSupported[CheckDllSpeedUp])) {
182 MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F11, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F11) | 0x2000));
183 MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F10, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F10) | 0x2000));
184 MemNSetBitFieldNb (NBPtr, BFPhy0x0D088F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D088F30) | 0x2000));
185 MemNSetBitFieldNb (NBPtr, BFPhy0x0D08C030, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D08C030) | 0x2000));
187 MemNSetBitFieldNb (NBPtr, BFPhy0x0D082F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D082F30) | 0x2000));
189 // NOTE: wait 512 clocks for DLL-relock
190 MemFS3Wait10ns (50000, NBPtr->MemPtr); // wait 500us
194 // Errata After S3 resume sequence
196 for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
197 MemNSwitchDCTNb (NBPtr, DCT);
198 if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) {
199 if (!((DCT == 1) && GangedEn)) {
200 if (MemNS3GetDummyReadAddr (NBPtr, &TestAddr)) {
202 Read64Mem8 (TestAddr);
203 // Flush the cache line
204 LibAmdCLFlush (TestAddr, 1);
207 MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000);
208 MemFS3Wait10ns (60, NBPtr->MemPtr); // Wait 300ns
209 MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000);
210 MemFS3Wait10ns (400, NBPtr->MemPtr); // Wait 2us
217 /* -----------------------------------------------------------------------------*/
221 * This function executes the S3 resume for a node on a client NB
223 * @param[in,out] *S3NBPtr - Pointer to the S3_MEM_NB_BLOCK
224 * @param[in] NodeID - The Node id of the target die
227 * TRUE - This is the correct constructor for the targeted node.
228 * FALSE - This isn't the correct constructor for the targeted node.
231 MemNS3ResumeClientNb (
232 IN OUT S3_MEM_NB_BLOCK *S3NBPtr,
238 MEM_DATA_STRUCT *MemPtr;
240 NBPtr = S3NBPtr->NBPtr;
241 MemPtr = NBPtr->MemPtr;
243 // Errata before S3 resume sequence
246 AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader);
247 if (AgesaHookBeforeExitSelfRefresh (0, MemPtr) == AGESA_SUCCESS) {
249 AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader);
251 NBPtr->ChangeNbFrequencyWrap (NBPtr, 0);
252 //Override the NB Pstate if needed
253 IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, S3NBPtr->NBPtr, &MemPtr->StdHeader);
254 // Set F2x[1,0]90[ExitSelfRef]
255 // Wait for F2x[1,0]90[ExitSelfRef]=0
256 for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
257 MemNSwitchDCTNb (NBPtr, DCT);
258 if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) {
259 MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1);
260 MemNSetBitFieldNb (NBPtr, BFExitSelfRef, 1);
261 while (MemNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {}
262 MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0);
266 // Errata After S3 resume sequence
269 /* -----------------------------------------------------------------------------*/
273 * This function executes the S3 resume for a node on a UNB
275 * @param[in,out] *S3NBPtr - Pointer to the S3_MEM_NB_BLOCK
276 * @param[in] NodeID - The Node id of the target die
279 * TRUE - This is the correct constructor for the targeted node.
280 * FALSE - This isn't the correct constructor for the targeted node.
284 IN OUT S3_MEM_NB_BLOCK *S3NBPtr,
290 MEM_DATA_STRUCT *MemPtr;
292 NBPtr = S3NBPtr->NBPtr;
293 MemPtr = NBPtr->MemPtr;
295 // Errata before S3 resume sequence
298 AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader);
299 if (AgesaHookBeforeExitSelfRefresh (0, MemPtr) == AGESA_SUCCESS) {
301 AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader);
303 //Override the NB Pstate if needed
304 IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, S3NBPtr->NBPtr, &MemPtr->StdHeader);
305 // Set F2x[1,0]90[ExitSelfRef]
306 // Wait for F2x[1,0]90[ExitSelfRef]=0
307 for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
308 MemNSwitchDCTNb (NBPtr, DCT);
309 if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) {
310 MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1);
311 MemNSetBitFieldNb (NBPtr, BFExitSelfRef, 1);
312 while (MemNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {}
313 if (NBPtr->IsSupported[SetDllShutDown]) {
314 MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0);
319 // Errata After S3 resume sequence
323 /* -----------------------------------------------------------------------------*/
327 * This function returns the conditional PCI device mask
329 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
330 * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP
334 MemNS3GetConPCIMaskNb (
335 IN OUT MEM_NB_BLOCK *NBPtr,
336 IN OUT DESCRIPTOR_GROUP *DescriptPtr
339 BIT_FIELD_NAME bitfield;
350 for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
351 NBPtr->SwitchDCT (NBPtr, DCT);
352 if (MemNGetBitFieldNb (NBPtr, BFMemClkFreqVal)) {
353 if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) {
356 for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr7Reg; bitfield ++) {
357 RegVal = MemNGetBitFieldNb (NBPtr, bitfield);
359 DimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT));
360 } else if (RegVal & 0x4) {
361 BadDimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT));
367 NBPtr->SwitchDCT (NBPtr, 0);
368 DctGangEn = (UINT8) MemNGetBitFieldNb (NBPtr, BFDctGangEn);
370 DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 0;
371 DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 0;
372 for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
373 if (DimmMask & (0x55 << DCT)) {
374 // Set mask before exit self refresh
375 DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT;
376 // Set mask after exit self refresh
377 DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 1 << DCT;
378 // Set DDR3 mask if Dimms present are DDR3
380 DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 << 4);
382 } else if (BadDimmMask & (0x55 << DCT)) {
383 // Need to save function 2 registers for bad dimm
384 DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT;
389 DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask;
390 DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask;
392 // Need to set channel mask bit to 1 on DCT1 in ganged mode as some registers
393 // need to be restored on both channels in ganged mode
394 DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 2;
395 DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 2;
397 DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= (2 << 4);
398 DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (2 << 4);
400 // Before exit self refresh, do not copy dimm mask to DCT1 as registers restored
401 // in that time frame don't care about individual dimm population. We want to
402 // skip registers that are not needed to be restored for DCT1 in ganged mode.
404 // After exit self refresh, training registers will be restored and will only be
405 // restored for slots which have dimms on it. So dimm mask needs to be copied to DCT1.
407 DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 |= DimmMask << 1;
410 // Adjust the mask if there is no dimm on the node
411 if ((DescriptPtr->CPCIDevice[PRESELFREF].Mask2 == 0) &&
412 (DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 == 0)) {
413 DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK;
414 DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK;
418 /* -----------------------------------------------------------------------------*/
422 * This function returns the conditional PCI device mask
424 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
425 * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP
429 MemNS3GetConPCIMaskUnb (
430 IN OUT MEM_NB_BLOCK *NBPtr,
431 IN OUT DESCRIPTOR_GROUP *DescriptPtr
434 BIT_FIELD_NAME bitfield;
443 for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
444 MemNSwitchDCTNb (NBPtr, DCT);
445 if (MemNGetBitFieldNb (NBPtr, BFMemClkFreqVal)) {
446 for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr7Reg; bitfield ++) {
447 RegVal = MemNGetBitFieldNb (NBPtr, bitfield);
449 DimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT));
450 } else if (RegVal & 0x4) {
451 BadDimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT));
456 // Check if the system is capable of doing NB Pstate change
457 NbPsCap = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPstateDis);
459 MemNSwitchDCTNb (NBPtr, 0);
461 DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 0;
462 DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 0;
463 for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
464 if (DimmMask & (0x55 << DCT)) {
465 // Set mask before exit self refresh
466 DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= ((NbPsCap == 0) ? 5 : 1) << DCT;
467 // Set mask after exit self refresh
468 DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 1 << DCT;
469 // Set DDR3 mask if Dimms present are DDR3
470 DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 << 4);
471 } else if (BadDimmMask & (0x55 << DCT)) {
472 // Need to save function 2 registers for bad dimm
473 DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT;
478 DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask;
479 DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask;
481 // Adjust the mask if there is no dimm on the node
482 if ((DescriptPtr->CPCIDevice[PRESELFREF].Mask2 == 0) &&
483 (DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 == 0)) {
484 DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK;
485 DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK;
489 /* -----------------------------------------------------------------------------*/
493 * This function read the value of CSR register.
495 * @param[in] AccessWidth - Access width of the register
496 * @param[in] Address - address of the CSR register in PCI_ADDR format.
497 * @param[in] *Value - Pointer to the value be read.
498 * @param[in, out] *ConfigPtr - Pointer to Config handle.
503 IN ACCESS_WIDTH AccessWidth,
506 IN OUT VOID *ConfigPtr
514 ExtendOffset = Address.Address.Register;
515 if (ExtendOffset & 0x800) {
516 Address.Address.Register = 0xF0;
519 Address.Address.Register = 0x98;
522 if (ExtendOffset & 0x400) {
523 Address.Address.Register |= 0x100;
525 ExtendOffset &= 0x3FF;
526 LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr);
527 while (((ValueRead >> 31) & 1) == 0) {
528 LibAmdPciRead (AccessS3SaveWidth32, Address, &ValueRead, ConfigPtr);
530 Address.Address.Register = (Address.Address.Register & 0xF00) | DataPort;
531 LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr);
535 /* -----------------------------------------------------------------------------*/
539 * This function write to a CSR register
541 * @param[in] AccessWidth - Access width of the register
542 * @param[in] Address - address of the CSR register in PCI_ADDR format.
543 * @param[in, out] *Value - Pointer to the value be read.
544 * @param[in, out] *ConfigPtr - Pointer to Config handle.
549 IN ACCESS_WIDTH AccessWidth,
552 IN OUT VOID *ConfigPtr
561 ExtendOffset = Address.Address.Register;
562 // Check the flag and see the type of the access
563 if (ExtendOffset & 0x800) {
564 Address.Address.Register = 0xF4;
567 Address.Address.Register = 0x9C;
570 if (ExtendOffset & 0x400) {
571 Address.Address.Register |= 0x100;
573 ExtendOffset &= 0x3FF;
574 ExtendOffset |= 0x40000000;
575 switch (AccessWidth) {
576 case AccessS3SaveWidth8:
577 ValueWrite = *(UINT8 *) Value;
579 case AccessS3SaveWidth16:
580 ValueWrite = *(UINT16 *) Value;
582 case AccessS3SaveWidth32:
583 ValueWrite = *(UINT32 *) Value;
588 LibAmdPciWrite (AccessS3SaveWidth32, Address, &ValueWrite, ConfigPtr);
589 Address.Address.Register = (Address.Address.Register & 0xF00) | DataOffset;
590 LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr);
591 while (((ValueRead >> 31) & 1) == 0) {
592 LibAmdPciRead (AccessS3SaveWidth32, Address, &ValueRead, ConfigPtr);
596 /* -----------------------------------------------------------------------------*/
600 * This function reads register bitfield
602 * @param[in] AccessWidth - Access width of the register
603 * @param[in] Address - address of the CSR register in PCI_ADDR format.
604 * @param[in, out] *Value - Pointer to the value be read.
605 * @param[in, out] *ConfigPtr - Pointer to Config handle.
609 MemNS3GetBitFieldNb (
610 IN ACCESS_WIDTH AccessWidth,
613 IN OUT VOID *ConfigPtr
616 MemNS3GetSetBitField (AccessWidth, Address, FALSE, Value, ConfigPtr);
619 /* -----------------------------------------------------------------------------*/
623 * This function writes register bitfield
625 * @param[in] AccessWidth - Access width of the register
626 * @param[in] Address - address of the CSR register in PCI_ADDR format.
627 * @param[in, out] *Value - Pointer to the value to be written.
628 * @param[in, out] *ConfigPtr - Pointer to Config handle.
632 MemNS3SetBitFieldNb (
633 IN ACCESS_WIDTH AccessWidth,
636 IN OUT VOID *ConfigPtr
639 MemNS3GetSetBitField (AccessWidth, Address, TRUE, Value, ConfigPtr);
642 /* -----------------------------------------------------------------------------*/
646 * This function restores scrubber base register
648 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
649 * @param[in] Node - The Node id of the target die
653 MemNS3RestoreScrubNb (
654 IN OUT MEM_NB_BLOCK *NBPtr,
658 UINT32 ScrubAddrRJ16;
660 ScrubAddrRJ16 = (MemNGetBitFieldNb (NBPtr, BFDramBaseReg0 + Node) & 0xFFFF0000) >> 8;
661 ScrubAddrRJ16 |= MemNGetBitFieldNb (NBPtr, BFDramBaseHiReg0 + Node) << 24;
662 MemNSetBitFieldNb (NBPtr, BFScrubAddrLoReg, ScrubAddrRJ16 << 16);
663 MemNSetBitFieldNb (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16);
666 /* -----------------------------------------------------------------------------*/
670 * This function disable NB Pstate Debug.
672 * @param[in] AccessWidth - Access width of the register.
673 * @param[in] Address - address in PCI_ADDR format.
674 * @param[in, out] *Value - Pointer to the value to be written.
675 * @param[in, out] *ConfigPtr - Pointer to Config handle.
680 IN ACCESS_WIDTH AccessWidth,
683 IN OUT VOID *ConfigPtr
688 LibAmdPciRead (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr);
689 // Clear NbPsDbgEn and NbPsCsrAccSel
690 if ((RegValue & 0xC0000000) != 0) {
691 RegValue &= 0x3FFFFFFF;
692 LibAmdPciWrite (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr);
696 /* -----------------------------------------------------------------------------*/
700 * This function that enable NB Pstate debug register to allow access to NB Pstate
701 * 1 registers without actually changing NB Pstate.
703 * @param[in] AccessWidth - Access width of the register.
704 * @param[in] Address - address in PCI_ADDR format.
705 * @param[in, out] *Value - Pointer to the value to be written.
706 * @param[in, out] *ConfigPtr - Pointer to Config handle.
711 IN ACCESS_WIDTH AccessWidth,
714 IN OUT VOID *ConfigPtr
719 LibAmdPciRead (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr);
720 // Set NbPsDbgEn to 1 and NbPsCsrAccSel to 1
721 if ((RegValue & 0xC0000000) != 0xC0000000) {
722 RegValue = (*(UINT32 *)Value & 0x3FFFFFFF) | 0xC0000000;
723 LibAmdPciWrite (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr);
727 /* -----------------------------------------------------------------------------*/
731 * This function sets bit 31 [DynModeChange] of F2x9C_xB
733 * @param[in] AccessWidth - Access width of the register.
734 * @param[in] Address - address in PCI_ADDR format.
735 * @param[in, out] *Value - Pointer to the value to be written.
736 * @param[in, out] *ConfigPtr - Pointer to Config handle.
740 MemNS3SetDynModeChangeNb (
741 IN ACCESS_WIDTH AccessWidth,
744 IN OUT VOID *ConfigPtr
749 RegValue = 0x80000000;
750 IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) {
751 MemNS3SetCSRNb (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr);
755 /* -----------------------------------------------------------------------------*/
759 * This function does the channel disable sequence
761 * @param[in] AccessWidth - Access width of the register.
762 * @param[in] Address - address in PCI_ADDR format.
763 * @param[in, out] *Value - Pointer to the value to be written.
764 * @param[in, out] *ConfigPtr - Pointer to Config handle.
768 MemNS3DisableChannelNb (
769 IN ACCESS_WIDTH AccessWidth,
772 IN OUT VOID *ConfigPtr
776 LOCATE_HEAP_PTR LocateBufferPtr;
777 S3_MEM_NB_BLOCK *S3NBPtr;
781 // See which Node should be accessed
782 Die = (UINT8) (Address.Address.Device - 24);
784 LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE;
785 if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
786 S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr;
787 NBPtr = S3NBPtr[Die].NBPtr;
789 // Function field contains the DCT number
790 NBPtr->SwitchDCT (NBPtr, (UINT8) Address.Address.Function);
791 RegValue = MemNGetBitFieldNb (NBPtr, BFCKETri);
792 // if CKETri is 0b11, this channel is disabled
794 //Wait for 24 MEMCLKs, which is 60ns under 400MHz
795 MemFS3Wait10ns (6, NBPtr->MemPtr);
796 MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF);
797 MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
798 MemNSetBitFieldNb (NBPtr, BFDramPhyStatusReg, 0x80800000);
803 /* -----------------------------------------------------------------------------*/
807 * This function disables auto compensation.
809 * @param[in] AccessWidth - Access width of the register.
810 * @param[in] Address - address in PCI_ADDR format.
811 * @param[in, out] *Value - Pointer to the value to be written.
812 * @param[in, out] *ConfigPtr - Pointer to Config handle.
816 MemNS3SetDisAutoCompUnb (
817 IN ACCESS_WIDTH AccessWidth,
820 IN OUT VOID *ConfigPtr
825 MemNS3GetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
826 RegValue = 0x6000 | RegValue;
827 MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
830 /* -----------------------------------------------------------------------------*/
834 * This function retores Pre Driver Calibration with pre driver calibration code
835 * code valid bit set.
837 * @param[in] AccessWidth - Access width of the register.
838 * @param[in] Address - address in PCI_ADDR format.
839 * @param[in, out] *Value - Pointer to the value to be written.
840 * @param[in, out] *ConfigPtr - Pointer to Config handle.
844 MemNS3SetPreDriverCalUnb (
845 IN ACCESS_WIDTH AccessWidth,
848 IN OUT VOID *ConfigPtr
853 RegValue = 0x8000 | *(UINT16 *) Value;
854 MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
857 /* -----------------------------------------------------------------------------*/
860 * This function is used by families that use a separate DctCfgSel bit to
861 * select the current DCT which will be accessed by function 2.
862 * NOTE: This function must be called BEFORE the NBPtr->Dct variable is
865 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
866 * @param[in] *Dct - Pointer to ID of the target DCT
871 MemNS3DctCfgSelectUnb (
872 IN OUT MEM_NB_BLOCK *NBPtr,
876 // Set the DctCfgSel to new DCT
878 MemNSetBitFieldNb (NBPtr, BFDctCfgSel, *(UINT8*)Dct);
883 /* -----------------------------------------------------------------------------*/
887 * This function write to a register that has one copy for each NB Pstate
889 * @param[in] AccessWidth - Access width of the register
890 * @param[in] Address - address of the CSR register in PCI_ADDR format.
891 * @param[in, out] *Value - Pointer to the value be read.
892 * @param[in, out] *ConfigPtr - Pointer to Config handle.
896 MemNS3GetNBPStateDepRegUnb (
897 IN ACCESS_WIDTH AccessWidth,
900 IN OUT VOID *ConfigPtr
908 Temp = Address.Address.Register;
909 NBPstate = (UINT8) (Temp >> 10);
910 Dct = (UINT8) Address.Address.Function;
914 // Function field contains DCT value
915 Address.Address.Function = FUNC_1;
916 Address.Address.Register = 0x10C;
917 LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
918 TempValue = (TempValue & 0xCE) | ((NBPstate << 4) | Dct);
919 LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
921 Address.Address.Function = FUNC_2;
922 Address.Address.Register = Temp;
923 LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr);
925 Address.Address.Function = FUNC_1;
926 Address.Address.Register = 0x10C;
928 LibAmdPciWrite (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr);
931 /* -----------------------------------------------------------------------------*/
935 * This function write to a register that has one copy for each NB Pstate
937 * @param[in] AccessWidth - Access width of the register
938 * @param[in] Address - address of the CSR register in PCI_ADDR format.
939 * @param[in, out] *Value - Pointer to the value be read.
940 * @param[in, out] *ConfigPtr - Pointer to Config handle.
944 MemNS3SetNBPStateDepRegUnb (
945 IN ACCESS_WIDTH AccessWidth,
948 IN OUT VOID *ConfigPtr
956 Temp = Address.Address.Register;
957 NBPstate = (UINT8) (Temp >> 10);
958 Dct = (UINT8) Address.Address.Function;
962 // Function field contains DCT value
963 Address.Address.Function = FUNC_1;
964 Address.Address.Register = 0x10C;
965 LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
966 TempValue = (TempValue & 0xCE) | ((NBPstate << 4) | Dct);
967 LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
969 Address.Address.Function = FUNC_2;
970 Address.Address.Register = Temp;
971 LibAmdPciWrite (AccessWidth, Address, Value, ConfigPtr);
973 Address.Address.Function = FUNC_1;
974 Address.Address.Register = 0x10C;
976 LibAmdPciWrite (AccessS3SaveWidth32, Address, &TempValue, ConfigPtr);
979 /* -----------------------------------------------------------------------------*/
983 * This function read the value of Function 2 PCI register.
985 * @param[in] AccessWidth - Access width of the register
986 * @param[in] Address - address of the NB register in PCI_ADDR format.
987 * @param[in] *Value - Pointer to the value be read.
988 * @param[in, out] *ConfigPtr - Pointer to Config handle.
992 MemNS3SaveNBRegiserUnb (
993 IN ACCESS_WIDTH AccessWidth,
996 IN OUT VOID *ConfigPtr
1003 Temp = Address.Address.Register;
1004 Dct = (UINT8) Address.Address.Function;
1007 // Function field contains DCT value
1008 Address.Address.Function = FUNC_1;
1009 Address.Address.Register = 0x10C;
1010 LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
1011 TempValue = (TempValue & 0xFE) | Dct;
1012 LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
1014 Address.Address.Register = Temp;
1015 Address.Address.Function = FUNC_2;
1016 LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr);
1019 /* -----------------------------------------------------------------------------*/
1023 * This function set the value of Function 2 PCI register.
1025 * @param[in] AccessWidth - Access width of the register
1026 * @param[in] Address - address of the NB register in PCI_ADDR format.
1027 * @param[in] *Value - Pointer to the value be write.
1028 * @param[in, out] *ConfigPtr - Pointer to Config handle.
1032 MemNS3RestoreNBRegiserUnb (
1033 IN ACCESS_WIDTH AccessWidth,
1034 IN PCI_ADDR Address,
1036 IN OUT VOID *ConfigPtr
1043 Temp = Address.Address.Register;
1044 Dct = (UINT8) Address.Address.Function;
1047 // Function field contains DCT value
1048 Address.Address.Function = FUNC_1;
1049 Address.Address.Register = 0x10C;
1050 LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
1051 TempValue = (TempValue & 0xFE) | Dct;
1052 LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr);
1054 Address.Address.Register = Temp;
1055 Address.Address.Function = FUNC_2;
1056 LibAmdPciWrite (AccessWidth, Address, Value, ConfigPtr);
1059 /*----------------------------------------------------------------------------
1062 *----------------------------------------------------------------------------*/
1064 /* -----------------------------------------------------------------------------*/
1068 * This function reads and writes register bitfield
1070 * @param[in] AccessWidth - Access width of the register
1071 * @param[in] Address - address of the CSR register in PCI_ADDR format.
1072 * @param[in] IsSet - if this is a register read or write
1073 * @param[in, out] *Value - Pointer to the value be read or written.
1074 * @param[in, out] *ConfigPtr - Pointer to Config handle.
1079 MemNS3GetSetBitField (
1080 IN ACCESS_WIDTH AccessWidth,
1081 IN PCI_ADDR Address,
1084 IN OUT VOID *ConfigPtr
1087 BIT_FIELD_NAME BitField;
1088 MEM_NB_BLOCK *NBPtr;
1089 LOCATE_HEAP_PTR LocateBufferPtr;
1090 S3_MEM_NB_BLOCK *S3NBPtr;
1095 // See which Node should be accessed
1096 Die = (UINT8) (Address.Address.Device - 24);
1098 LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE;
1099 if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
1100 S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr;
1101 NBPtr = S3NBPtr[Die].NBPtr;
1103 // Function field contains the DCT number
1104 NBPtr->SwitchDCT (NBPtr, (UINT8) Address.Address.Function);
1106 // Get the bitfield name to be accessed
1107 // Register field contains the bitfield name
1108 BitField = (BIT_FIELD_NAME) Address.Address.Register;
1111 switch (AccessWidth) {
1112 case AccessS3SaveWidth8:
1113 RegValue = *(UINT8 *) Value;
1115 case AccessS3SaveWidth16:
1116 RegValue = *(UINT16 *) Value;
1118 case AccessS3SaveWidth32:
1119 RegValue = *(UINT32 *) Value;
1124 MemNSetBitFieldNb (NBPtr, BitField, RegValue);
1126 RegValue = MemNGetBitFieldNb (NBPtr, BitField);
1128 switch (AccessWidth) {
1129 case AccessS3SaveWidth8:
1130 *(UINT8 *) Value = (UINT8) RegValue;
1132 case AccessS3SaveWidth16:
1133 *(UINT16 *) Value = (UINT16) RegValue;
1135 case AccessS3SaveWidth32:
1136 *(UINT32 *) Value = RegValue;
1147 /* -----------------------------------------------------------------------------*/
1151 * This function gets the dummy read address for a channel of a node.
1153 * @param[in, out] *NBPtr - Pointer to northbridge block
1154 * @param[out] *TestAddr - Pointer to the test address
1156 * @retval TRUE - Dummy read address can be found
1157 * @retval FALSE - Dummy read address cannot be found
1162 MemNS3GetDummyReadAddr (
1163 IN OUT MEM_NB_BLOCK *NBPtr,
1164 OUT UINT64 *TestAddr
1167 BOOLEAN DctSelIntlvEn;
1169 UINT8 DctSelIntlvAddr;
1170 UINT8 IntLvRgnBaseAddr;
1171 UINT8 IntLvRgnLmtAddr;
1173 UINT32 DctSelBaseAddr;
1178 // Check if Node interleaving is enabled
1179 DramIntlvEn = (UINT8) MemNGetBitFieldNb (NBPtr, BFDramIntlvEn);
1180 if (DramIntlvEn != 0) {
1181 // Set the address bits that identify the node
1182 *TestAddr = (UINT64) MemNGetBitFieldNb (NBPtr, BFDramIntlvSel) << 12;
1184 *TestAddr = (UINT64) MemNGetBitFieldNb (NBPtr, BFDramBaseAddr) << 27;
1187 // Check if channel interleaving is enabled
1188 DctSelIntlvEn = (BOOLEAN) MemNGetBitFieldNb (NBPtr, BFDctSelIntLvEn);
1189 DctSelBaseAddr = MemNGetBitFieldNb (NBPtr, BFDctSelBaseAddr);
1190 if (!DctSelIntlvEn) {
1191 if ((NBPtr->Dct == 1) && ((UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelHi) == 1)) {
1192 *TestAddr = ((UINT64) DctSelBaseAddr << 27) | (*TestAddr & 0xFFFFFFF);
1195 DctSelIntlvAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelIntLvAddr);
1196 // Set the address bits that identify the channel
1197 if ((DctSelIntlvAddr == 0) || (DctSelIntlvAddr == 2)) {
1198 *TestAddr |= (UINT64) NBPtr->Dct << 6;
1199 } else if (DctSelIntlvAddr == 1) {
1200 *TestAddr |= (UINT64) NBPtr->Dct << (12 + LibAmdBitScanReverse (DramIntlvEn + 1));
1201 } else if (DctSelIntlvAddr == 3) {
1202 *TestAddr |= (UINT64) NBPtr->Dct << 9;
1205 // Adding 2M to avoid conflict
1206 *TestAddr += 0x200000;
1208 // If memory hoisting is disabled, the address can fall into MMIO area
1209 // Need to find an address out of MMIO area but belongs to the channel
1210 // If the whole channel is in MMIO, then do not do dummy read.
1212 LibAmdMsrRead (TOP_MEM, &TOM, &NBPtr->MemPtr->StdHeader);
1213 if ((*TestAddr >= TOM) && (*TestAddr < ((UINT64) _4GB_RJ16 << 16))) {
1214 if ((NBPtr->Dct == 1) && ((UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelHi) == 1)) {
1215 // This is the DCT that goes to high address range
1216 if (DctSelBaseAddr >= (_4GB_RJ16 >> (27 - 16))) {
1217 // When DctSelBaseAddr is higher than 4G, choose DctSelBaseAddr as the dummy read addr
1218 if (DctSelIntlvEn) {
1219 *TestAddr = ((UINT64) DctSelBaseAddr << 27) | (*TestAddr & 0xFFFFFFF);
1221 } else if (MemNGetBitFieldNb (NBPtr, BFDramLimitAddr) > (UINT32) (_4GB_RJ16 >> (27 - 16))) {
1222 // if DctSelBase is smaller than 4G, but Dram limit is larger than 4G, then choose 4G as
1223 // dummy read address
1224 *TestAddr = ((UINT64) _4GB_RJ16 << 16) | (*TestAddr & 0xFFFFFF);
1229 // This is the DCT that only goes to low address range
1230 if (DctSelBaseAddr > (_4GB_RJ16 >> (27 - 16))) {
1231 // When DctSelBaseAddr is larger than 4G, choose 4G as the dummy read address
1232 // Keep the lower bits for node and channel selection
1233 *TestAddr = ((UINT64) _4GB_RJ16 << 16) | (*TestAddr & 0xFFFFFF);
1240 // Interleaved Swap Region handling
1241 if ((BOOLEAN) MemNGetBitFieldNb (NBPtr, BFIntLvRgnSwapEn)) {
1242 IntLvRgnBaseAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnBaseAddr);
1243 IntLvRgnLmtAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnLmtAddr);
1244 IntLvRgnSize = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnSize);
1245 ASSERT (IntLvRgnSize == (IntLvRgnLmtAddr - IntLvRgnBaseAddr + 1));
1246 if (((*TestAddr >> 34) == 0) &&
1247 ((((*TestAddr >> 27) >= IntLvRgnBaseAddr) && ((*TestAddr >> 27) <= IntLvRgnLmtAddr))
1248 || ((*TestAddr >> 27) < IntLvRgnSize))) {
1249 *TestAddr ^= (UINT64) IntLvRgnBaseAddr << 27;
1256 /* -----------------------------------------------------------------------------*/
1260 * This function sets bit 7 [MemClkFreqVal] of F2x94_dct[1:0]
1262 * @param[in] AccessWidth - Access width of the register.
1263 * @param[in] Address - address in PCI_ADDR format.
1264 * @param[in, out] *Value - Pointer to the value to be written.
1265 * @param[in, out] *ConfigPtr - Pointer to Config handle.
1269 MemNS3SetMemClkFreqValUnb (
1270 IN ACCESS_WIDTH AccessWidth,
1271 IN PCI_ADDR Address,
1273 IN OUT VOID *ConfigPtr
1278 // 1. Program F2x94_dct[1:0][MemClkFreqVal] = 1
1279 MemNS3SaveNBRegiserUnb (AccessWidth, Address, &TempValue, ConfigPtr);
1281 MemNS3RestoreNBRegiserUnb (AccessWidth, Address, &TempValue, ConfigPtr);
1283 // 2. Wait for F2x94_dct[1:0][FreqChgInPrg] = 0
1284 MemNS3SaveNBRegiserUnb (AccessWidth, Address, &TempValue, ConfigPtr);
1285 while ((TempValue & 0x200000) != 0) {
1286 MemNS3SaveNBRegiserUnb (AccessWidth, Address, &TempValue, ConfigPtr);
1290 /* -----------------------------------------------------------------------------*/
1294 * This function changes memory Pstate context
1296 * @param[in] AccessWidth - Access width of the register.
1297 * @param[in] Address - address in PCI_ADDR format. Target MemPState is in
1298 * Address.Address.Register.
1299 * @param[in, out] *Value - Pointer to the value to be written.
1300 * @param[in, out] *ConfigPtr - Pointer to Config handle.
1304 * ----------------------------------------------------------------------------
1307 MemNS3ChangeMemPStateContextNb (
1308 IN ACCESS_WIDTH AccessWidth,
1309 IN PCI_ADDR Address,
1311 IN OUT VOID *ConfigPtr
1314 MEM_NB_BLOCK *NBPtr;
1315 LOCATE_HEAP_PTR LocateBufferPtr;
1316 S3_MEM_NB_BLOCK *S3NBPtr;
1319 // See which Node should be accessed
1320 Die = (UINT8) (Address.Address.Device - 24);
1322 LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE;
1323 if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
1324 S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr;
1325 NBPtr = S3NBPtr[Die].NBPtr;
1326 MemNChangeMemPStateContextNb (NBPtr, Address.Address.Register);
1330 /* -----------------------------------------------------------------------------*/
1334 * This function retores Phy Clk DLL fine delay
1336 * @param[in] AccessWidth - Access width of the register.
1337 * @param[in] Address - address in PCI_ADDR format.
1338 * @param[in, out] *Value - Pointer to the value to be written.
1339 * @param[in, out] *ConfigPtr - Pointer to Config handle.
1343 MemNS3SetPhyClkDllFineClientNb (
1344 IN ACCESS_WIDTH AccessWidth,
1345 IN PCI_ADDR Address,
1347 IN OUT VOID *ConfigPtr
1352 RegValue = 0x4000 | *(UINT16 *) Value;
1353 MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
1354 RegValue = 0xBFFF & *(UINT16 *) Value;
1355 MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);