7 * Common Northbridge functions
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/NB/)
12 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
18 * All rights reserved.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are met:
22 * * Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
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28 * its contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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38 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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40 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 * ***************************************************************************
46 *----------------------------------------------------------------------------
49 *----------------------------------------------------------------------------
53 #include "AdvancedApi.h"
57 #include "OptionMemory.h"
65 #define FILECODE PROC_MEM_NB_MN_FILECODE
68 /*----------------------------------------------------------------------------
69 * DEFINITIONS AND MACROS
71 *----------------------------------------------------------------------------
73 /*----------------------------------------------------------------------------
74 * TYPEDEFS AND STRUCTURES
76 *----------------------------------------------------------------------------
79 /*----------------------------------------------------------------------------
80 * PROTOTYPES OF LOCAL FUNCTIONS
82 *----------------------------------------------------------------------------
86 MemNDefaultFamilyHookNb (
87 IN OUT MEM_NB_BLOCK *NBPtr,
91 /*----------------------------------------------------------------------------
94 *----------------------------------------------------------------------------
96 extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[];
98 extern BUILD_OPT_CFG UserOptions;
100 /* -----------------------------------------------------------------------------*/
103 * This function initializes member functions and variables of NB block.
105 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
111 IN OUT MEM_NB_BLOCK *NBPtr
117 NBPtr->DctCachePtr = NBPtr->DctCache;
118 NBPtr->PsPtr = NBPtr->PSBlock;
120 BytePtr = (UINT8 *) (NBPtr->DctCache);
121 for (i = 0; i < sizeof (NBPtr->DctCache); i++) {
125 for (i = 0; i < EnumSize; i++) {
126 NBPtr->IsSupported[i] = FALSE;
129 for (i = 0; i < NumberOfHooks; i++) {
130 NBPtr->FamilySpecificHook[i] = MemNDefaultFamilyHookNb;
133 for (i = 0; i < NBPtr->DctCount; i++) {
134 NBPtr->PSBlock[i].MemPGetPass1Seeds = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue;
137 NBPtr->SwitchDCT = MemNSwitchDCTNb;
138 NBPtr->SwitchChannel = MemNSwitchChannelNb;
139 NBPtr->GetBitField = MemNGetBitFieldNb;
140 NBPtr->SetBitField = MemNSetBitFieldNb;
143 /* -----------------------------------------------------------------------------*/
147 * Get System address of Chipselect RJ 16 bits (Addr[47:16])
149 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
150 * @param[in] Receiver - Chipselect to be targeted [0-7]
151 * @param[out] AddrPtr - Pointer to System Address [47:16]
153 * @return TRUE - Address is valid
154 * @return FALSE - Address is not valid
158 MemNGetMCTSysAddrNb (
159 IN OUT MEM_NB_BLOCK *NBPtr,
167 UINT32 DctSelBaseAddr;
170 MEM_DATA_STRUCT *MemPtr;
172 MCTPtr = NBPtr->MCTPtr;
173 MemPtr = NBPtr->MemPtr;
175 ASSERT (Receiver < 8);
177 CSBase = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + Receiver);
179 ASSERT ((CSBase & 0xE0) == 0); // Should not enable CS interleaving before DQS training.
181 // Scale base address from [39:8] to [47:16]
184 HoleBase = MCTPtr->NodeHoleBase ? MCTPtr->NodeHoleBase : 0x7FFFFFFF;
186 if ((MemNGetBitFieldNb (NBPtr, BFDctSelHiRngEn) == 1) && (NBPtr->Dct == MemNGetBitFieldNb (NBPtr, BFDctSelHi))) {
187 DctSelBaseAddr = MemNGetBitFieldNb (NBPtr, BFDctSelBaseAddr) << (27 - 16);
188 if (DctSelBaseAddr > HoleBase) {
189 DctSelBaseAddr -= _4GB_RJ16 - HoleBase;
191 CSBase += DctSelBaseAddr;
193 CSBase += MCTPtr->NodeSysBase;
196 if (CSBase >= HoleBase) {
197 CSBase += _4GB_RJ16 - HoleBase;
200 CSBase += (UINT32)1 << (21 - 16); // Add 2MB offset to avoid compat area.
201 if ((CSBase >= (MCT_TRNG_KEEPOUT_START >> 8)) && (CSBase <= (MCT_TRNG_KEEPOUT_END >> 8))) {
202 CSBase += (((MCT_TRNG_KEEPOUT_END >> 8) - CSBase) + 0x0F) & 0xFFFFFFF0;
205 if (MCTPtr->Status[SbHWHole]) {
206 if (MCTPtr->Status[SbSWNodeHole]) {
207 LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader);
209 if ((CSBase >= (SMsr.lo >> 16)) && (CSBase < _4GB_RJ16)) {
215 BottomUma = NBPtr->RefPtr->Sub4GCacheTop >> 16;
216 if (BottomUma && (CSBase >= BottomUma) && (CSBase < _4GB_RJ16)) {
225 /* -----------------------------------------------------------------------------*/
228 * This function determines if a Rank is enabled.
230 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
231 * @param[in] Receiver - Receiver to check
238 IN OUT MEM_NB_BLOCK *NBPtr,
243 CSBase = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + Receiver);
251 /* -----------------------------------------------------------------------------*/
255 * This function sets the EccSymbolSize bit depending upon configurations
256 * and system override.
258 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
263 MemNSetEccSymbolSizeNb (
264 IN OUT MEM_NB_BLOCK *NBPtr
272 ASSERT (NBPtr != NULL);
274 MCTPtr = NBPtr->MCTPtr;
275 DCTPtr = NBPtr->DCTPtr;
277 // Determine if this node has only x4 DRAM parts
278 X4DimmsOnly = (UINT16) ((!(DCTPtr->Timings.Dimmx8Present | DCTPtr->Timings.Dimmx16Present)) && DCTPtr->Timings.Dimmx4Present);
280 // Check if EccSymbolSize BKDG value is overridden
282 if (UserOptions.CfgEccSymbolSize != ECCSYMBOLSIZE_USE_BKDG) {
283 Size = (UserOptions.CfgEccSymbolSize == ECCSYMBOLSIZE_FORCE_X4) ? FALSE : TRUE;
285 if (X4DimmsOnly && MCTPtr->GangedMode) {
291 IDS_OPTION_HOOK (IDS_ECCSYMBOLSIZE, &Size, &(NBPtr->MemPtr->StdHeader));
292 MemNSetBitFieldNb (NBPtr, BFEccSymbolSize, (UINT32) Size);
295 /* -----------------------------------------------------------------------------*/
298 * This function sets the training control flow
299 * The DDR3 mode bit must be set prior to calling this function
301 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
305 IN OUT MEM_NB_BLOCK *NBPtr
308 if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) {
309 memNTrainFlowControl[DDR3_TRAIN_FLOW] (NBPtr);
311 memNTrainFlowControl[DDR2_TRAIN_FLOW] (NBPtr);
316 /*-----------------------------------------------------------------------------*/
319 * This function flushes the training pattern
320 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
321 * @param[in] Address - System Address [47:16]
322 * @param[in] ClCount - Number of cache lines
328 IN OUT MEM_NB_BLOCK *NBPtr,
333 // Due to speculative execution during MemUReadCachelines, we must
334 // flush one more cache line than we read.
335 MemUProcIOClFlush (Address, ClCount + 1, NBPtr->MemPtr);
338 /* -----------------------------------------------------------------------------*/
341 * This function compares test pattern with data in buffer and
342 * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved)
344 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
345 * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare
346 * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against
347 * @param[in] ByteCount - Byte count
349 * @return PASS - Bitmap of results of comparison
353 MemNCompareTestPatternNb (
354 IN OUT MEM_NB_BLOCK *NBPtr,
363 UINT8 FailingBitMask[8];
365 ASSERT ((ByteCount == 18 * 64) || (ByteCount == 9 * 64) || (ByteCount == 64 * 64) || (ByteCount == 32 * 64) || (ByteCount == 3 * 64));
367 ColumnCount = NBPtr->ChannelPtr->ColumnCount;
370 // Clear Failing Bit Mask
372 for (i = 0; i < sizeof (FailingBitMask); i++) {
373 FailingBitMask[i] = 0;
376 if (NBPtr->Ganged && (NBPtr->Dct != 0)) {
377 i = 8; // DCT 1 in ganged mode
382 for (; i < ByteCount; i++) {
383 if (Buffer[i] != Pattern[i]) {
384 // if bytelane n fails
385 Pass &= ~((UINT16)1 << (i % 8)); // clear bit n
386 FailingBitMask[i % NBPtr->TechPtr->MaxByteLanes ()] |= (Buffer[i] ^ Pattern[i]);
389 if (NBPtr->Ganged && ((i & 7) == 7)) {
390 i += 8; // if ganged, skip over other Channel's Data
394 // Accumulate Failing bit data
396 for (i = 0; i < sizeof (FailingBitMask); i++) {
397 NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel) + i] &=
404 /*-----------------------------------------------------------------------------
407 * This function compares test pattern with data in buffer and
408 * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved)
410 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
411 * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare
412 * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against
413 * @param[in] ByteCount - Byte count
415 * @retval PASS - Bitmap of results of comparison
416 * ----------------------------------------------------------------------------
419 MemNInsDlyCompareTestPatternNb (
420 IN MEM_NB_BLOCK *NBPtr,
431 UINT8 FailingBitMask[8];
433 ASSERT ((ByteCount == 18 * 64) || (ByteCount == 9 * 64) || (ByteCount == 64 * 64) || (ByteCount == 32 * 64) || (ByteCount == 3 * 64));
435 ColumnCount = NBPtr->ChannelPtr->ColumnCount;
438 // Clear Failing Bit Mask
440 for (i = 0; i < sizeof (FailingBitMask); i++) {
441 FailingBitMask[i] = 0;
444 if (NBPtr->Ganged && (NBPtr->Dct != 0)) {
445 i = 8; // DCT 1 in ganged mode
457 for (; i < ByteCount; i++) {
459 if (Buffer[i] != Pattern[i + BeatOffset]) {
460 // if bytelane n fails
461 Pass &= ~((UINT16)1 << (i % 8)); // clear bit n
462 FailingBitMask[i % NBPtr->TechPtr->MaxByteLanes ()] |= (Buffer[i] ^ Pattern[i + BeatOffset]);
467 i += 8; // if ganged, skip over other Channel's Data
472 if ((BeatCnt & 3) == 3) {
473 // Skip last data beat of a 4-beat burst.
479 // Accumulate Failing bit data
481 for (i = 0; i < sizeof (FailingBitMask); i++) {
482 NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel) + i] &=
489 /* -----------------------------------------------------------------------------*/
492 * This function sets the training control flow for UNB
493 * The DDR3 mode bit must be set prior to calling this function
495 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
498 MemNTrainingFlowUnb (
499 IN OUT MEM_NB_BLOCK *NBPtr
502 memNTrainFlowControl[DDR3_TRAIN_FLOW] (NBPtr);
505 /*----------------------------------------------------------------------------
508 *----------------------------------------------------------------------------
511 /*-----------------------------------------------------------------------------
514 * This function is an empty function used to intialize FamilySpecificHook array
516 * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
517 * @param[in,out] OptParam - Optional parameter
519 * @return TRUE - always
520 * ----------------------------------------------------------------------------
524 MemNDefaultFamilyHookNb (
525 IN OUT MEM_NB_BLOCK *NBPtr,
526 IN OUT VOID *OptParam