src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.c

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * mnor.c
   6  *
   7  * Common Northbridge  functions for Orochi
   8  *
   9  * @xrefitem bom "File Content Label" "Release Content"
  10  * @e project: AGESA
  11  * @e sub-project: (Mem/NB/OR)
  12  * @e \$Revision: 52421 $ @e \$Date: 2011-05-05 21:03:23 -0600 (Thu, 05 May 2011) $
  13  *
  14  **/
  15 /*****************************************************************************
  16 *
  17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
  18 * All rights reserved.
  19 *
  20 * Redistribution and use in source and binary forms, with or without
  21 * modification, are permitted provided that the following conditions are met:
  22 *     * Redistributions of source code must retain the above copyright
  23 *       notice, this list of conditions and the following disclaimer.
  24 *     * Redistributions in binary form must reproduce the above copyright
  25 *       notice, this list of conditions and the following disclaimer in the
  26 *       documentation and/or other materials provided with the distribution.
  27 *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  28 *       its contributors may be used to endorse or promote products derived
  29 *       from this software without specific prior written permission.
  30 *
  31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  37 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  38 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  40 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  41 *
  42 * ***************************************************************************
  43 *
  44 */
  45
  46 /*
  47  *----------------------------------------------------------------------------
  48  *                                MODULES USED
  49  *
  50  *----------------------------------------------------------------------------
  51  */
  52
  53
  54
  55 #include "AGESA.h"
  56 #include "AdvancedApi.h"
  57 #include "amdlib.h"
  58 #include "Ids.h"
  59 #include "OptionMemory.h"
  60 #include "mm.h"
  61 #include "mn.h"
  62 #include "mnor.h"
  63 #include "mu.h"
  64 #include "S3.h"
  65 #include "cpuRegisters.h"
  66 #include "cpuFamRegisters.h"
  67 #include "cpuFamilyTranslation.h"
  68 #include "F15PackageType.h"
  69 #include "heapManager.h"
  70 #include "GeneralServices.h"
  71 #include "Filecode.h"
  72 CODE_GROUP (G3_DXE)
  73 RDATA_GROUP (G3_DXE)
  74
  75 #define FILECODE PROC_MEM_NB_OR_MNOR_FILECODE
  76 /*----------------------------------------------------------------------------
  77  *                          DEFINITIONS AND MACROS
  78  *
  79  *----------------------------------------------------------------------------
  80  */
  81
  82 #define SPLIT_CHANNEL   (UINT32) 0x20000000
  83 #define CHANNEL_SELECT  (UINT32) 0x10000000
  84
  85 /*----------------------------------------------------------------------------
  86  *                           TYPEDEFS AND STRUCTURES
  87  *
  88  *----------------------------------------------------------------------------
  89  */
  90 /*----------------------------------------------------------------------------
  91  *                        PROTOTYPES OF LOCAL FUNCTIONS
  92  *
  93  *----------------------------------------------------------------------------
  94  */
  95 /**
  96  * @todo:  Add Comments with field descriptions
  97  */
  98 CONST MEM_FREQ_CHANGE_PARAM FreqChangeParamOr = {0x0190, 7, 7, 14, 3, 18, 470, 946};
  99
 100 /*----------------------------------------------------------------------------
 101  *                            EXPORTED FUNCTIONS
 102  *
 103  *----------------------------------------------------------------------------
 104  */
 105
 106 extern BUILD_OPT_CFG UserOptions;
 107 extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
 108 extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[];
 109
 110 /* -----------------------------------------------------------------------------*/
 111 /**
 112  *
 113  *
 114  *   This function initializes the northbridge block
 115  *
 116  *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
 117  *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
 118  *     @param[in]        *FeatPtr  - Pointer to the MEM_FEAT_BLOCK_NB
 119  *     @param[in]        *SharedPtr - Pointer to the MEM_SHARED_DATA
 120  *     @param[in]        NodeID  - UINT8 indicating node ID of the NB object.
 121  *
 122  *     @return     Boolean indicating that this is the correct memory
 123  *                 controller type for the node number that was passed in.
 124  */
 125
 126 BOOLEAN
 127 MemConstructNBBlockOR (
 128   IN OUT   MEM_NB_BLOCK *NBPtr,
 129   IN OUT   MEM_DATA_STRUCT *MemPtr,
 130   IN       MEM_FEAT_BLOCK_NB *FeatPtr,
 131   IN       MEM_SHARED_DATA *SharedPtr,
 132   IN       UINT8 NodeID
 133   )
 134 {
 135   UINT8 Dct;
 136   UINT8 Channel;
 137   UINT8 SpdSocketIndex;
 138   UINT8 SpdChannelIndex;
 139   DIE_STRUCT *MCTPtr;
 140   ALLOCATE_HEAP_PARAMS AllocHeapParams;
 141
 142   //
 143   // Determine if this is the expected NB Type
 144   //
 145   GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
 146   if (!MemNIsIdSupportedOr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
 147     return FALSE;
 148   }
 149
 150   NBPtr->MemPtr = MemPtr;
 151   NBPtr->RefPtr = MemPtr->ParameterListPtr;
 152   NBPtr->SharedPtr = SharedPtr;
 153
 154   MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
 155   NBPtr->MCTPtr = MCTPtr;
 156   NBPtr->MCTPtr->NodeId = NodeID;
 157   NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
 158   NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
 159
 160   //
 161   // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
 162   //
 163   AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_OR * (
 164                                           sizeof (DCT_STRUCT) + (
 165                                             MAX_CHANNELS_PER_DCT_OR * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
 166                                           )
 167                                         );
 168   AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
 169   AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
 170   if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
 171     PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
 172     SetMemError (AGESA_FATAL, MCTPtr);
 173     ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
 174     return FALSE;
 175   }
 176
 177   MCTPtr->DctCount = MAX_DCTS_PER_NODE_OR;
 178   MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
 179   AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_OR * sizeof (DCT_STRUCT);
 180   for (Dct = 0; Dct < MAX_DCTS_PER_NODE_OR; Dct++) {
 181     MCTPtr->DctData[Dct].Dct = Dct;
 182     MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_OR;
 183     MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
 184     MCTPtr->DctData[Dct].ChData[0].Dct = Dct;
 185     AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_OR * sizeof (CH_DEF_STRUCT);
 186   }
 187   NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
 188
 189   //
 190   // Initialize Socket List
 191   //
 192   for (Dct = 0; Dct < MAX_DCTS_PER_NODE_OR; Dct++) {
 193     MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
 194     MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].Timings);
 195     MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct;
 196   }
 197
 198   MemNInitNBDataOr (NBPtr);
 199
 200   FeatPtr->InitCPG (NBPtr);
 201   FeatPtr->InitHwRxEn (NBPtr);
 202   FeatPtr->InitEarlySampleSupport (NBPtr);
 203   NBPtr->FeatPtr = FeatPtr;
 204
 205
 206   //
 207   // Calculate SPD Offsets per channel and assign pointers to the data.  At this point, we calculate the Node-Dct-Channel
 208   // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
 209   // channel.  This pointer is then used later to calculate the offsets to be used for each logical dimm once the
 210   // dimm types(QR or not) are known. This is done in the Technology block constructor.
 211   //
 212   // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
 213   // This will facilitate modifications due to some processors that might
 214   // map the DCT-CHANNEL differently.
 215   //
 216   SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
 217   //
 218   // Traverse the Dct/Channel structures
 219   //
 220   for (Dct = 0; Dct < MAX_DCTS_PER_NODE_OR; Dct++) {
 221     for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_OR; Channel++) {
 222       //
 223       // Calculate the number of Dimms on this channel using the
 224       //   die/dct/channel to Socket/channel conversion.
 225       //
 226       SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
 227                                             NBPtr->MCTPtr->SocketId,
 228                                             MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel),
 229                                             &MemPtr->StdHeader);
 230       NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
 231     }
 232   }
 233
 234   //
 235   // Initialize Dct and DctCfgSel bit
 236   //
 237   MemNSetBitFieldNb (NBPtr, BFDctCfgSel, 0);
 238   MemNSwitchDCTNb (NBPtr, 0);
 239
 240   return TRUE;
 241 }
 242
 243 /* -----------------------------------------------------------------------------*/
 244 /**
 245  *
 246  *   This function initializes member functions and variables of NB block.
 247  *
 248  *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
 249  *
 250  */
 251
 252 VOID
 253 MemNInitNBDataOr (
 254   IN OUT   MEM_NB_BLOCK *NBPtr
 255   )
 256 {
 257   UINT32  PackageType;
 258
 259   NBPtr->DctCachePtr = NBPtr->DctCache;
 260   NBPtr->PsPtr = NBPtr->PSBlock;
 261
 262   MemNInitNBRegTableOr (NBPtr, NBPtr->NBRegTable);
 263   NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
 264   NBPtr->Dct = 0;
 265   NBPtr->Channel = 0;
 266   NBPtr->DctCount = MAX_DCTS_PER_NODE_OR;
 267   NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_OR;
 268   NBPtr->NodeCount = MAX_NODES_SUPPORTED_OR;
 269   NBPtr->Ganged = FALSE;
 270   NBPtr->PosTrnPattern = POS_PATTERN_256B;
 271   NBPtr->MemCleared = FALSE;
 272   NBPtr->StartupSpeed = DDR667_FREQUENCY;
 273   NBPtr->RcvrEnDlyLimit = 0x1FF;
 274   NBPtr->DefDctSelIntLvAddr = 3;
 275   NBPtr->NbFreqChgState = 0;
 276   NBPtr->MaxRxEnSeedTotal = 0x3FF;
 277   NBPtr->MinRxEnSeedGross = 0;
 278   NBPtr->FreqChangeParam = (MEM_FREQ_CHANGE_PARAM *) &FreqChangeParamOr;
 279   NBPtr->CsRegMsk = 0x7FF83FE0;
 280   NBPtr->TotalMaxVrefRange = 0x20;
 281   NBPtr->TotalRdDQSDlyRange = 0x40;
 282   NBPtr->MaxSeedCount = MAX____DQS_SEED_COUNT;
 283   NBPtr->PhaseLaneMask = 0x3FFFF;
 284   NBPtr->MaxDiamondStep = 3;
 285
 286   LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
 287
 288   NBPtr->SetMaxLatency = MemNSetMaxLatencyOr;
 289   NBPtr->getMaxLatParams = MemNGetMaxLatParamsOr;
 290   NBPtr->InitializeMCT = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue;
 291   NBPtr->FinalizeMCT = MemNFinalizeMctOr;
 292   NBPtr->SendMrsCmd = MemNSendMrsCmdUnb;
 293   NBPtr->sendZQCmd = MemNSendZQCmdNb;
 294   NBPtr->WritePattern = MemNWritePatternOr;
 295   NBPtr->ReadPattern = MemNReadPatternOr;
 296   NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
 297   NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
 298   NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
 299   NBPtr->StitchMemory = MemNStitchMemoryNb;
 300   NBPtr->AutoConfig = MemNAutoConfigOr;
 301   NBPtr->PlatformSpec = MemNPlatformSpecUnb;
 302   NBPtr->InitMCT = MemNInitMCTNb;
 303   NBPtr->DisableDCT = MemNDisableDCTUnb;
 304   NBPtr->StartupDCT = MemNStartupDCTUnb;
 305   NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
 306   NBPtr->ChangeFrequency = MemNChangeFrequencyUnb;
 307   NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
 308   NBPtr->ChangeNbFrequency = MemNChangeNbFrequencyUnb;
 309   NBPtr->ChangeNbFrequencyWrap = MemNChangeNbFrequencyWrapUnb;
 310   NBPtr->ProgramNbPsDependentRegs = MemNProgramNbPstateDependentRegistersUnb;
 311   NBPtr->ProgramCycTimings = MemNProgramCycTimingsUnb;
 312   NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
 313   NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
 314   NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
 315   NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
 316   NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingOr;
 317   NBPtr->AfterDqsTraining = MemNAfterDQSTrainingOr;
 318   NBPtr->OtherTiming = MemNOtherTimingOr;
 319   NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
 320   NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelOr;
 321   NBPtr->TechBlockSwitch = MemNTechBlockSwitchOr;
 322   NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldOr;
 323   NBPtr->SetEccSymbolSize = MemNSetEccSymbolSizeNb;
 324   NBPtr->TrainingFlow = (VOID (*) (MEM_NB_BLOCK *)) MemNTrainingFlowUnb;
 325   MemNInitNBDataNb (NBPtr);
 326   NBPtr->PollBitField = MemNPollBitFieldNb;
 327   NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
 328   NBPtr->BrdcstSet = MemNBrdcstSetNb;
 329   NBPtr->GetTrainDly = MemNGetTrainDlyNb;
 330   NBPtr->SetTrainDly = MemNSetTrainDlyNb;
 331   NBPtr->PhyFenceTraining = MemNPhyFenceTrainingUnb;
 332   NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
 333   NBPtr->RankEnabled = MemNRankEnabledNb;
 334   NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitOr;
 335   NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyUnb;
 336   NBPtr->MemPPhyFenceTrainingNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
 337   NBPtr->MemNInitPhyComp = MemNInitPhyCompOr;
 338   NBPtr->MemNBeforePlatformSpecNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
 339   NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitTblDrvNb;
 340   NBPtr->MemNPFenceAdjustNb = MemNPFenceAdjustOr;
 341   NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsUnb;
 342   NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
 343   NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
 344   NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
 345   NBPtr->CSPerChannel = MemNCSPerChannelNb;
 346   NBPtr->CSPerDelay = MemNCSPerDelayNb;
 347   NBPtr->FlushPattern = MemNFlushPatternNb;
 348   NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
 349   NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeOr;
 350   NBPtr->GetUmaSize = MemNGetUmaSizeNb;
 351   NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdUnb;
 352   NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb;
 353   NBPtr->WaitXMemClks = MemNWaitXMemClksNb;
 354   NBPtr->MemNGetDramTerm = MemNGetDramTermTblDrvNb;
 355   NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermTblDrvNb;
 356   NBPtr->MemNGetMR0CL = MemNGetMR0CLTblDrvNb;
 357   NBPtr->MemNGetMR0WR = MemNGetMR0WRTblDrvNb;
 358   NBPtr->MemNSaveMR0 = MemNSaveMR0Or;
 359   NBPtr->MemNGetMR2CWL = MemNGetMR2CWLUnb;
 360   NBPtr->AllocateC6Storage = MemNAllocateC6StorageUnb;
 361   NBPtr->InPhaseCompareRdDqs__Pattern = MemNInPhaseCompareRdDqs__PatternUnb;
 362   NBPtr->Phase180CompareRdDqs__Pattern = MemN180CompareRdDqs__PatternUnb;
 363   NBPtr->AgressorContinuousWrites = MemNAgressorContinuousWritesUnb;
 364   NBPtr->GetPrbs__RdDqsSeed = MemNGetPrbs__RdDqsSeedUnb;
 365   NBPtr->InitializeRdDqs__VictimContinuousWrites = MemNInitializeRdDqs__VictimContinuousWritesUnb;
 366   NBPtr->FinalizeRdDqs__VictimContinuousWrites = MemNFinalizeRdDqs__VictimContinuousWritesUnb;
 367   NBPtr->InitializeRdDqs__VictimChipSelContinuousWrites = MemNInitializeRdDqs__VictimChipSelContinuousWritesUnb;
 368   NBPtr->StartRdDqs__VictimContinuousWrites = MemNStartRdDqs__VictimContinuousWritesUnb;
 369
 370   NBPtr->IsSupported[SetSpareEn] = TRUE;
 371   NBPtr->IsSupported[CheckSpareEn] = TRUE;
 372   NBPtr->IsSupported[SetDllShutDown] = TRUE;
 373   NBPtr->IsSupported[CheckEccDLLPwrDnConfig] = TRUE;
 374   NBPtr->IsSupported[DimmBasedOnSpeed] = FALSE;
 375   NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
 376   NBPtr->IsSupported[Check1GAlign] = FALSE;
 377   NBPtr->IsSupported[CheckDisDllShutdownSR] = FALSE;
 378   NBPtr->IsSupported[CheckMemClkCSPresent] = TRUE;
 379   NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
 380   NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
 381   NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE;
 382   NBPtr->IsSupported[CheckGetMCTSysAddr] = FALSE;
 383   NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE;
 384   NBPtr->IsSupported[CheckFindPSDct] = FALSE;
 385   NBPtr->IsSupported[FenceTrnBeforeDramInit] = TRUE;
 386   NBPtr->IsSupported[UnifiedNbFence] = TRUE;
 387   NBPtr->IsSupported[CheckODTControls] = TRUE;
 388   NBPtr->IsSupported[CheckDummyCLRead] = TRUE;
 389   NBPtr->IsSupported[CheckDllStdBy] = FALSE;
 390   NBPtr->IsSupported[CheckSlewWithMarginImprv] = FALSE;
 391   NBPtr->IsSupported[CheckSlewWithoutMarginImprv] = TRUE;
 392   NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
 393   NBPtr->IsSupported[CheckDllRegDis] = FALSE;
 394   NBPtr->IsSupported[PchgPDMode] = TRUE;
 395   NBPtr->IsSupported[EccByteTraining] = TRUE;
 396   NBPtr->IsSupported[CheckDramTerm] = TRUE;
 397   NBPtr->IsSupported[CheckDramTermDyn] = TRUE;
 398   NBPtr->IsSupported[CheckQoff] = TRUE;
 399   NBPtr->IsSupported[CheckDrvImpCtrl] = TRUE;
 400   NBPtr->IsSupported[CheckSetSameDctODTsEn] = TRUE;
 401   NBPtr->IsSupported[WLSeedAdjust] = TRUE;
 402   NBPtr->IsSupported[WLNegativeDelay] = TRUE;
 403   NBPtr->IsSupported[TwoStageDramInit] = TRUE;
 404   NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
 405   NBPtr->IsSupported[ProgramCsrComparator] = TRUE;
 406   NBPtr->IsSupported[SetTDqsForx8DimmOnly] = TRUE;
 407   NBPtr->IsSupported[WlRttNomFor1of3Cfg] = TRUE;
 408
 409   NBPtr->FamilySpecificHook[ExitPhyAssistedTraining] = MemNExitPhyAssistedTrainingOr;
 410   NBPtr->FamilySpecificHook[DCTSelectSwitch] = MemNDctCfgSelectUnb;
 411   NBPtr->FamilySpecificHook[ScrubberErratum] = MemNScrubberErratumOr;
 412   NBPtr->FamilySpecificHook[AfterSaveRestore] = MemNAfterSaveRestoreUnb;
 413   NBPtr->FamilySpecificHook[OverrideDataTxFifoWrDly] = MemNDataTxFifoWrDlyOverrideOr;
 414   NBPtr->FamilySpecificHook[OverrideRcvEnSeed] = MemNOverrideRcvEnSeedOr;
 415   NBPtr->FamilySpecificHook[OverrideRcvEnSeedPassN] = MemNOverrideRcvEnSeedPassNOr;
 416   NBPtr->FamilySpecificHook[OverrideWLSeed] = MemNOverrideWLSeedOr;
 417   NBPtr->FamilySpecificHook[AfterMemClkFreqChg] = MemNAfterMemClkFreqChgOr;
 418   NBPtr->FamilySpecificHook[CalcWrDqDqsEarly] = MemNCalcWrDqDqsEarlyUnb;
 419   NBPtr->FamilySpecificHook[TrainWlPerNibble] = MemNTrainWlPerNibbleOr;
 420   NBPtr->FamilySpecificHook[TrainWlPerNibbleAdjustWLDly] = MemNTrainWlPerNibbleAdjustWLDlyOr;
 421   NBPtr->FamilySpecificHook[TrainWlPerNibbleSeed] = MemNTrainWlPerNibbleSeedOr;
 422   NBPtr->FamilySpecificHook[TrainRxEnPerNibble] = MemNTrainRxEnPerNibbleOr;
 423   NBPtr->FamilySpecificHook[TrainRxEnAdjustDlyPerNibble] = MemNTrainRxEnAdjustDlyPerNibbleOr;
 424   NBPtr->FamilySpecificHook[TrainRxEnGetAvgDlyPerNibble] = MemNTrainRxEnGetAvgDlyPerNibbleOr;
 425   NBPtr->FamilySpecificHook[InitPerNibbleTrn] = MemNInitPerNibbleTrnOr;
 426   NBPtr->FamilySpecificHook[TrainingNibbleZero] = MemNTrainingNibbleZeroOr;
 427   NBPtr->FamilySpecificHook[BeforeSetCsTri] = MemNBeforeSetCsTriOr;
 428   NBPtr->FamilySpecificHook[AdjustRdDqsDlyOffset] = MemNAdjustRdDqsDlyOffsetUnb;
 429   NBPtr->FamilySpecificHook[EnableParityAfterMemRst] = MemNEnableParityAfterMemRstOr;
 430   NBPtr->FamilySpecificHook[GetDdrMaxRate] = MemNGetMaxDdrRateUnb;
 431   NBPtr->FamilySpecificHook[ProgOdtControl] = MemNProgOdtControlOr;
 432   NBPtr->FamilySpecificHook[SetSkewMemClk] = MemNSetSkewMemClkUnb;
 433   NBPtr->FamilySpecificHook[ReleaseNbPstate] = MemNReleaseNbPstateOr;
 434   NBPtr->FamilySpecificHook[InitializeRxEnSeedlessTraining] = MemNInitializeRxEnSeedlessTrainingUnb;
 435   NBPtr->FamilySpecificHook[TrackRxEnSeedlessRdWrNoWindBLError] = MemNTrackRxEnSeedlessRdWrNoWindBLErrorUnb;
 436   NBPtr->FamilySpecificHook[TrackRxEnSeedlessRdWrSmallWindBLError] = MemNTrackRxEnSeedlessRdWrSmallWindBLErrorUnb;
 437   NBPtr->FamilySpecificHook[InitialzeRxEnSeedlessByteLaneError] = MemNInitialzeRxEnSeedlessByteLaneErrorUnb;
 438   NBPtr->FamilySpecificHook[AdjustWrDqsBeforeSeedScaling] = MemNAdjustWrDqsBeforeSeedScalingOr;
 439   NBPtr->FamilySpecificHook[Adjust2DPhaseMaskBasedOnEcc] = MemNAdjust2DPhaseMaskBasedOnEccUnb;
 440
 441   PackageType = LibAmdGetPackageType (&(NBPtr->MemPtr->StdHeader));
 442   if (PackageType == PACKAGE_TYPE_AM3r2) {
 443     // AM3r2 does not support 1.35V
 444     NBPtr->IsSupported[PerformanceOnly] = TRUE;
 445
 446     // AM3r2 does not support Dll shutdown
 447     NBPtr->IsSupported[SetDllShutDown] = FALSE;
 448   }
 449 }
 450
 451 /* -----------------------------------------------------------------------------*/
 452 /**
 453  *
 454  *
 455  *   This function initializes the default values in the MEM_DATA_STRUCT
 456  *
 457  *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
 458  *
 459  */
 460 VOID
 461 MemNInitDefaultsOR (
 462   IN OUT   MEM_DATA_STRUCT *MemPtr
 463   )
 464 {
 465   UINT8 Socket;
 466   UINT8 Channel;
 467   MEM_PARAMETER_STRUCT *RefPtr;
 468   ASSERT (MemPtr != NULL);
 469   RefPtr = MemPtr->ParameterListPtr;
 470
 471   // Memory Map/Mgt.
 472   // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
 473   RefPtr->BottomIo = 0xE0;
 474   RefPtr->UmaMode = UserOptions.CfgUmaMode;
 475   RefPtr->UmaSize = UserOptions.CfgUmaSize;
 476   RefPtr->MemHoleRemapping = TRUE;
 477   RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb;
 478   //
 479
 480
 481   // Dram Timing
 482   RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
 483   RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
 484   for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
 485     for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
 486       MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
 487       MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
 488     }
 489   }
 490
 491   // Memory Clear
 492   RefPtr->EnableMemClr = TRUE;
 493
 494   // TableBasedAlterations
 495   RefPtr->TableBasedAlterations = NULL;
 496
 497   // Platform config table
 498   RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
 499
 500   // Memory Restore
 501   RefPtr->MemRestoreCtl = FALSE;
 502   RefPtr->SaveMemContextCtl = FALSE;
 503   AmdS3ParamsInitializer (&RefPtr->MemContext);
 504
 505   // Dram Configuration
 506   RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
 507   RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
 508   RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
 509   RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
 510   RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
 511   RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
 512
 513   // Dram Power
 514   RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
 515
 516   // ECC
 517   RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
 518
 519   // Vref
 520   RefPtr->ExternalVrefCtl = UserOptions.CfgExternalVrefCtlFeature;
 521
 522   //Training Mode
 523   RefPtr->ForceTrainMode = UserOptions.CfgForceTrainMode;
 524 }
 525 /*-----------------------------------------------------------------------------*/
 526 /**
 527  *
 528  *      This function writes training pattern
 529  *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
 530  *     @param[in] Pattern[] - Pattern to write
 531  *     @param[in] Address - System Address [47:16]
 532  *     @param[in] ClCount - Number of cache lines
 533  *
 534  */
 535
 536 VOID
 537 MemNWritePatternOr (
 538   IN OUT   MEM_NB_BLOCK *NBPtr,
 539   IN       UINT32 Address,
 540   IN       UINT8 Pattern[],
 541   IN       UINT16 ClCount
 542   )
 543 {
 544   Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
 545   MemUWriteCachelines (Address, Pattern, ClCount);
 546 }
 547
 548 /*-----------------------------------------------------------------------------*/
 549 /**
 550  *
 551  *      This function reads training pattern
 552  *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
 553  *     @param[in] Buffer[] - Buffer to fill
 554  *     @param[in] Address - System Address [47:16]
 555  *     @param[in] ClCount - Number of cache lines
 556  *
 557  */
 558
 559 VOID
 560 MemNReadPatternOr (
 561   IN OUT   MEM_NB_BLOCK *NBPtr,
 562   IN       UINT8 Buffer[],
 563   IN       UINT32 Address,
 564   IN       UINT16 ClCount
 565   )
 566 {
 567   Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
 568   MemUReadCachelines (Buffer, Address, ClCount);
 569 }
 570
 571 /* -----------------------------------------------------------------------------*/
 572 /**
 573  *
 574  *   This function initiates DQS training for Unified NB
 575  *
 576  *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
 577  *
 578  */
 579
 580 BOOLEAN
 581 memNEnableTrainSequenceOr (
 582   IN OUT   MEM_NB_BLOCK *NBPtr
 583   )
 584 {
 585   BOOLEAN Retval;
 586   Retval = TRUE;
 587   if (!MemNIsIdSupportedOr (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) {
 588     Retval = FALSE;
 589   }
 590   return Retval;
 591 }
 592
 593 /* -----------------------------------------------------------------------------*/
 594 /**
 595  *
 596  *
 597  *   This function save the MR0 value sent to memory during initialization
 598  *
 599  *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
 600  *     @param[in]       MrsAddress   - MR0 value to be saved
 601  *     @return         none
 602  */
 603 VOID
 604 MemNSaveMR0Or (
 605   IN OUT   MEM_NB_BLOCK *NBPtr,
 606   IN       UINT32 MrsAddress
 607   )
 608 {
 609   AGESA_STATUS Status;
 610   LOCATE_HEAP_PTR LocateHeapStructPtr;
 611   ALLOCATE_HEAP_PARAMS AllocHeapParams;
 612   UINT32 ChipSel;
 613   MR0_DATA_ARRAY_PTR pMR0Data;
 614
 615   ChipSel = NBPtr->GetBitField (NBPtr, BFMrsChipSel);
 616   LocateHeapStructPtr.BufferHandle = AMD_MEM_S3_MR0_DATA_HANDLE;
 617   LocateHeapStructPtr.BufferPtr = NULL;
 618   Status = HeapLocateBuffer (&LocateHeapStructPtr, &NBPtr->MemPtr->StdHeader);
 619   if (Status == AGESA_SUCCESS) {
 620     // MR0 data already present in heap
 621     pMR0Data = (MR0_DATA_ARRAY_PTR) (LocateHeapStructPtr.BufferPtr);
 622     ASSERT (pMR0Data != NULL);
 623   } else {
 624     AllocHeapParams.RequestedBufferSize = sizeof (MR0_DATA_STRUCT) * MAX_NODES_SUPPORTED_OR * MAX_DCTS_PER_NODE_OR;
 625     AllocHeapParams.BufferHandle = AMD_MEM_S3_MR0_DATA_HANDLE;
 626     AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
 627
 628     //
 629     // Allocate data buffer in heap
 630     //
 631     Status = HeapAllocateBuffer (&AllocHeapParams, &NBPtr->MemPtr->StdHeader);
 632     ASSERT (Status == AGESA_SUCCESS);
 633     pMR0Data = (MR0_DATA_ARRAY_PTR) (AllocHeapParams.BufferPtr);
 634     ASSERT (pMR0Data != NULL);
 635     LibAmdMemFill (pMR0Data, 0, sizeof (MR0_DATA_STRUCT) * MAX_NODES_SUPPORTED_OR * MAX_DCTS_PER_NODE_OR, &NBPtr->MemPtr->StdHeader);
 636   }
 637   (*pMR0Data)[NBPtr->Node][NBPtr->Dct].MR0Value = (UINT16) MrsAddress;
 638   (*pMR0Data)[NBPtr->Node][NBPtr->Dct].ChipSelEnMap |= (((UINT16)1) << ChipSel);
 639   IDS_HDT_CONSOLE (MEM_FLOW, "\tLog last MR0\n\t\tNode: %d, Dct: %d, CS: %d, MR0: %08X\n", NBPtr->Node, NBPtr->Dct, ChipSel, MrsAddress);
 640 }