7 * Main Memory initialization sequence for C32
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/Main/C32)
12 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
18 * All rights reserved.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are met:
22 * * Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
28 * its contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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38 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
40 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 * ***************************************************************************
47 *----------------------------------------------------------------------------
50 *----------------------------------------------------------------------------
57 #include "OptionMemory.h"
62 #include "cpuFamilyTranslation.h"
64 #include "GeneralServices.h"
68 #define FILECODE PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE
72 extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
74 /*----------------------------------------------------------------------------
75 * DEFINITIONS AND MACROS
77 *----------------------------------------------------------------------------
80 /*----------------------------------------------------------------------------
81 * TYPEDEFS AND STRUCTURES
83 *----------------------------------------------------------------------------
86 /*----------------------------------------------------------------------------
87 * PROTOTYPES OF LOCAL FUNCTIONS
89 *----------------------------------------------------------------------------
94 IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
97 /*----------------------------------------------------------------------------
100 *----------------------------------------------------------------------------
102 /* -----------------------------------------------------------------------------*/
106 * This function defines the memory initialization flow for
107 * systems that only support C32 processors.
109 * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
111 * @return AGESA_STATUS
119 IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
125 MEM_TECH_BLOCK *TechPtr;
126 MEM_DATA_STRUCT *MemPtr;
128 NBPtr = MemMainPtr->NBPtr;
129 TechPtr = MemMainPtr->TechPtr;
130 NodeCnt = MemMainPtr->DieCount;
131 MemPtr = MemMainPtr->MemPtr;
133 GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader));
134 if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) {
135 MemPtr->IsFlowControlSupported = FALSE;
138 MemPtr->IsFlowControlSupported = TRUE;
141 for (Node = 0; Node < NodeCnt; Node++) {
142 MemFInitTableDrive (&NBPtr[Node], MTBeforeInitializeMCT);
145 //----------------------------------------------------------------
147 //----------------------------------------------------------------
148 AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
149 for (Node = 0; Node < NodeCnt; Node++) {
150 if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
155 //----------------------------------------------------------------
157 //----------------------------------------------------------------
158 // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
159 AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
160 if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
164 //----------------------------------------------------------------
165 // Initialize DRAM and DCTs, and Create Memory Map
166 //----------------------------------------------------------------
167 AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
168 for (Node = 0; Node < NodeCnt; Node++) {
169 // Initialize Memory Controller and Dram
170 IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node);
171 if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
172 return AGESA_FATAL; //fatalexit
176 AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
177 if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
182 //----------------------------------------------------
183 // If there is no dimm on the system, do fatal exit
184 //----------------------------------------------------
185 if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
186 PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
191 //----------------------------------------------------------------
193 //----------------------------------------------------------------
194 AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
195 for (Node = 0; Node < NodeCnt; Node++) {
196 if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
201 //----------------------------------------------------------------
203 //----------------------------------------------------------------
204 AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
205 if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
209 //----------------------------------------------------------------
210 // Before Training Table values
211 //----------------------------------------------------------------
212 for (Node = 0; Node < NodeCnt; Node++) {
213 MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
216 //----------------------------------------------------------------
217 // Memory Context Restore
218 //----------------------------------------------------------------
219 if (!MemFeatMain.MemRestore (MemMainPtr)) {
220 // Do DQS training only if memory context restore fails
222 //----------------------------------------------------------------
224 //----------------------------------------------------------------
225 MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
226 AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
227 IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) {
228 if (!MemFeatMain.Training (MemMainPtr)) {
232 IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n");
235 //----------------------------------------------------------------
236 // Disable chipselects that fail training
237 //----------------------------------------------------------------
238 MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
239 MemFeatMain.ExcludeDIMM (MemMainPtr);
240 MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
242 //----------------------------------------------------------------
244 //----------------------------------------------------------------
245 AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
246 for (Node = 0; Node < NodeCnt; Node++) {
247 if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
252 //----------------------------------------------------------------
253 // After Training Table values
254 //----------------------------------------------------------------
255 for (Node = 0; Node < NodeCnt; Node++) {
256 MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
259 //----------------------------------------------------------------
261 //----------------------------------------------------------------
262 AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
263 for (Node = 0; Node < NodeCnt; Node++) {
264 if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
269 //----------------------------------------------------------------
271 //----------------------------------------------------------------
272 if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
276 //----------------------------------------------------------------
278 //----------------------------------------------------------------
279 for (Node = 0; Node < NodeCnt; Node++) {
280 if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
281 if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
287 //----------------------------------------------------------------
289 //----------------------------------------------------------------
290 if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
294 //----------------------------------------------------------------
295 // Interleave channels
296 //----------------------------------------------------------------
297 for (Node = 0; Node < NodeCnt; Node++) {
298 if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
299 if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
305 //----------------------------------------------------------------
306 // After Programming Interleave registers
307 //----------------------------------------------------------------
308 for (Node = 0; Node < NodeCnt; Node++) {
309 MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave);
312 //----------------------------------------------------------------
313 // UMA Allocation & UMAMemTyping
314 //----------------------------------------------------------------
315 AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
316 if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
321 //----------------------------------------------------------------
322 if (!MemFeatMain.InitEcc (MemMainPtr)) {
326 //----------------------------------------------------------------
328 //----------------------------------------------------------------
329 AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
330 if (!MemFeatMain.MemClr (MemMainPtr)) {
334 //----------------------------------------------------------------
336 //----------------------------------------------------------------
337 for (Node = 0; Node < NodeCnt; Node++) {
338 if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
339 if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
345 //----------------------------------------------------------------
347 //----------------------------------------------------------------
348 for (Node = 0; Node < NodeCnt; Node++) {
349 if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
354 //----------------------------------------------------------------
355 // After Finalize MCT
356 //----------------------------------------------------------------
357 for (Node = 0; Node < NodeCnt; Node++) {
358 MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT);
361 //----------------------------------------------------------------
362 // Memory Context Save
363 //----------------------------------------------------------------
364 MemFeatMain.MemSave (MemMainPtr);
366 //----------------------------------------------------------------
367 // Memory DMI support
368 //----------------------------------------------------------------
369 if (!MemFeatMain.MemDmi (MemMainPtr)) {
370 return AGESA_CRITICAL;
373 return AGESA_SUCCESS;
376 /*----------------------------------------------------------------------------
379 *----------------------------------------------------------------------------