7 * Platform specific settings for DA DDR2 SO-dimms
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem/Ardk)
12 * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
18 * All rights reserved.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are met:
22 * * Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
28 * its contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
37 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
38 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
40 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 * ***************************************************************************
46 /* This file contains routine that add platform specific support S1g3 */
51 #include "PlatformMemoryConfiguration.h"
54 #include "cpuFamRegisters.h"
59 #define FILECODE PROC_MEM_ARDK_DA_MASDA2_FILECODE
60 /*----------------------------------------------------------------------------
61 * DEFINITIONS AND MACROS
63 *----------------------------------------------------------------------------
66 /*----------------------------------------------------------------------------
67 * TYPEDEFS AND STRUCTURES
69 *----------------------------------------------------------------------------
72 /*----------------------------------------------------------------------------
73 * PROTOTYPES OF LOCAL FUNCTIONS
75 *----------------------------------------------------------------------------
79 *-----------------------------------------------------------------------------
82 *-----------------------------------------------------------------------------
85 STATIC CONST UINT8 ROMDATA DASDdr2CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
86 // Even chip select maps to M[B,A]_CKE[0]
87 // Odd chip select maps to M[B,A]_CKE[1]
88 STATIC CONST UINT8 ROMDATA DASDdr2CKETri[] = {0x55, 0xAA};
89 // Bit 0: M[B,A]0_ODT[0]
90 // Bit 1: M[B,A]1_ODT[0]
91 // Bit 2: M[B,A]0_ODT[1]
92 // Bit 3: M[B,A]1_ODT[1]
93 STATIC CONST UINT8 ROMDATA DASDdr2ODTTri[] = {0x01, 0x04, 0x02, 0x08};
94 // Bit 0: M[B,A]0_CS_H/L[0]
95 // Bit 1: M[B,A]0_CS_H/L[1]
96 // Bit 2: M[B,A]0_CS_H/L[2]
97 // Bit 3: M[B,A]0_CS_H/L[3]
98 STATIC CONST UINT8 ROMDATA DASDdr2CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
100 /* -----------------------------------------------------------------------------*/
103 * This is function sets the platform specific settings for DA DDR2 SO-dimms
106 * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
107 * @param[in] SocketID Socket number
108 * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
110 * @return AGESA_SUCCESS
111 * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
112 * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
113 * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
114 * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
115 * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
116 * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
117 * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
118 * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
119 * @return CurrentChannel->SlowMode Slow Mode
126 IN OUT MEM_DATA_STRUCT *MemData,
128 IN OUT CH_DEF_STRUCT *CurrentChannel
131 STATIC CONST PSCFG_ENTRY PSCfg[] = {
132 {DDR400_FREQUENCY, 0xFF, 0x002F2F2F, 0x10111222},
133 {DDR533_FREQUENCY, 0xFF, 0x002F2F2F, 0x10111222},
134 {DDR667_FREQUENCY, 0xFF, 0x002A2A2A, 0x10111222},
135 {DDR800_FREQUENCY, 0xFF, 0x002A2A2A, 0x10111222},
146 ASSERT (MemData != 0);
147 ASSERT (CurrentChannel != 0);
152 if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
153 return AGESA_UNSUPPORTED;
155 if (CurrentChannel->TechType != DDR2_TECHNOLOGY) {
156 return AGESA_UNSUPPORTED;
158 if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) {
159 return AGESA_UNSUPPORTED;
163 Loads = CurrentChannel->Loads;
164 Ranks = CurrentChannel->Ranks;
165 Speed = CurrentChannel->DCTPtr->Timings.Speed;
166 SlowMode = FALSE; // 1T
168 for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
169 if (Speed == PSCfg[i].Speed) {
170 if (Loads <= PSCfg[i].Loads) {
171 AddrTmgCTL = PSCfg[i].AddrTmg;
172 DctOdcCtl = PSCfg[i].Odc;
177 ASSERT (i < GET_SIZE_OF (PSCfg));
180 // Overrides and/or exceptions
183 if ((Speed == DDR533_FREQUENCY) && (Ranks == 2)) {
184 AddrTmgCTL = 0x002C2C2C;
185 } else if ((Speed == DDR667_FREQUENCY) && (Ranks == 1)) {
186 AddrTmgCTL = 0x00272727;
187 } else if ((Speed == DDR667_FREQUENCY) && (Ranks == 2)) {
188 AddrTmgCTL = 0x00002828;
189 SlowMode = TRUE; // 2T
190 } else if ((Speed == DDR800_FREQUENCY) && (Ranks == 1)) {
191 AddrTmgCTL = 0x00292929;
192 } else if ((Speed == DDR800_FREQUENCY) && (Ranks == 2)) {
193 AddrTmgCTL = 0x00002F2F;
194 SlowMode = TRUE; // 2T
197 CurrentChannel->MemClkDisMap = (UINT8 *) DASDdr2CLKDis;
198 CurrentChannel->CKETriMap = (UINT8 *) DASDdr2CKETri;
199 CurrentChannel->ODTTriMap = (UINT8 *) DASDdr2ODTTri;
200 CurrentChannel->ChipSelTriMap = (UINT8 *) DASDdr2CSTri;
201 CurrentChannel->DctAddrTmg = AddrTmgCTL;
202 CurrentChannel->DctOdcCtl = DctOdcCtl;
203 CurrentChannel->SlowMode = SlowMode;
205 return AGESA_SUCCESS;