5 * AMD AGESA Basic Level Public APIs
7 * Contains basic Level Initialization routines.
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: Interface
12 * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
15 /*****************************************************************************
17 * Copyright (C) 2012 Advanced Micro Devices, Inc.
18 * All rights reserved.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are met:
22 * * Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
28 * its contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
37 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
38 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
40 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 ******************************************************************************
46 /*----------------------------------------------------------------------------------------
47 * M O D U L E S U S E D
48 *----------------------------------------------------------------------------------------
54 #include "cpuRegisters.h"
55 #include "cpuServices.h"
56 #include "cpuPostInit.h"
57 #include "AdvancedApi.h"
58 #include "heapManager.h"
59 #include "CommonInits.h"
60 #include "cpuServices.h"
61 #include "GnbInterface.h"
63 #include "CreateStruct.h"
67 #define FILECODE PROC_COMMON_AMDINITPOST_FILECODE
68 /*----------------------------------------------------------------------------------------
69 * D E F I N I T I O N S A N D M A C R O S
70 *----------------------------------------------------------------------------------------
74 /*----------------------------------------------------------------------------------------
75 * T Y P E D E F S A N D S T R U C T U R E S
76 *----------------------------------------------------------------------------------------
80 /*----------------------------------------------------------------------------------------
81 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
82 *----------------------------------------------------------------------------------------
85 AmdPostPlatformConfigInit (
86 IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
87 IN OUT AMD_CONFIG_PARAMS *StdHeader
91 /*----------------------------------------------------------------------------------------
92 * E X P O R T E D F U N C T I O N S
93 *----------------------------------------------------------------------------------------
96 extern BUILD_OPT_CFG UserOptions;
98 /*------------------------------------------------------------------------------------*/
100 * Initialize AmdInitPost stage platform profile and user option input.
102 * @param[in,out] PlatformConfig Platform profile/build option config structure
103 * @param[in,out] StdHeader AMD standard header config param
105 * @retval AGESA_SUCCESS Always Succeeds.
109 AmdPostPlatformConfigInit (
110 IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
111 IN OUT AMD_CONFIG_PARAMS *StdHeader
114 CommonPlatformConfigInit (PlatformConfig, StdHeader);
116 return AGESA_SUCCESS;
120 *---------------------------------------------------------------------------------------
122 * AmdInitPostInitializer
124 * Initializer routine that will be invoked by the wrapper
125 * to initialize the input structure for the AmdInitPost
127 * @param[in, out] IN OUT AMD_POST_PARAMS *PostParamsPtr
129 * @retval AGESA_STATUS
131 *---------------------------------------------------------------------------------------
134 AmdInitPostInitializer (
135 IN AMD_CONFIG_PARAMS *StdHeader,
136 IN OUT AMD_POST_PARAMS *PostParamsPtr
139 AGESA_STATUS AgesaStatus;
140 ALLOCATE_HEAP_PARAMS AllocHeapParams;
142 ASSERT (StdHeader != NULL);
143 ASSERT (PostParamsPtr != NULL);
145 PostParamsPtr->StdHeader = *StdHeader;
147 AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
148 AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
149 AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
150 AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, &PostParamsPtr->StdHeader);
152 if (AgesaStatus == AGESA_SUCCESS) {
153 PostParamsPtr->MemConfig.MemData = (MEM_DATA_STRUCT *) AllocHeapParams.BufferPtr;
154 PostParamsPtr->MemConfig.MemData->ParameterListPtr = &(PostParamsPtr->MemConfig);
155 PostParamsPtr->MemConfig.MemData->StdHeader = PostParamsPtr->StdHeader;
156 AmdPostPlatformConfigInit (&PostParamsPtr->PlatformConfig, &PostParamsPtr->StdHeader);
157 AmdMemInitDataStructDef (PostParamsPtr->MemConfig.MemData, &PostParamsPtr->PlatformConfig);
163 *---------------------------------------------------------------------------------------
165 * AmdInitPostDestructor
167 * Destruct routine that provide a chance if something need to be done
168 * before the end of AmdInitPost.
170 * @param[in] StdHeader The standard header.
171 * @param[in] PostParamsPtr AMD init post param.
173 * @retval AGESA_STATUS
175 *---------------------------------------------------------------------------------------
178 AmdInitPostDestructor (
179 IN AMD_CONFIG_PARAMS *StdHeader,
180 IN AMD_POST_PARAMS *PostParamsPtr
184 ASSERT (PostParamsPtr != NULL);
186 PostParamsPtr->StdHeader = *StdHeader;
187 PostParamsPtr->MemConfig.MemData->StdHeader = *StdHeader;
190 // AmdMemAuto completed. Here, release heap space which is used for memory init.
192 MemAmdFinalize (PostParamsPtr->MemConfig.MemData);
193 HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader);
196 // AmdCpuPost completed.
198 if (PostParamsPtr->MemConfig.SysLimit != 0) {
199 // WBINVD can only be executed when memory is available
200 FinalizeAtPost (StdHeader);
203 return AGESA_SUCCESS;
206 /*---------------------------------------------------------------------------------------*/
208 * Main entry point for the AMD_INIT_POST function.
210 * This entry point is responsible for initializing all system memory,
211 * gathering important data out of the pre-memory cache storage into a
212 * temporary holding buffer in main memory. After that APs will be
213 * shutdown in preparation for the host environment to take control.
214 * Note: pre-memory stack will be disabled also.
216 * @param[in,out] PostParams Required input parameters for the AMD_INIT_POST
219 * @return Aggregated status across all internal AMD POST calls invoked.
224 IN OUT AMD_POST_PARAMS *PostParams
227 AGESA_STATUS AgesaStatus;
228 AGESA_STATUS AmdInitPostStatus;
229 WARM_RESET_REQUEST Request;
230 UINT8 PrevRequestBit;
233 AGESA_TESTPOINT (TpIfAmdInitPostEntry, &PostParams->StdHeader);
234 IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitPost: Start\n\n");
235 IDS_PERF_TIME_MEASURE (&PostParams->StdHeader);
237 ASSERT (PostParams != NULL);
238 AmdInitPostStatus = AGESA_SUCCESS;
239 PrevRequestBit = FALSE;
240 PrevStateBits = WR_STATE_COLD;
242 IDS_OPTION_HOOK (IDS_INIT_POST_BEFORE, PostParams, &PostParams->StdHeader);
244 // If a previously requested warm reset cannot be triggered in the
245 // current stage, store the previous state of request and reset the
246 // request struct to the current post stage
247 GetWarmResetFlag (&PostParams->StdHeader, &Request);
248 if (Request.RequestBit == TRUE) {
249 if (Request.StateBits >= Request.PostStage) {
250 PrevRequestBit = Request.RequestBit;
251 PrevStateBits = Request.StateBits;
252 Request.RequestBit = FALSE;
253 Request.StateBits = Request.PostStage - 1;
254 SetWarmResetFlag (&PostParams->StdHeader, &Request);
258 AgesaStatus = GnbInitAtPost (PostParams);
259 if (AgesaStatus > AmdInitPostStatus) {
260 AmdInitPostStatus = AgesaStatus;
263 IDS_HDT_CONSOLE (MAIN_FLOW, "AmdMemAuto: Start\n");
264 AgesaStatus = AmdMemAuto (PostParams->MemConfig.MemData);
265 IDS_HDT_CONSOLE (MAIN_FLOW, "AmdMemAuto: End\n");
266 if (AgesaStatus > AmdInitPostStatus) {
267 AmdInitPostStatus = AgesaStatus;
270 if (AgesaStatus != AGESA_FATAL) {
273 AgesaStatus = CheckBistStatus (&PostParams->StdHeader);
274 if (AgesaStatus > AmdInitPostStatus) {
275 AmdInitPostStatus = AgesaStatus;
279 // P-State data gathered, then, Relinquish APs
281 IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuPost: Start\n");
282 AgesaStatus = AmdCpuPost (&PostParams->StdHeader, &PostParams->PlatformConfig);
283 IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuPost: End\n");
284 if (AgesaStatus > AmdInitPostStatus) {
285 AmdInitPostStatus = AgesaStatus;
289 GetWarmResetFlag (&PostParams->StdHeader, &Request);
290 // If a warm reset is requested in the current post stage, trigger the
291 // warm reset and ignore the previous request
292 if (Request.RequestBit == TRUE) {
293 if (Request.StateBits < Request.PostStage) {
294 AgesaDoReset (WARM_RESET_WHENEVER, &PostParams->StdHeader);
297 // Otherwise, if there's a previous request, restore it
298 // so that the subsequent post stage can trigger the warm reset
299 if (PrevRequestBit == TRUE) {
300 Request.RequestBit = PrevRequestBit;
301 Request.StateBits = PrevStateBits;
302 SetWarmResetFlag (&PostParams->StdHeader, &Request);
306 AgesaStatus = GnbInitAtPostAfterDram (PostParams);
307 if (AgesaStatus > AmdInitPostStatus) {
308 AmdInitPostStatus = AgesaStatus;
311 IDS_OPTION_HOOK (IDS_INIT_POST_AFTER, PostParams, &PostParams->StdHeader);
313 IDS_PERF_TIME_MEASURE (&PostParams->StdHeader);
314 AGESA_TESTPOINT (TpIfAmdInitPostExit, &PostParams->StdHeader);
315 IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitPost: End\n\n");
316 IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer Start ...\n\n");
318 //For Heap will be relocate to new address in next stage, flush out debug print buffer if needed
319 IDS_HDT_CONSOLE_FLUSH_BUFFER (&PostParams->StdHeader);
321 // WARNING: IDT will be moved from local cache to temp memory, so restore IDTR for BSP here
322 IDS_EXCEPTION_TRAP (IDS_IDT_RESTORE_IDTR_FOR_BSC, NULL, &PostParams->StdHeader);
323 // Copies BSP heap content to RAM, and it should be at the end of AmdInitPost
324 AgesaStatus = CopyHeapToTempRamAtPost (&(PostParams->StdHeader));
325 if (AgesaStatus > AmdInitPostStatus) {
326 AmdInitPostStatus = AgesaStatus;
328 PostParams->StdHeader.HeapStatus = HEAP_TEMP_MEM;
330 // Check for Cache As Ram Corruption
331 IDS_CAR_CORRUPTION_CHECK (&PostParams->StdHeader);
333 // At the end of AmdInitPost, set StateBits to POST to allow any warm reset that occurs outside
334 // of AGESA to be recognized by IsWarmReset()
335 GetWarmResetFlag (&PostParams->StdHeader, &Request);
336 Request.StateBits = Request.PostStage;
337 SetWarmResetFlag (&PostParams->StdHeader, &Request);
339 return AmdInitPostStatus;