5 * AMD CPU Reset API, and related functions and structures.
7 * Contains code that initialized the CPU after early reset.
9 * @xrefitem bom "File Content Label" "Release Content"
12 * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $
16 ******************************************************************************
18 * Copyright (C) 2012 Advanced Micro Devices, Inc.
19 * All rights reserved.
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22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
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29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ******************************************************************************
46 #ifndef _CPU_EARLY_INIT_H_
47 #define _CPU_EARLY_INIT_H_
50 /*---------------------------------------------------------------------------------------
51 * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
52 *---------------------------------------------------------------------------------------
54 AGESA_FORWARD_DECLARATION (CPU_CORE_LEVELING_FAMILY_SERVICES);
56 /*---------------------------------------------------------------------------------------
57 * D E F I N I T I O N S A N D M A C R O S
58 *---------------------------------------------------------------------------------------
60 //----------------------------------------------------------------------------
61 // CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
63 //----------------------------------------------------------------------------
64 #define CPU_BRAND_ID_LENGTH 48 // Total number of characters supported
65 #define LOW_NODE_DEVICEID 24
66 #define NB_CAPABILITIES 0xE8 //Function 3 Registers
67 //----------------------------------------------------------------------------
68 // CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
70 //----------------------------------------------------------------------------
71 /* All lengths are in bytes */
72 #define MICROCODE_TRIADE_SIZE 28
73 #define MICROCODE_HEADER_LENGTH 64
76 * @page ucodeflag Microcode Patches Signature Guide
78 * We mark patches in the ROM with a signature so that they can be easily found
80 * @anchor Microcode Patch Signature
81 * @li @e Microcode Patch Signature @n
82 * Microcode patches are marked by adding a signature before patches in the ROM image to
83 * help identify where they are located.
84 * There're two kind of signatures. One is '$UCODE2K', it indicates there's a following patch with 2K size.
85 * The other is '$UCODE4K', it indicates there's a following patch with 4K size.
86 * If you want to know the patch level / equivalent ID, please consult the BKDG for patch header format.
90 /// Microcode patch flag for replacement
92 IN UINT8 MicrocodePatchesFlag[8]; ///< a flag followed by microcode
93 } MICROCODE_PATCHES_FLAG;
95 #define UCODE_2K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '2', 'K'}};
96 #define UCODE_4K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '4', 'K'}};
97 #define UCODE_VS_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', 'V', 'S'}};
99 /* Offsets in UCODE PATCH Header */
100 /* Note: Header is 64 bytes */
101 #define DATE_CODE_OFFSET 0 // 4 bytes
102 #define PATCH_ID 4 // 4 bytes
103 #define MICROCODE_PATH_DATA_ID 8 // 2 bytes
104 #define MICROCODE_PATCH_DATA_LENGTH 10 // 1 byte
105 #define MICROCODE_PATCH_DATA_CHECKSUM 12 // 4 bytes
106 #define CHIPSET_1_DEVICE_ID 16 // 4 bytes
107 #define CHIPSET_2_DEVICE_ID 20 // 4 bytes
108 #define PROCESSOR_REV_ID 24 // 2 bytes
109 #define CHIPSET_1_REV_ID 26 // 1 byte
110 #define CHIPSET_2_REV_ID 27 // 1 byte
112 #define MICROCODE_PATCH_2K_SIZE 2048
113 #define MICROCODE_PATCH_4K_SIZE 4096
114 /*---------------------------------------------------------------------------------------
115 * T Y P E D E F S, S T R U C T U R E S, E N U M S
116 *---------------------------------------------------------------------------------------
118 //----------------------------------------------------------------------------
119 // CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
121 //----------------------------------------------------------------------------
122 /// A structure representing BrandId[15:0] from
123 /// CPUID Fn8000_0001_EBX
125 UINT8 String1:4; ///< An index to a string value used to create the name string
126 UINT8 String2:4; ///< An index to a string value used to create the name string
127 UINT8 Page:1; ///< An index to the appropriate page for the String1, String2, and Model values
128 UINT8 Model:7; ///< A field used to create the model number in the name string
129 UINT8 Socket:4; ///< Specifies the package type
130 UINT8 Cores:4; ///< Identifies how many physical cores are present
131 } AMD_CPU_BRAND_DATA;
133 /// A structure containing string1 and string2 values
134 /// as well as information pertaining to their usage
136 IN UINT8 Cores; ///< Appropriate number of physical cores
137 IN UINT8 Page; ///< This string's page number
138 IN UINT8 Index; ///< String index
139 IN UINT8 Socket; ///< Package type information
140 IN CONST CHAR8 *Stringstart; ///< The literal string
141 IN UINT8 Stringlength; ///< Number of characters in the string
144 /// An entire CPU brand table.
146 UINT8 NumberOfEntries; ///< The number of entries in the table.
147 CONST AMD_CPU_BRAND *Table; ///< The table entries.
150 //----------------------------------------------------------------------------
151 // CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
153 //----------------------------------------------------------------------------
154 /// Microcode patch field definitions
156 UINT32 DateCode; ///< Date of patch creation
157 UINT32 PatchID; ///< Patch level
158 UINT16 MicrocodePatchDataID; ///< Internal use only
159 UINT8 MicrocodePatchDataLength; ///< Internal use only
160 UINT8 InitializationFlag; ///< Internal use only
161 UINT32 MicrocodePatchDataChecksum; ///< Doubleword sum of data block
162 UINT32 Chipset1DeviceID; ///< Device ID of 1st HT device to match
163 UINT32 Chipset2DeviceID; ///< Device ID of 2nd HT device to match
164 UINT16 ProcessorRevisionID; ///< Equivalent ID
165 UINT8 Chipset1RevisionID; ///< Revision level of 1st HT device to match
166 UINT8 Chipset2RevisionID; ///< Revision level of 2nd HT device to match
167 UINT8 BiosApiRevision; ///< BIOS INT 15 API revision required
168 UINT8 Reserved1[3]; ///< Reserved
169 UINT32 MatchRegister0; ///< Internal use only
170 UINT32 MatchRegister1; ///< Internal use only
171 UINT32 MatchRegister2; ///< Internal use only
172 UINT32 MatchRegister3; ///< Internal use only
173 UINT32 MatchRegister4; ///< Internal use only
174 UINT32 MatchRegister5; ///< Internal use only
175 UINT32 MatchRegister6; ///< Internal use only
176 UINT32 MatchRegister7; ///< Internal use only
177 UINT8 PatchDataBlock[896]; ///< Raw patch data
178 UINT8 Reserved2[896]; ///< Reserved
179 UINT8 X86CodePresent; ///< Boolean to determine if executable code exists
180 UINT8 X86CodeEntry[191]; ///< Code to execute if X86CodePresent != 0
183 /// Two kilobyte array containing the raw
184 /// microcode patch binary data
186 IN UINT8 MicrocodePatches[MICROCODE_PATCH_2K_SIZE]; ///< 2k UINT8 elements
189 /// Four kilobyte array containing the raw
190 /// microcode patch binary data
192 IN UINT8 MicrocodePatches[MICROCODE_PATCH_4K_SIZE]; ///< 4k UINT8 elements
193 } MICROCODE_PATCHES_4K;
196 * Set down core register
198 * @CpuServiceInstances
200 * @param[in] FamilySpecificServices The current Family Specific Services.
201 * @param[in] Socket Socket ID.
202 * @param[in] Module Module ID in socket.
203 * @param[in] LeveledCores Number of core.
204 * @param[in] CoreLevelMode Core level mode.
205 * @param[in] StdHeader Header for library and services.
207 * @retval TRUE Down Core register is updated.
208 * @retval FALSE Down Core register is not updated.
210 typedef BOOLEAN (F_CPU_SET_DOWN_CORE_REGISTER) (
211 IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
214 IN UINT32 *LeveledCores,
215 IN CORE_LEVELING_TYPE CoreLevelMode,
216 IN AMD_CONFIG_PARAMS *StdHeader
219 /// Reference to a method
220 typedef F_CPU_SET_DOWN_CORE_REGISTER *PF_CPU_SET_DOWN_CORE_REGISTER;
223 * Provide the interface to the Core Leveling Family Specific Services.
225 * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
226 * Each supported Family must provide an implementation for all methods in this interface, even if the
227 * implementation is a CommonReturn().
229 struct _CPU_CORE_LEVELING_FAMILY_SERVICES { // See Forward Declaration above
230 UINT16 Revision; ///< Interface version
232 PF_CPU_SET_DOWN_CORE_REGISTER SetDownCoreRegister; ///< Method: Set down core register.
235 //----------------------------------------------------------------------------
236 // CPU PERFORM EARLY INIT ON CORE
238 //----------------------------------------------------------------------------
240 #define PERFORM_EARLY_WARM_RESET 0x1 // bit 0 --- the related function needs to be run if it's warm reset
241 #define PERFORM_EARLY_COLD_BOOT 0x2 // bit 1 --- the related function needs to be run if it's cold boot
243 #define PERFORM_EARLY_ANY_CONDITION 0xFFFFFFFF // the related function always needs to be run
244 /*---------------------------------------------------------------------------------------
245 * F U N C T I O N P R O T O T Y P E
246 *---------------------------------------------------------------------------------------
249 // These are P U B L I C functions, used by IBVs
252 IN AMD_CONFIG_PARAMS *StdHeader,
253 IN PLATFORM_CONFIGURATION *PlatformConfig
256 // These are P U B L I C functions, used by AGESA
258 SetBrandIdRegisters (
259 IN OUT AMD_CONFIG_PARAMS *StdHeader
263 PmInitializationAtEarly (
264 IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
265 IN AMD_CONFIG_PARAMS *StdHeader
270 IN OUT AMD_CONFIG_PARAMS *StdHeader
274 GetPatchEquivalentId (
275 IN OUT UINT16 *ProcessorEquivalentId,
276 IN OUT AMD_CONFIG_PARAMS *StdHeader
281 IN MICROCODE_PATCH *MicrocodePatchPtr,
282 IN UINT16 ProcessorEquivalentId,
283 IN OUT AMD_CONFIG_PARAMS *StdHeader
287 GetMicrocodeVersion (
288 OUT UINT32 *pMicrocodeVersion,
289 IN OUT AMD_CONFIG_PARAMS *StdHeader
293 AmdCpuEarlyInitializer (
294 IN AMD_CONFIG_PARAMS *StdHeader,
295 IN PLATFORM_CONFIGURATION *PlatformConfig,
296 IN OUT AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
301 IN AMD_CONFIG_PARAMS *StdHeader
304 #endif // _CPU_EARLY_INIT_H_