5 * AMD Family_15 Power Management related registers defination
7 * @xrefitem bom "File Content Label" "Release Content"
9 * @e sub-project: CPU/Family/0x15
10 * @e \$Revision: 52710 $ @e \$Date: 2011-05-10 15:58:53 -0600 (Tue, 10 May 2011) $
14 ******************************************************************************
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41 ******************************************************************************
44 #ifndef _CPUF15POWERMGMT_H_
45 #define _CPUF15POWERMGMT_H_
48 * Family 15h CPU Power Management MSR definitions
53 /* Last Branch From IP Register 0x000001DB */
54 #define MSR_BR_FROM 0x000001DB
56 /* P-state Current Limit Register 0xC0010061 */
57 #define MSR_PSTATE_CURRENT_LIMIT 0xC0010061 // F15 Shared
59 /// Pstate Current Limit MSR Register
61 UINT64 CurPstateLimit:3; ///< Current Pstate Limit
62 UINT64 :1; ///< Reserved
63 UINT64 PstateMaxVal:3; ///< Pstate Max Value
64 UINT64 :57; ///< Reserved
68 /* P-state Control Register 0xC0010062 */
69 #define MSR_PSTATE_CTL 0xC0010062 // F15 Shared
71 /// Pstate Control MSR Register
73 UINT64 PstateCmd:3; ///< Pstate change command
74 UINT64 :61; ///< Reserved
78 /* P-state Status Register 0xC0010063 */
79 #define MSR_PSTATE_STS 0xC0010063
81 /// Pstate Status MSR Register
83 UINT64 CurPstate:3; ///< Current Pstate
84 UINT64 :61; ///< Reserved
88 /* P-state Registers 0xC001006[B:4] */
89 #define MSR_PSTATE_0 0xC0010064
90 #define MSR_PSTATE_1 0xC0010065
91 #define MSR_PSTATE_2 0xC0010066
92 #define MSR_PSTATE_3 0xC0010067
93 #define MSR_PSTATE_4 0xC0010068
94 #define MSR_PSTATE_5 0xC0010069
95 #define MSR_PSTATE_6 0xC001006A
96 #define MSR_PSTATE_7 0xC001006B
98 #define PS_REG_BASE MSR_PSTATE_0 /* P-state Register base */
99 #define PS_MAX_REG MSR_PSTATE_7 /* Maximum P-State Register */
100 #define PS_MIN_REG MSR_PSTATE_0 /* Minimum P-State Register */
101 #define NM_PS_REG 8 /* number of P-state MSR registers */
103 /// P-state MSR with common field
105 UINT64 :63; ///< CpuFid
106 UINT64 PsEnable:1; ///< Pstate Enable
110 /* C-state Address Register 0xC0010073 */
111 #define MSR_CSTATE_ADDRESS 0xC0010073
113 /// C-state Address MSR Register
115 UINT64 CstateAddr:16; ///< C-state address
116 UINT64 :48; ///< Reserved
117 } CSTATE_ADDRESS_MSR;
121 * Family 15h CPU Power Management PCI definitions
125 /* Extended Memory Controller Configuration Low Register F2x1B0 */
126 #define EXT_MEMCTRL_CFG_LOW_REG 0x1B0
128 /// Extended Memory Controller Configuration Low PCI Register
130 UINT32 AdapPrefMissRatio:2; ///< Adaptive prefetch miss ratio
131 UINT32 AdapPrefPositiveStep:2; ///< Adaptive prefetch positive step
132 UINT32 AdapPrefNegativeStep:2; ///< Adaptive prefetch negative step
133 UINT32 :2; ///< Reserved
134 UINT32 CohPrefPrbLmt:3; ///< Coherent prefetch probe limit
135 UINT32 DisIoCohPref:1; ///< Disable coherent prefetched for IO
136 UINT32 EnSplitDctLimits:1; ///< Split DCT write limits enable
137 UINT32 SpecPrefDis:1; ///< Speculative prefetch disable
138 UINT32 SpecPrefMis:1; ///< Speculative prefetch predict miss
139 UINT32 SpecPrefThreshold:3; ///< Speculative prefetch threshold
140 UINT32 :4; ///< Reserved
141 UINT32 PrefFourConf:3; ///< Prefetch four-ahead confidence
142 UINT32 PrefFiveConf:3; ///< Prefetch five-ahead confidence
143 UINT32 DcqBwThrotWm:4; ///< Dcq bandwidth throttle watermark
144 } EXT_MEMCTRL_CFG_LOW_REGISTER;
147 /* Hardware thermal control register F3x64 */
150 /// Hardware Thermal Control PCI Register
152 UINT32 HtcEn:1; ///< HTC Enable
153 UINT32 :3; ///< Reserved
154 UINT32 HtcAct:1; ///< HTC Active State
155 UINT32 HtcActSts:1; ///< HTC Active Status
156 UINT32 PslApicHiEn:1; ///< P-state limit higher APIC int enable
157 UINT32 PslApicLoEn:1; ///< P-state limit lower APIC int enable
158 UINT32 :8; ///< Reserved
159 UINT32 HtcTmpLmt:7; ///< HTC temperature limit
160 UINT32 HtcSlewSel:1; ///< HTC slew-controlled temp select
161 UINT32 HtcHystLmt:4; ///< HTC hysteresis
162 UINT32 HtcPstateLimit:3; ///< HTC P-state limit select
163 UINT32 :1; ///< Reserved
167 /* Software P-state limit register F3x68 */
168 #define SW_PS_LIMIT_REG 0x68
170 /// Software P-state Limit PCI Register
172 UINT32 :5; ///< Reserved
173 UINT32 SwPstateLimitEn:1; ///< Software P-state limit enable
174 UINT32 :22; ///< Reserved
175 UINT32 SwPstateLimit:3; ///< HTC P-state limit select
176 UINT32 :1; ///< Reserved
177 } SW_PS_LIMIT_REGISTER;
179 /* ACPI Power State Control Registers F3x84:80 */
181 /// System Management Action Field (SMAF) Register
183 UINT8 CpuPrbEn:1; ///< CPU direct probe enable
184 UINT8 NbLowPwrEn:1; ///< Northbridge low-power enable
185 UINT8 NbGateEn:1; ///< Northbridge gate enable
186 UINT8 Reserved:2; ///< Reserved
187 UINT8 ClkDivisor:3; ///< Clock divisor
190 /// union type for ACPI State SMAF setting
192 UINT8 SMAFValue; ///< SMAF raw value
193 SMAF_REGISTER SMAF; ///< SMAF structure
196 /// ACPI Power State Control Register F3x80
198 ACPI_STATE_SMAF C2; ///< [7:0] SMAF Code 000b - C2
199 ACPI_STATE_SMAF C1eLinkInit; ///< [15:8] SMAF Code 001b - C1e or Link init
200 ACPI_STATE_SMAF SmafAct2; ///< [23:16] SMAF Code 010b
201 ACPI_STATE_SMAF S1; ///< [31:24] SMAF Code 011b - S1
202 } ACPI_PSC_0_REGISTER;
204 /// ACPI Power State Control Register F3x84
206 ACPI_STATE_SMAF S3; ///< [7:0] SMAF Code 100b - S3
207 ACPI_STATE_SMAF Throttling; ///< [15:8] SMAF Code 101b - Throttling
208 ACPI_STATE_SMAF S4S5; ///< [23:16] SMAF Code 110b - S4/S5
209 ACPI_STATE_SMAF C1; ///< [31:24] SMAF Code 111b - C1
210 } ACPI_PSC_4_REGISTER;
213 /* Popup P-state Register F3xA8 */
214 #define POPUP_PSTATE_REG 0xA8
215 #define POPUP_PSTATE_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, POPUP_PSTATE_REG))
217 /// Popup P-state Register
219 UINT32 :29; ///< Reserved
220 UINT32 PopDownPstate:3; ///< PopDownPstate
221 } POPUP_PSTATE_REGISTER;
224 /* Clock Power/Timing Control 2 Register F3xDC */
225 #define CPTC2_REG 0xDC
226 #define CPTC2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC2_REG))
228 /// Clock Power Timing Control 2 PCI Register
230 UINT32 :8; ///< Reserved
231 UINT32 PstateMaxVal:3; ///< P-state maximum value
232 UINT32 :1; ///< Reserved
233 UINT32 NbsynPtrAdj:3; ///< NB/Core sync FIFO ptr adjust
234 UINT32 :1; ///< Reserved
235 UINT32 CacheFlushOnHaltCtl:3; ///< Cache flush on halt control
236 UINT32 CacheFlushOnHaltTmr:7; ///< Cache flush on halt timer
237 UINT32 IgnCpuPrbEn:1; ///< ignore CPU probe enable
238 UINT32 :5; ///< Reserved
239 } CLK_PWR_TIMING_CTRL2_REGISTER;
242 /* Core Performance Boost Control Register D18F4x15C */
243 #define CPB_CTRL_REG 0x15C
244 #define CPB_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPB_CTRL_REG))
246 /// Core Performance Boost Control Register of Family 15h common aceess
248 UINT32 BoostSrc:2; ///< Boost source
249 UINT32 NumBoostStates:3; ///< Number of boosted states
250 UINT32 :2; ///< Reserved
251 UINT32 ApmMasterEn:1; ///< APM master enable
252 UINT32 :23; ///< Reserved
253 UINT32 BoostLock:1; ///<
254 } F15_CPB_CTRL_REGISTER;
257 #define NM_NB_PS_REG 4 /* Number of NB P-state registers */
259 /* Northbridge P-state */
260 #define NB_PSTATE_0 0x160
261 #define NB_PSTATE_0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_0))
263 #define NB_PSTATE_1 0x164
264 #define NB_PSTATE_1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_1))
266 #define NB_PSTATE_2 0x168
267 #define NB_PSTATE_2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_2))
269 #define NB_PSTATE_3 0x16C
270 #define NB_PSTATE_3_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_3))
273 /* Northbridge P-state Status */
274 #define F15_NB_PSTATE_CTRL 0x170
275 #define F15_NB_PSTATE_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, F15_NB_PSTATE_CTRL))
277 /// Northbridge P-state Control Register
279 UINT32 NbPstateMaxVal:2; ///< NB P-state maximum value
280 UINT32 :1; ///< Reserved
281 UINT32 NbPstateLo:2; ///< NB P-state low
282 UINT32 :1; ///< Reserved
283 UINT32 NbPstateHi:2; ///< NB P-state high
284 UINT32 :1; ///< Reserved
285 UINT32 NbPstateThreshold:3; ///< NB P-state threshold
286 UINT32 :1; ///< Reserved
287 UINT32 NbPstateDisOnP0:1; ///< NB P-state disable on P0
288 UINT32 SwNbPstateLoDis:1; ///< Software NB P-state low disable
289 UINT32 :17; ///< Reserved
290 } F15_NB_PSTATE_CTRL_REGISTER;
293 #endif /* _CPUF15POWERMGMT_H */