5 * AMD Family_15 PCI tables with values as defined in BKDG
7 * @xrefitem bom "File Content Label" "Release Content"
9 * @e sub-project: CPU/Family/0x15
10 * @e \$Revision: 59440 $ @e \$Date: 2011-09-22 19:44:44 -0600 (Thu, 22 Sep 2011) $
14 ******************************************************************************
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41 ******************************************************************************
44 /*----------------------------------------------------------------------------------------
45 * M O D U L E S U S E D
46 *----------------------------------------------------------------------------------------
50 #include "cpuRegisters.h"
56 #define FILECODE PROC_CPU_FAMILY_0X15_CPUF15PCITABLES_FILECODE
58 /*----------------------------------------------------------------------------------------
59 * D E F I N I T I O N S A N D M A C R O S
60 *----------------------------------------------------------------------------------------
63 /*----------------------------------------------------------------------------------------
64 * T Y P E D E F S A N D S T R U C T U R E S
65 *----------------------------------------------------------------------------------------
68 /*----------------------------------------------------------------------------------------
69 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
70 *----------------------------------------------------------------------------------------
73 /*----------------------------------------------------------------------------------------
74 * E X P O R T E D F U N C T I O N S
75 *----------------------------------------------------------------------------------------
79 // ----------------------
81 STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15PciRegisters[] =
83 // F2x1B0 - Extended Memory Controller Configuration Low
84 // bits[10:8], CohPrefPrbLmt = 1
88 AMD_FAMILY_15, // CpuFamily
89 AMD_F15_ALL // CpuRevision
91 {AMD_PF_ALL}, // platformFeatures
93 MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address
94 0x00000100, // regData
95 0x00000700, // regMask
99 // Function 3 - Misc. Control
101 // F3x6C - Data Buffer Count
102 // bits[30:28] IsocRspDBC = 1
103 // bits[18:16] UpRspDBC = 1
104 // bits[7:6] DnRspDBC = 1
105 // bits[5:4] DnReqDBC = 1
106 // bits[2:0] UpReqDBC = 2
110 AMD_FAMILY_15, // CpuFamily
111 AMD_F15_ALL // CpuRevision
113 {AMD_PF_ALL}, // platformFeatures
115 MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C), // Address
116 0x10010052, // regData
117 0x700700F7, // regMask
120 // F3xA0 - Power Control Miscellaneous
121 // bits[13:11] PllLockTime = 1
125 AMD_FAMILY_15, // CpuFamily
126 AMD_F15_ALL // CpuRevision
128 {AMD_PF_ALL}, // platformFeatures
130 MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
131 0x00000800, // regData
132 0x00003800, // regMask
135 // F3xA4 - Reported Temperature Control
136 // bits[12:8] PerStepTimeDn = 0x0F
137 // bits[7] TmpSlewDnEn = 1
138 // bits[6:5] TmpMaxDiffUp = 3
139 // bits[4:0] PerStepTimeUp = 0x0F
143 AMD_FAMILY_15, // CpuFamily
144 AMD_F15_ALL // CpuRevision
146 {AMD_PF_ALL}, // platformFeatures
148 MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4), // Address
149 0x00000FEF, // regData
150 0x00001FFF, // regMask
153 // F3xDC - Clock Power Timing Control 2
154 // bit [26] IgnCpuPrbEn = 1
155 // bits[14:12] NbsynPtrAdj = 5
159 AMD_FAMILY_15, // CpuFamily
160 AMD_F15_ALL // CpuRevision
162 {AMD_PF_ALL}, // platformFeatures
164 MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
165 0x04005000, // regData
166 0x04007000, // regMask
169 // F3x1CC - IBS Control
170 // bits[8] LvtOffsetVal = 1
171 // bits[3:0] LvtOffset = 0
175 AMD_FAMILY_15, // CpuFamily
176 AMD_F15_ALL // CpuRevision
178 {AMD_PF_ALL}, // platformFeatures
180 MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC), // Address
181 0x00000100, // regData
182 0x0000010F, // regMask
185 // F4x15C - Core Performance Boost Control
186 // bits[1:0] BoostSrc = 0
190 AMD_FAMILY_15, // CpuFamily
191 AMD_F15_ALL // CpuRevision
193 {AMD_PF_ALL}, // platformFeatures
195 MAKE_SBDFO (0, 0, 24, FUNC_4, 0x15C), // Address
196 0x00000000, // regData
197 0x00000003, // regMask
202 CONST REGISTER_TABLE ROMDATA F15PciRegisterTable = {
204 (sizeof (F15PciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),