5 * AMD Family_15 CPB Initialization
7 * Enables core performance boost.
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: CPU/F15/OR
12 * @e \$Revision: 54493 $ @e \$Date: 2011-06-08 15:21:06 -0600 (Wed, 08 Jun 2011) $
16 ******************************************************************************
18 * Copyright (C) 2012 Advanced Micro Devices, Inc.
19 * All rights reserved.
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22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
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29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ******************************************************************************
46 /*----------------------------------------------------------------------------------------
47 * M O D U L E S U S E D
48 *----------------------------------------------------------------------------------------
52 #include "GeneralServices.h"
53 #include "cpuFamilyTranslation.h"
54 #include "cpuF15PowerMgmt.h"
55 #include "cpuF15OrPowerMgmt.h"
56 #include "cpuFeatures.h"
58 #include "F15PackageType.h"
59 #include "OptionFamily15hEarlySample.h"
64 #define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORCPB_FILECODE
66 /*----------------------------------------------------------------------------------------
67 * D E F I N I T I O N S A N D M A C R O S
68 *----------------------------------------------------------------------------------------
70 extern F15_OR_ES_CPB_SUPPORT F15OrEarlySampleCpbSupport;
71 /*----------------------------------------------------------------------------------------
72 * T Y P E D E F S A N D S T R U C T U R E S
73 *----------------------------------------------------------------------------------------
76 /*----------------------------------------------------------------------------------------
77 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
78 *----------------------------------------------------------------------------------------
81 /*----------------------------------------------------------------------------------------
82 * E X P O R T E D F U N C T I O N S
83 *----------------------------------------------------------------------------------------
86 /*---------------------------------------------------------------------------------------*/
88 * BSC entry point for checking whether or not CPB is supported.
90 * @param[in] CpbServices The current CPU's family services.
91 * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
92 * @param[in] Socket Zero based socket number to check.
93 * @param[in] StdHeader Config handle for library and services.
95 * @retval TRUE CPB is supported.
96 * @retval FALSE CPB is not supported.
101 F15OrIsCpbSupported (
102 IN CPB_FAMILY_SERVICES *CpbServices,
103 IN PLATFORM_CONFIGURATION *PlatformConfig,
105 IN AMD_CONFIG_PARAMS *StdHeader
110 AGESA_STATUS IgnoredSts;
115 GetPciAddress (StdHeader, Socket, 0, &PciAddress, &IgnoredSts);
116 PciAddress.Address.Function = FUNC_4;
117 PciAddress.Address.Register = CPB_CTRL_REG;
118 LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
119 IsEnabled = (BOOLEAN) (((CPB_CTRL_REGISTER *) (&CpbControl))->NumBoostStates != 0);
121 F15OrEarlySampleCpbSupport.F15OrIsCpbSupportedHook (&IsEnabled, StdHeader);
127 /*---------------------------------------------------------------------------------------*/
129 * BSC entry point for for enabling Core Performance Boost.
131 * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
133 * @param[in] CpbServices The current CPU's family services.
134 * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
135 * @param[in] EntryPoint Current CPU feature dispatch point.
136 * @param[in] Socket Zero based socket number to check.
137 * @param[in] StdHeader Config handle for library and services.
139 * @retval AGESA_SUCCESS Always succeeds.
145 IN CPB_FAMILY_SERVICES *CpbServices,
146 IN PLATFORM_CONFIGURATION *PlatformConfig,
147 IN UINT64 EntryPoint,
149 IN AMD_CONFIG_PARAMS *StdHeader
156 AGESA_STATUS IgnoredSts;
158 if ((EntryPoint & (CPU_FEAT_BEFORE_PM_INIT | CPU_FEAT_INIT_LATE_END | CPU_FEAT_S3_LATE_RESTORE_END)) != 0) {
159 for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {
160 PackageType = LibAmdGetPackageType (StdHeader);
161 GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
162 PciAddress.Address.Function = FUNC_4;
163 PciAddress.Address.Register = CPB_CTRL_REG;
164 LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
165 if (PackageType == PACKAGE_TYPE_AM3r2) {
166 ((CPB_CTRL_REGISTER *) (&CpbControl))->BoostSrc = 1;
168 if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) {
169 ((CPB_CTRL_REGISTER *) (&CpbControl))->BoostSrc = 1;
172 LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
175 return AGESA_SUCCESS;
178 CONST CPB_FAMILY_SERVICES ROMDATA F15OrCpbSupport =