src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * AMD Family_10 Rev C PCI tables with values as defined in BKDG
   6  *
   7  * @xrefitem bom "File Content Label" "Release Content"
   8  * @e project:      AGESA
   9  * @e sub-project:  CPU/FAMILY/0x10/RevC
  10  * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
  11  *
  12  */
  13 /*
  14  ******************************************************************************
  15  *
  16  * Copyright (C) 2012 Advanced Micro Devices, Inc.
  17  * All rights reserved.
  18  *
  19  * Redistribution and use in source and binary forms, with or without
  20  * modification, are permitted provided that the following conditions are met:
  21  *     * Redistributions of source code must retain the above copyright
  22  *       notice, this list of conditions and the following disclaimer.
  23  *     * Redistributions in binary form must reproduce the above copyright
  24  *       notice, this list of conditions and the following disclaimer in the
  25  *       documentation and/or other materials provided with the distribution.
  26  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  27  *       its contributors may be used to endorse or promote products derived
  28  *       from this software without specific prior written permission.
  29  *
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  31  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  32  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  33  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  34  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  35  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  36  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  37  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  39  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  ******************************************************************************
  42  */
  43
  44 /*----------------------------------------------------------------------------------------
  45  *                             M O D U L E S    U S E D
  46  *----------------------------------------------------------------------------------------
  47  */
  48 #include "AGESA.h"
  49 #include "cpuRegisters.h"
  50 #include "Table.h"
  51 #include "F10PackageType.h"
  52 #include "Filecode.h"
  53 CODE_GROUP (G1_PEICC)
  54 RDATA_GROUP (G2_PEI)
  55 #define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE
  56
  57 /*----------------------------------------------------------------------------------------
  58  *                   D E F I N I T I O N S    A N D    M A C R O S
  59  *----------------------------------------------------------------------------------------
  60  */
  61
  62 /*----------------------------------------------------------------------------------------
  63  *                  T Y P E D E F S     A N D     S T R U C T U R E S
  64  *----------------------------------------------------------------------------------------
  65  */
  66
  67 /*----------------------------------------------------------------------------------------
  68  *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
  69  *----------------------------------------------------------------------------------------
  70  */
  71
  72 /*----------------------------------------------------------------------------------------
  73  *                          E X P O R T E D    F U N C T I O N S
  74  *----------------------------------------------------------------------------------------
  75  */
  76
  77 //  P C I    T a b l e s
  78 // ----------------------
  79
  80 STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevCPciRegisters[] =
  81 {
  82 // Function 2 - DRAM Controller
  83
  84 // F2x1B0 - Extended Memory Controller Configuration Low Register
  85 //
  86 // bit[5:4], AdapPrefNegativeStep = 0
  87   {
  88     PciRegister,
  89     {
  90       AMD_FAMILY_10,                      // CpuFamily
  91       AMD_F10_Cx                          // CpuRevision
  92     },
  93     {AMD_PF_ALL},                           // platformFeatures
  94     {{
  95       MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address
  96       0x00000000,                           // regData
  97       0x00000030,                           // regMask
  98     }}
  99   },
 100 // Function 3 - Misc. Control
 101
 102 // F3x158 - Link to XCS Token Count
 103 // bits[3:0] LnkToXcsDRToken = 3
 104   {
 105     PciRegister,
 106     {
 107       AMD_FAMILY_10,                      // CpuFamily
 108       AMD_F10_GT_A2                       // CpuRevision
 109     },
 110     {AMD_PF_UMA},                           // platformFeatures
 111     {{
 112       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
 113       0x00000003,                           // regData
 114       0x0000000F,                           // regMask
 115     }}
 116   },
 117 // F3x80 - ACPI Power State Control
 118 // ACPI State C2
 119 // bits[0] CpuPrbEn = 1
 120 // bits[1] NbLowPwrEn = 0
 121 // bits[2] NbGateEn = 0
 122 // bits[3] NbCofChg = 0
 123 // bits[4] AltVidEn = 0
 124 // bits[7:5] ClkDivisor = 1
 125 // ACPI State C3, C1E or Link init
 126 // bits[0] CpuPrbEn = 0
 127 // bits[1] NbLowPwrEn = 1
 128 // bits[2] NbGateEn = 1
 129 // bits[3] NbCofChg = 0
 130 // bits[4] AltVidEn = 0
 131 // bits[7:5] ClkDivisor = 7
 132   {
 133     PciRegister,
 134     {
 135       AMD_FAMILY_10,                      // CpuFamily
 136       AMD_F10_Cx                          // CpuRevision
 137     },
 138     {AMD_PF_ALL},                           // platformFeatures
 139     {{
 140       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
 141       0x0000E681,                           // regData
 142       0x0000FFFF,                           // regMask
 143     }}
 144   },
 145 // F3x80 - ACPI Power State Control
 146 // ACPI State C3, C1E or Link init
 147 // bits[0] CpuPrbEn = 1
 148 // bits[1] NbLowPwrEn = 1
 149 // bits[2] NbGateEn = 1
 150 // bits[3] NbCofChg = 0
 151 // bits[4] AltVidEn = 0
 152 // bits[7:5] ClkDivisor = 4
 153   {
 154     HtFeatPciRegister,
 155     {
 156       AMD_FAMILY_10,                      // CpuFamily
 157       AMD_F10_Cx                          // CpuRevision
 158     },
 159     {AMD_PF_SINGLE_LINK},                   // platformFeatures
 160     {{
 161       HT_HOST_FEAT_HT1,                     // link feats
 162       PACKAGE_TYPE_ASB2,                    // package type
 163       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
 164       0x00008700,                           // regData
 165       0x0000FF00,                           // regMask
 166     }}
 167   },
 168 // F3x80 - ACPI Power State Control
 169 // ACPI State C3, C1E or Link init
 170 // bits[0] CpuPrbEn = 0
 171 // bits[1] NbLowPwrEn = 1
 172 // bits[2] NbGateEn = 1
 173 // bits[3] NbCofChg = 0
 174 // bits[4] AltVidEn = 1
 175 // bits[7:5] ClkDivisor = 7
 176   {
 177     ProfileFixup,
 178     {
 179       AMD_FAMILY_10,                        // CpuFamily
 180       AMD_F10_C3                           // CpuRevision
 181     },
 182     {AMD_PF_ALL},                             // platformFeatures
 183     {{
 184       PERFORMANCE_VRM_HIGH_SPEED_ENABLE,    // PerformanceFeatures
 185       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
 186       0x0000F600,                           // regData
 187       0x0000FF00,                           // regMask
 188     }}
 189   },
 190 // F3x80 - ACPI Power State Control
 191 // ACPI State C3, C1E or Link init
 192 // bits[0] CpuPrbEn = 1
 193 // bits[1] NbLowPwrEn = 1
 194 // bits[2] NbGateEn = 1
 195 // bits[3] NbCofChg = 0
 196 // bits[4] AltVidEn = 0
 197 // bits[7:5] ClkDivisor = 4
 198   {
 199     HtFeatPciRegister,
 200     {
 201       AMD_FAMILY_10,                      // CpuFamily
 202       AMD_F10_Cx                          // CpuRevision
 203     },
 204     {AMD_PF_SINGLE_LINK},                   // platformFeatures
 205     {{
 206       HT_HOST_FEAT_HT1,                     // link feats
 207       PACKAGE_TYPE_ALL & (~ PACKAGE_TYPE_ASB2),  // package type
 208       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
 209       0x00008700,                           // regData
 210       0x0000FF00,                           // regMask
 211     }}
 212   },
 213 // F3xDC - Clock Power Timing Control 2
 214 // bits[14:12] NbsynPtrAdj = 5
 215   {
 216     PciRegister,
 217     {
 218       AMD_FAMILY_10,                      // CpuFamily
 219       AMD_F10_Cx                          // CpuRevision
 220     },
 221     {AMD_PF_ALL},                           // platformFeatures
 222     {{
 223       MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
 224       0x00005000,                           // regData
 225       0x00007000,                           // regMask
 226     }}
 227   },
 228 // F3x180 - NB Extended Configuration
 229 // bits[23] SyncFloodOnDramTempErr = 1
 230   {
 231     PciRegister,
 232     {
 233       AMD_FAMILY_10,                      // CpuFamily
 234       AMD_F10_Cx                          // CpuRevision
 235     },
 236     {AMD_PF_ALL},                           // platformFeatures
 237     {{
 238       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
 239       0x00800000,                           // regData
 240       0x00800000,                           // regMask
 241     }}
 242   },
 243 // F3x188 - NB Extended Configuration Low Register
 244 // bit[22] = DisHldReg2
 245 // Errata #346
 246   {
 247     PciRegister,
 248     {
 249       AMD_FAMILY_10,                      // CpuFamily
 250       AMD_F10_Cx                          // CpuRevision
 251     },
 252     {AMD_PF_ALL},                           // platformFeatures
 253     {{
 254       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
 255       0x00400000,                           // regData
 256       0x00400000,                           // regMask
 257     }}
 258   }
 259 };
 260
 261 CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable = {
 262   PrimaryCores,
 263   (sizeof (F10RevCPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
 264   F10RevCPciRegisters,
 265 };