src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * AMD Family_10 PCI tables in Recommended Settings for Single Link Processors.
   6  *
   7  * @xrefitem bom "File Content Label" "Release Content"
   8  * @e project:      AGESA
   9  * @e sub-project:  CPU/FAMILY/0x10
  10  * @e \$Revision: 59564 $   @e \$Date: 2011-09-26 12:33:51 -0600 (Mon, 26 Sep 2011) $
  11  *
  12  */
  13 /*
  14  ******************************************************************************
  15  *
  16  * Copyright (C) 2012 Advanced Micro Devices, Inc.
  17  * All rights reserved.
  18  *
  19  * Redistribution and use in source and binary forms, with or without
  20  * modification, are permitted provided that the following conditions are met:
  21  *     * Redistributions of source code must retain the above copyright
  22  *       notice, this list of conditions and the following disclaimer.
  23  *     * Redistributions in binary form must reproduce the above copyright
  24  *       notice, this list of conditions and the following disclaimer in the
  25  *       documentation and/or other materials provided with the distribution.
  26  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  27  *       its contributors may be used to endorse or promote products derived
  28  *       from this software without specific prior written permission.
  29  *
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  31  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  32  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  33  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  34  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  35  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  36  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  37  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  39  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  ******************************************************************************
  42  */
  43
  44 /*----------------------------------------------------------------------------------------
  45  *                             M O D U L E S    U S E D
  46  *----------------------------------------------------------------------------------------
  47  */
  48 #include "AGESA.h"
  49 #include "Ids.h"
  50 #include "cpuRegisters.h"
  51 #include "Table.h"
  52 #include "Filecode.h"
  53 CODE_GROUP (G1_PEICC)
  54 RDATA_GROUP (G2_PEI)
  55
  56 #define FILECODE PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE
  57
  58 /*----------------------------------------------------------------------------------------
  59  *                   D E F I N I T I O N S    A N D    M A C R O S
  60  *----------------------------------------------------------------------------------------
  61  */
  62
  63 /*----------------------------------------------------------------------------------------
  64  *                  T Y P E D E F S     A N D     S T R U C T U R E S
  65  *----------------------------------------------------------------------------------------
  66  */
  67
  68 /*----------------------------------------------------------------------------------------
  69  *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
  70  *----------------------------------------------------------------------------------------
  71  */
  72
  73 /*----------------------------------------------------------------------------------------
  74  *                          E X P O R T E D    F U N C T I O N S
  75  *----------------------------------------------------------------------------------------
  76  */
  77
  78 //  P C I    T a b l e s
  79 // ----------------------
  80
  81 STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10SingleLinkPciRegisters[] =
  82 {
  83 // F0x68 - Link Transaction Control
  84 // bit[14:13], BufPriRel = 01b
  85   {
  86     PciRegister,
  87     {
  88       AMD_FAMILY_10,                        // CpuFamily
  89       AMD_F10_ALL                           // CpuRevision
  90     },
  91     {AMD_PF_SINGLE_LINK},                     // platform Features
  92     {{
  93       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
  94       0x00002000,                           // regData
  95       0x00006000,                           // regMask
  96     }}
  97   },
  98 // F0x68 - Link Transaction Control
  99 // bit[24], DispRefModeEn = 0
 100   {
 101     PciRegister,
 102     {
 103       AMD_FAMILY_10,                        // CpuFamily
 104       AMD_F10_ALL                           // CpuRevision
 105     },
 106     {AMD_PF_ALL},                             // platform Features
 107     {{
 108       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
 109       0x00000000,                           // regData
 110       0x01000000,                           // regMask
 111     }}
 112   },
 113 // F0x68 - Link Transaction Control
 114 // bit[24], DispRefModeEn = 1 for UMA, but can only set it on the warm reset.
 115   {
 116     ProfileFixup,
 117     {
 118       AMD_FAMILY_10,                        // CpuFamily
 119       AMD_F10_ALL                           // CpuRevision
 120     },
 121     {AMD_PF_UMA},                     // platform Features
 122     {{
 123       PERFORMANCE_IS_WARM_RESET,
 124       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
 125       0x01000000,                           // regData
 126       0x01000000,                           // regMask
 127     }}
 128   },
 129   // F0x[F0,D0,B0,90] Link Base Buffer Count Register
 130   // 27:25 FreeData: 2
 131   // 24:20 FreeCmd: 8
 132   // 19:18 RspData: 1
 133   // 17:16 NpReqData: 1
 134   // 15:12 ProbeCmd: 0
 135   // 11:8 RspCmd: 2
 136   // 7:5 PReq: 4
 137   // 4:0 NpReqCmd: 18
 138   {
 139     HtHostPciRegister,
 140     {
 141       AMD_FAMILY_10,                        // CpuFamily
 142       AMD_F10_ALL                           // CpuRevision
 143     },
 144     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) },
 145     {{
 146       HT_HOST_FEATURES_ALL,                 // Link Features
 147       0x10,                                 // Address
 148       0x04850292,                           // Data
 149       0x0FFFFFFF                            // Mask
 150     }},
 151   },
 152   // F0x[F0,D0,B0,90] Link Base Buffer Count Register
 153   // 27:25 FreeData: 2
 154   // 24:20 FreeCmd: 8
 155   // 19:18 RspData: 1
 156   // 17:16 NpReqData: 1
 157   // 15:12 ProbeCmd: 0
 158   // 11:8 RspCmd: 2
 159   // 7:5 PReq: 4
 160   // 4:0 NpReqCmd: 18
 161   {
 162     HtHostPciRegister,
 163     {
 164       AMD_FAMILY_10,                        // CpuFamily
 165       AMD_F10_ALL                           // CpuRevision
 166     },
 167     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },
 168     {{
 169       HT_HOST_FEATURES_ALL,                 // Link Features
 170       0x10,                                 // Address
 171       0x04850292,                           // Data
 172       0x0FFFFFFF                            // Mask
 173     }},
 174   },
 175   // F0x[F0,D0,B0,90] Link Base Buffer Count Register
 176   // 27:25 FreeData: 2
 177   // 24:20 FreeCmd: 8
 178   // 19:18 RspData: 1
 179   // 17:16 NpReqData: 1
 180   // 15:12 ProbeCmd: 0
 181   // 11:8 RspCmd: 2
 182   // 7:5 PReq: 3
 183   // 4:0 NpReqCmd: 11
 184   {
 185     HtHostPciRegister,
 186     {
 187       AMD_FAMILY_10,                        // CpuFamily
 188       AMD_F10_ALL                           // CpuRevision
 189     },
 190     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },
 191     {{
 192       HT_HOST_FEATURES_ALL,                 // Link Features
 193       0x10,                                 // Address
 194       0x0485026B,                           // Data
 195       0x0FFFFFFF                            // Mask
 196     }},
 197   },
 198   // F0x[F0,D0,B0,90] Link Base Buffer Count Register
 199   // 27:25 FreeData: 2
 200   // 24:20 FreeCmd: 8
 201   // 19:18 RspData: 1
 202   // 17:16 NpReqData: 1
 203   // 15:12 ProbeCmd: 0
 204   // 11:8 RspCmd: 2
 205   // 7:5 PReq: 6
 206   // 4:0 NpReqCmd: 15
 207   {
 208     HtHostPciRegister,
 209     {
 210       AMD_FAMILY_10,                        // CpuFamily
 211       AMD_F10_ALL                           // CpuRevision
 212     },
 213     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },
 214     {{
 215       HT_HOST_FEATURES_ALL,                 // Link Features
 216       0x10,                                 // Address
 217       0x008502CF,                           // Data
 218       0x0FFFFFFF                            // Mask
 219     }},
 220   },
 221   // F0x[F0,D0,B0,90] Link Base Buffer Count Register
 222   // 27:25 FreeData: 0
 223   // 24:20 FreeCmd: 8
 224   // 19:18 RspData: 1
 225   // 17:16 NpReqData: 1
 226   // 15:12 ProbeCmd: 0
 227   // 11:8 RspCmd: 2
 228   // 7:5 PReq: 6
 229   // 4:0 NpReqCmd: 15
 230   {
 231     HtHostPciRegister,
 232     {
 233       AMD_FAMILY_10,                        // CpuFamily
 234       AMD_F10_ALL                           // CpuRevision
 235     },
 236     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },
 237     {{
 238       HT_HOST_FEATURES_ALL,                 // Link Features
 239       0x10,                                 // Address
 240       0x808502CF,                           // Data
 241       0x0FFFFFFF                            // Mask
 242     }},
 243   },
 244   // F0x[F4,D4,B4,94] Link Base Buffer Count Register
 245   // 28:27 IsocRspData: 0
 246   // 26:25 IsocNpReqData: 0
 247   // 24:22 IsocRspCmd: 0
 248   // 21:19 IsocPReq: 0
 249   // 18:16 IsocNpReqCmd: 0
 250   {
 251     HtHostPciRegister,
 252     {
 253       AMD_FAMILY_10,                        // CpuFamily
 254       AMD_F10_ALL                           // CpuRevision
 255     },
 256     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) },
 257     {{
 258       HT_HOST_FEATURES_ALL,                 // Link Features
 259       0x14,                                 // Address
 260       0x00000000,                           // Data
 261       0x1FFF0000                            // Mask
 262     }},
 263   },
 264   // F0x[F4,D4,B4,94] Link Base Buffer Count Register
 265   // 28:27 IsocRspData: 0
 266   // 26:25 IsocNpReqData: 0
 267   // 24:22 IsocRspCmd: 0
 268   // 21:19 IsocPReq: 0
 269   // 18:16 IsocNpReqCmd: 0
 270   {
 271     HtHostPciRegister,
 272     {
 273       AMD_FAMILY_10,                        // CpuFamily
 274       AMD_F10_ALL                           // CpuRevision
 275     },
 276     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },
 277     {{
 278       HT_HOST_FEATURES_ALL,                 // Link Features
 279       0x14,                                 // Address
 280       0x00000000,                           // Data
 281       0x1FFF0000                            // Mask
 282     }},
 283   },
 284   // F0x[F4,D4,B4,94] Link Base Buffer Count Register
 285   // 28:27 IsocRspData: 0
 286   // 26:25 IsocNpReqData: 0
 287   // 24:22 IsocRspCmd: 0
 288   // 21:19 IsocPReq: 1
 289   // 18:16 IsocNpReqCmd: 7
 290   {
 291     HtHostPciRegister,
 292     {
 293       AMD_FAMILY_10,                        // CpuFamily
 294       AMD_F10_ALL                           // CpuRevision
 295     },
 296     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },
 297     {{
 298       HT_HOST_FEATURES_ALL,                 // Link Features
 299       0x14,                                 // Address
 300       0x000F0000,                           // Data
 301       0x1FFF0000                            // Mask
 302     }},
 303   },
 304   // F0x[F4,D4,B4,94] Link Base Buffer Count Register
 305   // 28:27 IsocRspData: 0
 306   // 26:25 IsocNpReqData: 0
 307   // 24:22 IsocRspCmd: 0
 308   // 21:19 IsocPReq: 0
 309   // 18:16 IsocNpReqCmd: 1
 310   {
 311     HtHostPciRegister,
 312     {
 313       AMD_FAMILY_10,                        // CpuFamily
 314       AMD_F10_ALL                           // CpuRevision
 315     },
 316     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },
 317     {{
 318       HT_HOST_FEATURES_ALL,                 // Link Features
 319       0x14,                                 // Address
 320       0x00010000,                           // Data
 321       0x1FFF0000                            // Mask
 322     }},
 323   },
 324   // F0x[F4,D4,B4,94] Link Base Buffer Count Register
 325   // 28:27 IsocRspData: 0
 326   // 26:25 IsocNpReqData: 0
 327   // 24:22 IsocRspCmd: 0
 328   // 21:19 IsocPReq: 0
 329   // 18:16 IsocNpReqCmd: 1
 330   {
 331     HtHostPciRegister,
 332     {
 333       AMD_FAMILY_10,                        // CpuFamily
 334       AMD_F10_ALL                           // CpuRevision
 335     },
 336     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },
 337     {{
 338       HT_HOST_FEATURES_ALL,                 // Link Features
 339       0x14,                                 // Address
 340       0x00010000,                           // Data
 341       0x1FFF0000                            // Mask
 342     }},
 343   },
 344 // F0x170 - Link Extended Control Register - Link 0, sublink 0
 345 // bit[8] LS2En = 1
 346   {
 347     PciRegister,
 348     {
 349       AMD_FAMILY_10,                        // CpuFamily
 350       AMD_F10_ALL                           // CpuRevision
 351     },
 352     {AMD_PF_SINGLE_LINK},                     // platform Features
 353     {{
 354       MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
 355       0x00000100,                           // regData
 356       0x00000100,                           // regMask
 357     }}
 358   },
 359 // F2x118 - Memory Controller Configuration Low Register
 360 // bits[13:12] MctPriIsoc = 10b
 361 // bits[31:28] MctVarPriCntLmt = 0
 362   {
 363     PciRegister,
 364     {
 365       AMD_FAMILY_10,                      // CpuFamily
 366       AMD_F10_ALL                         // CpuRevision
 367     },
 368     { (AMD_PF_UMA | AMD_PF_UMA_IFCM) },        // platform Features
 369     {{
 370       MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118),  // Address
 371       0x00002000,                           // regData
 372       0xF0003000,                           // regMask
 373     }}
 374   },
 375 // F2x118 - Memory Controller Configuration Low Register
 376 // bits[13:12] MctPriIsoc = 00b
 377 // bits[31:28] MctVarPriCntLmt = 0
 378   {
 379     PciRegister,
 380     {
 381       AMD_FAMILY_10,                      // CpuFamily
 382       AMD_F10_ALL                         // CpuRevision
 383     },
 384     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },        // platform Features
 385     {{
 386       MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118),  // Address
 387       0x00000000,                           // regData
 388       0xF0000000,                           // regMask
 389     }}
 390   },
 391 // F2x118 - Memory Controller Configuration Low Register
 392 // bits[13:12] MctPriIsoc = 11b
 393 // bits[31:28] MctVarPriCntLmt = 1
 394   {
 395     ProfileFixup,
 396     {
 397       AMD_FAMILY_10,                      // CpuFamily
 398       AMD_F10_ALL                         // CpuRevision
 399     },
 400     { (AMD_PF_UMA | AMD_PF_UMA_IFCM) },       // platform Features
 401     {{
 402       PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
 403       MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118),  // Address
 404       0x10003000,                           // regData
 405       0xF0003000,                           // regMask
 406     }}
 407   },
 408 // F2x[1,0]90 - DRAM Configuration Low Register
 409 // bits [10] BurstLength32  0
 410 // It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
 411 // If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
 412   {
 413     PciRegister,
 414     {
 415       AMD_FAMILY_10,                      // CpuFamily
 416       AMD_F10_ALL                         // CpuRevision
 417     },
 418     { (AMD_PF_UMA | AMD_PF_UMA_IFCM) },        // platform Features
 419     {{
 420       MAKE_SBDFO (0, 0, 24, FUNC_2, 0x90),  // Address
 421       0x00000000,                           // regData
 422       0x00000400,                           // regMask
 423     }}
 424   },
 425 // F2x[1,0]90 - DRAM Configuration Low Register
 426 // bits [10] BurstLength32 = 0
 427 // It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
 428 // If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
 429   {
 430     PciRegister,
 431     {
 432       AMD_FAMILY_10,                      // CpuFamily
 433       AMD_F10_ALL                         // CpuRevision
 434     },
 435     { (AMD_PF_UMA | AMD_PF_UMA_IFCM) },        // platform Features
 436     {{
 437       MAKE_SBDFO (0, 0, 24, FUNC_2, 0x190),  // Address
 438       0x00000000,                           // regData
 439       0x00000400,                           // regMask
 440     }}
 441   },
 442 // F2x[1,0]90 - DRAM Configuration Low Register
 443 // bits [10] BurstLength32 = 1
 444 // It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
 445 // If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
 446   {
 447     ProfileFixup,
 448     {
 449       AMD_FAMILY_10,                      // CpuFamily
 450       AMD_F10_ALL                         // CpuRevision
 451     },
 452     { (AMD_PF_UMA | AMD_PF_UMA_IFCM) },        // platform Features
 453     {{
 454       PERFORMANCE_REFRESH_REQUEST_32B,
 455       MAKE_SBDFO (0, 0, 24, FUNC_2, 0x90),  // Address
 456       0x00000400,                           // regData
 457       0x00000400,                           // regMask
 458     }}
 459   },
 460 // F2x[1,0]90 - DRAM Configuration Low Register
 461 // bits [10] BurstLength32 = 1
 462 // It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
 463 // If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
 464   {
 465     ProfileFixup,
 466     {
 467       AMD_FAMILY_10,                      // CpuFamily
 468       AMD_F10_ALL                         // CpuRevision
 469     },
 470     { (AMD_PF_UMA | AMD_PF_UMA_IFCM) },        // platform Features
 471     {{
 472       PERFORMANCE_REFRESH_REQUEST_32B,
 473       MAKE_SBDFO (0, 0, 24, FUNC_2, 0x190),  // Address
 474       0x00000400,                           // regData
 475       0x00000400,                           // regMask
 476     }}
 477   },
 478 // F3x6C - Data Buffer Control
 479 // bits[2:0]   UpReqDBC = 2
 480 // bits[5:4]   DnReqDBC = 1
 481 // bits[7:6]   DnRspDBC = 1
 482 // bit[15]     DatBuf24 = 1
 483 // bits[18:16] UpRspDBC = 1
 484 // bits[30:28] IsocRspDBC = 0
 485   {
 486     PciRegister,
 487     {
 488       AMD_FAMILY_10,                      // CpuFamily
 489       AMD_F10_ALL                         // CpuRevision
 490     },
 491     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) }, // platform Features
 492     {{
 493       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
 494       0x00018052,                           // regData
 495       0x700780F7,                           // regMask
 496     }}
 497   },
 498 // F3x6C - Data Buffer Control
 499 // bits[2:0]   UpReqDBC = 1
 500 // bits[5:4]   DnReqDBC = 1
 501 // bits[7:6]   DnRspDBC = 1
 502 // bit[15]     DatBuf24 = 1
 503 // bits[18:16] UpRspDBC = 1
 504 // bits[30:28] IsocRspDBC = 6
 505   {
 506     PciRegister,
 507     {
 508       AMD_FAMILY_10,                      // CpuFamily
 509       AMD_F10_ALL                         // CpuRevision
 510     },
 511     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features
 512     {{
 513       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
 514       0x60018051,                           // regData
 515       0x700780F7,                           // regMask
 516     }}
 517   },
 518 // F3x6C - Data Buffer Control
 519 // bits[2:0]   UpReqDBC = 2
 520 // bits[5:4]   DnReqDBC = 1
 521 // bits[7:6]   DnRspDBC = 1
 522 // bit[15]     DatBuf24 = 1
 523 // bits[18:16] UpRspDBC = 1
 524 // bits[30:28] IsocRspDBC = 1
 525   {
 526     PciRegister,
 527     {
 528       AMD_FAMILY_10,                      // CpuFamily
 529       AMD_F10_ALL                         // CpuRevision
 530     },
 531     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, // platform Features
 532     {{
 533       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
 534       0x10018052,                           // regData
 535       0x700780F7,                           // regMask
 536     }}
 537   },
 538 // F3x6C - Data Buffer Control
 539 // bits[2:0]   UpReqDBC = 1
 540 // bits[5:4]   DnReqDBC = 1
 541 // bits[7:6]   DnRspDBC = 1
 542 // bit[15]     DatBuf24 = 1
 543 // bits[18:16] UpRspDBC = 1
 544 // bits[30:28] IsocRspDBC = 6
 545   {
 546     PciRegister,
 547     {
 548       AMD_FAMILY_10,                      // CpuFamily
 549       AMD_F10_ALL                         // CpuRevision
 550     },
 551     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
 552     {{
 553       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
 554       0x60018051,                           // regData
 555       0x700780F7,                           // regMask
 556     }}
 557   },
 558 // F3x6C - Data Buffer Control
 559 // bits[2:0]   UpReqDBC = 2
 560 // bits[5:4]   DnReqDBC = 1
 561 // bits[7:6]   DnRspDBC = 1
 562 // bit[15]     DatBuf24 = 1
 563 // bits[18:16] UpRspDBC = 1
 564 // bits[30:28] IsocRspDBC = 1
 565   {
 566     PciRegister,
 567     {
 568       AMD_FAMILY_10,                      // CpuFamily
 569       AMD_F10_ALL                         // CpuRevision
 570     },
 571     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) }, // platform Features
 572     {{
 573       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
 574       0x10018052,                           // regData
 575       0x700780F7,                           // regMask
 576     }}
 577   },
 578 // F3x70 - SRI_to_XBAR Command Buffer Count
 579 // bits[2:0]   UpReqCBC = 3
 580 // bits[5:4]   DnReqCBC = 1
 581 // bits[7:6]   DnRspCBC = 1
 582 // bits[10:8]  UpPreqCBC = 1
 583 // bits[14:12] DnPreqCBC = 1
 584 // bits[18:16] UpRspCBC = 4
 585 // bits[22:20] IsocReqCBC = 0
 586 // bits[26:24] IsocPreqCBC = 0
 587 // bits[30:28] IsocRspCBC = 0
 588   {
 589     PciRegister,
 590     {
 591       AMD_FAMILY_10,                      // CpuFamily
 592       AMD_F10_ALL                         // CpuRevision
 593     },
 594     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) }, // platform Features
 595     {{
 596       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
 597       0x00041153,                           // regData
 598       0x777777F7,                           // regMask
 599     }}
 600   },
 601 // F3x70 - SRI_to_XBAR Command Buffer Count
 602 // bits[2:0]   UpReqCBC = 1
 603 // bits[5:4]   DnReqCBC = 1
 604 // bits[7:6]   DnRspCBC = 1
 605 // bits[10:8]  UpPreqCBC = 1
 606 // bits[14:12] DnPreqCBC = 1
 607 // bits[18:16] UpRspCBC = 2
 608 // bits[22:20] IsocReqCBC = 2
 609 // bits[26:24] IsocPreqCBC = 1
 610 // bits[30:28] IsocRspCBC = 6
 611   {
 612     PciRegister,
 613     {
 614       AMD_FAMILY_10,                      // CpuFamily
 615       AMD_F10_ALL                         // CpuRevision
 616     },
 617     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features
 618     {{
 619       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
 620       0x61221151,                           // regData
 621       0x777777F7,                           // regMask
 622     }}
 623   },
 624 // F3x70 - SRI_to_XBAR Command Buffer Count
 625 // bits[2:0]   UpReqCBC = 1
 626 // bits[5:4]   DnReqCBC = 1
 627 // bits[7:6]   DnRspCBC = 1
 628 // bits[10:8]  UpPreqCBC = 1
 629 // bits[14:12] DnPreqCBC = 1
 630 // bits[18:16] UpRspCBC = 2
 631 // bits[22:20] IsocReqCBC = 2
 632 // bits[26:24] IsocPreqCBC = 1
 633 // bits[30:28] IsocRspCBC = 6
 634   {
 635     PciRegister,
 636     {
 637       AMD_FAMILY_10,                      // CpuFamily
 638       AMD_F10_ALL                         // CpuRevision
 639     },
 640     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
 641     {{
 642       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
 643       0x61221151,                           // regData
 644       0x777777F7,                           // regMask
 645     }}
 646   },
 647 // F3x70 - SRI_to_XBAR Command Buffer Count
 648 // bits[2:0]   UpReqCBC = 3
 649 // bits[5:4]   DnReqCBC = 1
 650 // bits[7:6]   DnRspCBC = 1
 651 // bits[10:8]  UpPreqCBC = 1
 652 // bits[14:12] DnPreqCBC = 1
 653 // bits[18:16] UpRspCBC = 4
 654 // bits[22:20] IsocReqCBC = 1
 655 // bits[26:24] IsocPreqCBC = 1
 656 // bits[30:28] IsocRspCBC = 1
 657   {
 658     PciRegister,
 659     {
 660       AMD_FAMILY_10,                      // CpuFamily
 661       AMD_F10_ALL                         // CpuRevision
 662     },
 663     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, // platform Features
 664     {{
 665       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
 666       0x11141153,                           // regData
 667       0x777777F7,                           // regMask
 668     }}
 669   },
 670 // F3x70 - SRI_to_XBAR Command Buffer Count
 671 // bits[2:0]   UpReqCBC = 3
 672 // bits[5:4]   DnReqCBC = 1
 673 // bits[7:6]   DnRspCBC = 1
 674 // bits[10:8]  UpPreqCBC = 1
 675 // bits[14:12] DnPreqCBC = 1
 676 // bits[18:16] UpRspCBC = 5
 677 // bits[22:20] IsocReqCBC = 1
 678 // bits[26:24] IsocPreqCBC = 0
 679 // bits[30:28] IsocRspCBC = 1
 680   {
 681     PciRegister,
 682     {
 683       AMD_FAMILY_10,                      // CpuFamily
 684       AMD_F10_ALL                         // CpuRevision
 685     },
 686     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) }, // platform Features
 687     {{
 688       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
 689       0x10151153,                           // regData
 690       0x777777F7,                           // regMask
 691     }}
 692   },
 693 // F3x74 - XBAR_to_SRI Command Buffer Count
 694 // bits[2:0]   UpReqCBC = 1
 695 // bits[6:4]   DnReqCBC = 1
 696 // bits[10:8]  UpPreqCBC = 1
 697 // bits[14:12] DnPreqCBC = 1
 698 // bits[19:16] ProbeCBC = 8
 699 // bits[23:20] IsocReqCBC = 0
 700 // bits[26:24] IsocPreqCBC = 0
 701 // bits[31:28] DRReqCBC = 0
 702   {
 703     PciRegister,
 704     {
 705       AMD_FAMILY_10,                      // CpuFamily
 706       AMD_F10_ALL                         // CpuRevision
 707     },
 708     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) }, // platform Features
 709     {{
 710       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
 711       0x00081111,                           // regData
 712       0xF7FF7777,                           // regMask
 713     }}
 714   },
 715 // F3x74 - XBAR_to_SRI Command Buffer Count
 716 // No Mct Variable Priority or 32 byte requests.
 717 // bits[2:0]   UpReqCBC = 1
 718 // bits[6:4]   DnReqCBC = 0
 719 // bits[10:8]  UpPreqCBC = 1
 720 // bits[14:12] DnPreqCBC = 0
 721 // bits[19:16] ProbeCBC = 8
 722 // bits[23:20] IsocReqCBC = 1
 723 // bits[26:24] IsocPreqCBC = 1
 724 // bits[31:28] DRReqCBC = 9
 725   {
 726     PciRegister,
 727     {
 728       AMD_FAMILY_10,                      // CpuFamily
 729       AMD_F10_ALL                         // CpuRevision
 730     },
 731     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
 732     {{
 733       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
 734       0x91180101,                           // regData
 735       0xF7FF7777,                           // regMask
 736     }}
 737   },
 738 // F3x74 - XBAR_to_SRI Command Buffer Count
 739 // No Mct Variable Priority or 32 byte requests.
 740 // bits[2:0]   UpReqCBC = 1
 741 // bits[6:4]   DnReqCBC = 0
 742 // bits[10:8]  UpPreqCBC = 1
 743 // bits[14:12] DnPreqCBC = 0
 744 // bits[19:16] ProbeCBC = 8
 745 // bits[23:20] IsocReqCBC = 1
 746 // bits[26:24] IsocPreqCBC = 1
 747 // bits[31:28] DRReqCBC = 9
 748   {
 749     PciRegister,
 750     {
 751       AMD_FAMILY_10,                      // CpuFamily
 752       AMD_F10_ALL                         // CpuRevision
 753     },
 754     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
 755     {{
 756       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
 757       0x91180101,                           // regData
 758       0xF7FF7777,                           // regMask
 759     }}
 760   },
 761 // F3x74 - XBAR_to_SRI Command Buffer Count
 762 // No Mct Variable Priority or 32 byte requests.
 763 // bits[2:0]   UpReqCBC = 1
 764 // bits[6:4]   DnReqCBC = 1
 765 // bits[10:8]  UpPreqCBC = 1
 766 // bits[14:12] DnPreqCBC =1
 767 // bits[19:16] ProbeCBC = 8
 768 // bits[23:20] IsocReqCBC = 1
 769 // bits[26:24] IsocPreqCBC = 0
 770 // bits[31:28] DRReqCBC = 0
 771   {
 772     PciRegister,
 773     {
 774       AMD_FAMILY_10,                      // CpuFamily
 775       AMD_F10_ALL                         // CpuRevision
 776     },
 777     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) }, // platform Features
 778     {{
 779       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
 780       0x00181111,                           // regData
 781       0xF7FF7777,                           // regMask
 782     }}
 783   },
 784 // F3x74 - XBAR_to_SRI Command Buffer Count
 785 // No Mct Variable Priority or 32 byte requests.
 786 // bits[2:0]   UpReqCBC = 1
 787 // bits[6:4]   DnReqCBC = 0
 788 // bits[10:8]  UpPreqCBC = 1
 789 // bits[14:12] DnPreqCBC = 0
 790 // bits[19:16] ProbeCBC = 8
 791 // bits[23:20] IsocReqCBC = 1
 792 // bits[26:24] IsocPreqCBC = 1
 793 // bits[31:28] DRReqCBC = 8
 794   {
 795     CoreCountsPciRegister,
 796     {
 797       AMD_FAMILY_10,                      // CpuFamily
 798       AMD_F10_ALL                         // CpuRevision
 799     },
 800     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
 801     {{
 802       PERFORMANCE_PROFILE_ALL,  // Features
 803       (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
 804       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
 805       0x81180101,                           // regData
 806       0xF7FF7777,                           // regMask
 807     }}
 808   },
 809 // F3x74 - XBAR_to_SRI Command Buffer Count
 810 // No Mct Variable Priority or 32 byte requests.
 811 // bits[2:0]   UpReqCBC = 1
 812 // bits[6:4]   DnReqCBC = 0
 813 // bits[10:8]  UpPreqCBC = 1
 814 // bits[14:12] DnPreqCBC = 0
 815 // bits[19:16] ProbeCBC = 8
 816 // bits[23:20] IsocReqCBC = 1
 817 // bits[26:24] IsocPreqCBC = 1
 818 // bits[31:28] DRReqCBC = 8
 819   {
 820     CoreCountsPciRegister,
 821     {
 822       AMD_FAMILY_10,                      // CpuFamily
 823       AMD_F10_ALL                         // CpuRevision
 824     },
 825     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
 826     {{
 827       PERFORMANCE_PROFILE_ALL,  // Features
 828       (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
 829       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
 830       0x81180101,                           // regData
 831       0xF7FF7777,                           // regMask
 832     }}
 833   },
 834 // F3x74 - XBAR_to_SRI Command Buffer Count
 835 // No Mct Variable Priority or 32 byte requests.
 836 // bits[2:0]   UpReqCBC = 1
 837 // bits[6:4]   DnReqCBC = 0
 838 // bits[10:8]  UpPreqCBC = 1
 839 // bits[14:12] DnPreqCBC = 0
 840 // bits[19:16] ProbeCBC = 8
 841 // bits[23:20] IsocReqCBC = 1
 842 // bits[26:24] IsocPreqCBC = 1
 843 // bits[31:28] DRReqCBC = 7
 844   {
 845     CoreCountsPciRegister,
 846     {
 847       AMD_FAMILY_10,                      // CpuFamily
 848       AMD_F10_ALL                         // CpuRevision
 849     },
 850     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
 851     {{
 852       PERFORMANCE_PROFILE_ALL,  // Features
 853       (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
 854       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
 855       0x71180101,                           // regData
 856       0xF7FF7777,                           // regMask
 857     }}
 858   },
 859 // F3x74 - XBAR_to_SRI Command Buffer Count
 860 // No Mct Variable Priority or 32 byte requests.
 861 // bits[2:0]   UpReqCBC = 1
 862 // bits[6:4]   DnReqCBC = 0
 863 // bits[10:8]  UpPreqCBC = 1
 864 // bits[14:12] DnPreqCBC = 0
 865 // bits[19:16] ProbeCBC = 8
 866 // bits[23:20] IsocReqCBC = 1
 867 // bits[26:24] IsocPreqCBC = 1
 868 // bits[31:28] DRReqCBC = 7
 869   {
 870     CoreCountsPciRegister,
 871     {
 872       AMD_FAMILY_10,                      // CpuFamily
 873       AMD_F10_ALL                         // CpuRevision
 874     },
 875     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
 876     {{
 877       PERFORMANCE_PROFILE_ALL,  // Features
 878       (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
 879       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
 880       0x71180101,                           // regData
 881       0xF7FF7777,                           // regMask
 882     }}
 883   },
 884
 885 // F3x74 - XBAR_to_SRI Command Buffer Count
 886 // bits[2:0]   UpReqCBC = 1
 887 // bits[6:4]   DnReqCBC = 0
 888 // bits[10:8]  UpPreqCBC = 1
 889 // bits[14:12] DnPreqCBC = 0
 890 // bits[19:16] ProbeCBC = 8
 891 // bits[23:20] IsocReqCBC = 1
 892 // bits[26:24] IsocPreqCBC = 1
 893 // bits[31:28] DRReqCBC = C
 894   {
 895     ProfileFixup,
 896     {
 897       AMD_FAMILY_10,                      // CpuFamily
 898       AMD_F10_ALL                         // CpuRevision
 899     },
 900     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
 901     {{
 902       PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
 903       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
 904       0xC1180101,                           // regData
 905       0xF7FF7777,                           // regMask
 906     }}
 907   },
 908 // F3x74 - XBAR_to_SRI Command Buffer Count
 909 // bits[2:0]   UpReqCBC = 1
 910 // bits[6:4]   DnReqCBC = 0
 911 // bits[10:8]  UpPreqCBC = 1
 912 // bits[14:12] DnPreqCBC = 0
 913 // bits[19:16] ProbeCBC = 8
 914 // bits[23:20] IsocReqCBC = 1
 915 // bits[26:24] IsocPreqCBC = 1
 916 // bits[31:28] DRReqCBC = C
 917   {
 918     ProfileFixup,
 919     {
 920       AMD_FAMILY_10,                      // CpuFamily
 921       AMD_F10_ALL                         // CpuRevision
 922     },
 923     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
 924     {{
 925       PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
 926       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
 927       0xC1180101,                           // regData
 928       0xF7FF7777,                           // regMask
 929     }}
 930   },
 931 // F3x74 - XBAR_to_SRI Command Buffer Count
 932 // bits[2:0]   UpReqCBC = 1
 933 // bits[6:4]   DnReqCBC = 0
 934 // bits[10:8]  UpPreqCBC = 1
 935 // bits[14:12] DnPreqCBC = 0
 936 // bits[19:16] ProbeCBC = 8
 937 // bits[23:20] IsocReqCBC = 1
 938 // bits[26:24] IsocPreqCBC = 1
 939 // bits[31:28] DRReqCBC = B
 940   {
 941     CoreCountsPciRegister,
 942     {
 943       AMD_FAMILY_10,                      // CpuFamily
 944       AMD_F10_ALL                         // CpuRevision
 945     },
 946     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
 947     {{
 948       PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
 949       (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
 950       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
 951       0xB1180101,                           // regData
 952       0xF7FF7777,                           // regMask
 953     }}
 954   },
 955 // F3x74 - XBAR_to_SRI Command Buffer Count
 956 // bits[2:0]   UpReqCBC = 1
 957 // bits[6:4]   DnReqCBC = 0
 958 // bits[10:8]  UpPreqCBC = 1
 959 // bits[14:12] DnPreqCBC = 0
 960 // bits[19:16] ProbeCBC = 8
 961 // bits[23:20] IsocReqCBC = 1
 962 // bits[26:24] IsocPreqCBC = 1
 963 // bits[31:28] DRReqCBC = A
 964   {
 965     CoreCountsPciRegister,
 966     {
 967       AMD_FAMILY_10,                      // CpuFamily
 968       AMD_F10_ALL                         // CpuRevision
 969     },
 970     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
 971     {{
 972       PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
 973       (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
 974       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
 975       0xA1180101,                           // regData
 976       0xF7FF7777,                           // regMask
 977     }}
 978   },
 979 // F3x74 - XBAR_to_SRI Command Buffer Count
 980 // bits[2:0]   UpReqCBC = 1
 981 // bits[6:4]   DnReqCBC = 0
 982 // bits[10:8]  UpPreqCBC = 1
 983 // bits[14:12] DnPreqCBC = 0
 984 // bits[19:16] ProbeCBC = 8
 985 // bits[23:20] IsocReqCBC = 1
 986 // bits[26:24] IsocPreqCBC = 1
 987 // bits[31:28] DRReqCBC = B
 988   {
 989     CoreCountsPciRegister,
 990     {
 991       AMD_FAMILY_10,                      // CpuFamily
 992       AMD_F10_ALL                         // CpuRevision
 993     },
 994     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
 995     {{
 996       PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
 997       (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
 998       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
 999       0xB1180101,                           // regData
1000       0xF7FF7777,                           // regMask
1001     }}
1002   },
1003 // F3x74 - XBAR_to_SRI Command Buffer Count
1004 // bits[2:0]   UpReqCBC = 1
1005 // bits[6:4]   DnReqCBC = 0
1006 // bits[10:8]  UpPreqCBC = 1
1007 // bits[14:12] DnPreqCBC = 0
1008 // bits[19:16] ProbeCBC = 8
1009 // bits[23:20] IsocReqCBC = 1
1010 // bits[26:24] IsocPreqCBC = 1
1011 // bits[31:28] DRReqCBC = A
1012   {
1013     CoreCountsPciRegister,
1014     {
1015       AMD_FAMILY_10,                      // CpuFamily
1016       AMD_F10_ALL                         // CpuRevision
1017     },
1018     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
1019     {{
1020       PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
1021       (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
1022       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
1023       0xA1180101,                           // regData
1024       0xF7FF7777,                           // regMask
1025     }}
1026   },
1027 // F3x74 - XBAR_to_SRI Command Buffer Count
1028 // bits[2:0]   UpReqCBC = 1
1029 // bits[6:4]   DnReqCBC = 0
1030 // bits[10:8]  UpPreqCBC = 1
1031 // bits[14:12] DnPreqCBC = 0
1032 // bits[19:16] ProbeCBC = 8
1033 // bits[23:20] IsocReqCBC = 1
1034 // bits[26:24] IsocPreqCBC = 1
1035 // bits[31:28] DRReqCBC = F
1036   {
1037     ProfileFixup,
1038     {
1039       AMD_FAMILY_10,                      // CpuFamily
1040       AMD_F10_ALL                         // CpuRevision
1041     },
1042     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
1043     {{
1044       PERFORMANCE_REFRESH_REQUEST_32B,        // Features
1045       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
1046       0xF1180101,                           // regData
1047       0xF7FF7777,                           // regMask
1048     }}
1049   },
1050 // F3x74 - XBAR_to_SRI Command Buffer Count
1051 // bits[2:0]   UpReqCBC = 1
1052 // bits[6:4]   DnReqCBC = 0
1053 // bits[10:8]  UpPreqCBC = 1
1054 // bits[14:12] DnPreqCBC = 0
1055 // bits[19:16] ProbeCBC = 8
1056 // bits[23:20] IsocReqCBC = 1
1057 // bits[26:24] IsocPreqCBC = 1
1058 // bits[31:28] DRReqCBC = F
1059   {
1060     ProfileFixup,
1061     {
1062       AMD_FAMILY_10,                      // CpuFamily
1063       AMD_F10_ALL                         // CpuRevision
1064     },
1065     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
1066     {{
1067       PERFORMANCE_REFRESH_REQUEST_32B,        // Features
1068       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
1069       0xF1181111,                           // regData
1070       0xF7FF7777,                           // regMask
1071     }}
1072   },
1073 // F3x74 - XBAR_to_SRI Command Buffer Count
1074 // bits[2:0]   UpReqCBC = 1
1075 // bits[6:4]   DnReqCBC = 0
1076 // bits[10:8]  UpPreqCBC = 1
1077 // bits[14:12] DnPreqCBC = 0
1078 // bits[19:16] ProbeCBC = 8
1079 // bits[23:20] IsocReqCBC = 1
1080 // bits[26:24] IsocPreqCBC = 1
1081 // bits[31:28] DRReqCBC = B
1082   {
1083     CoreCountsPciRegister,
1084     {
1085       AMD_FAMILY_10,                      // CpuFamily
1086       AMD_F10_ALL                         // CpuRevision
1087     },
1088     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
1089     {{
1090       PERFORMANCE_REFRESH_REQUEST_32B,        // Features
1091       (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
1092       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
1093       0xB1180101,                           // regData
1094       0xF7FF7777,                           // regMask
1095     }}
1096   },
1097 // F3x74 - XBAR_to_SRI Command Buffer Count
1098 // bits[2:0]   UpReqCBC = 1
1099 // bits[6:4]   DnReqCBC = 0
1100 // bits[10:8]  UpPreqCBC = 1
1101 // bits[14:12] DnPreqCBC = 0
1102 // bits[19:16] ProbeCBC = 8
1103 // bits[23:20] IsocReqCBC = 1
1104 // bits[26:24] IsocPreqCBC = 1
1105 // bits[31:28] DRReqCBC = B
1106   {
1107     CoreCountsPciRegister,
1108     {
1109       AMD_FAMILY_10,                      // CpuFamily
1110       AMD_F10_ALL                         // CpuRevision
1111     },
1112     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
1113     {{
1114       PERFORMANCE_REFRESH_REQUEST_32B,        // Features
1115       (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
1116       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
1117       0xB1180101,                           // regData
1118       0xF7FF7777,                           // regMask
1119     }}
1120   },
1121 // F3x74 - XBAR_to_SRI Command Buffer Count
1122 // bits[2:0]   UpReqCBC = 1
1123 // bits[6:4]   DnReqCBC = 0
1124 // bits[10:8]  UpPreqCBC = 1
1125 // bits[14:12] DnPreqCBC = 0
1126 // bits[19:16] ProbeCBC = 8
1127 // bits[23:20] IsocReqCBC = 1
1128 // bits[26:24] IsocPreqCBC = 1
1129 // bits[31:28] DRReqCBC = A
1130   {
1131     CoreCountsPciRegister,
1132     {
1133       AMD_FAMILY_10,                      // CpuFamily
1134       AMD_F10_ALL                         // CpuRevision
1135     },
1136     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
1137     {{
1138       PERFORMANCE_REFRESH_REQUEST_32B,        // Features
1139       (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
1140       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
1141       0xA1180101,                           // regData
1142       0xF7FF7777,                           // regMask
1143     }}
1144   },
1145 // F3x74 - XBAR_to_SRI Command Buffer Count
1146 // bits[2:0]   UpReqCBC = 1
1147 // bits[6:4]   DnReqCBC = 0
1148 // bits[10:8]  UpPreqCBC = 1
1149 // bits[14:12] DnPreqCBC = 0
1150 // bits[19:16] ProbeCBC = 8
1151 // bits[23:20] IsocReqCBC = 1
1152 // bits[26:24] IsocPreqCBC = 1
1153 // bits[31:28] DRReqCBC = A
1154   {
1155     CoreCountsPciRegister,
1156     {
1157       AMD_FAMILY_10,                      // CpuFamily
1158       AMD_F10_ALL                         // CpuRevision
1159     },
1160     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
1161     {{
1162       PERFORMANCE_REFRESH_REQUEST_32B,        // Features
1163       (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
1164       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
1165       0xA1180101,                           // regData
1166       0xF7FF7777,                           // regMask
1167     }}
1168   },
1169 // F3x74 - XBAR_to_SRI Command Buffer Count
1170 // bits[2:0]   UpReqCBC = 1
1171 // bits[6:4]   DnReqCBC = 0
1172 // bits[10:8]  UpPreqCBC = 1
1173 // bits[14:12] DnPreqCBC = 0
1174 // bits[19:16] ProbeCBC = 8
1175 // bits[23:20] IsocReqCBC = 1
1176 // bits[26:24] IsocPreqCBC = 1
1177 // bits[31:28] DRReqCBC = E
1178   {
1179     CoreCountsPciRegister,
1180     {
1181       AMD_FAMILY_10,                      // CpuFamily
1182       AMD_F10_ALL                         // CpuRevision
1183     },
1184     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
1185     {{
1186       PERFORMANCE_REFRESH_REQUEST_32B,        // Features
1187       (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
1188       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
1189       0xE1180101,                           // regData
1190       0xF7FF7777,                           // regMask
1191     }}
1192   },
1193 // F3x74 - XBAR_to_SRI Command Buffer Count
1194 // bits[2:0]   UpReqCBC = 1
1195 // bits[6:4]   DnReqCBC = 0
1196 // bits[10:8]  UpPreqCBC = 1
1197 // bits[14:12] DnPreqCBC = 0
1198 // bits[19:16] ProbeCBC = 8
1199 // bits[23:20] IsocReqCBC = 1
1200 // bits[26:24] IsocPreqCBC = 1
1201 // bits[31:28] DRReqCBC = E
1202   {
1203     CoreCountsPciRegister,
1204     {
1205       AMD_FAMILY_10,                      // CpuFamily
1206       AMD_F10_ALL                         // CpuRevision
1207     },
1208     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
1209     {{
1210       PERFORMANCE_REFRESH_REQUEST_32B,        // Features
1211       (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
1212       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
1213       0xE1180101,                           // regData
1214       0xF7FF7777,                           // regMask
1215     }}
1216   },
1217 // F3x74 - XBAR_to_SRI Command Buffer Count
1218 // bits[2:0]   UpReqCBC = 1
1219 // bits[6:4]   DnReqCBC = 0
1220 // bits[10:8]  UpPreqCBC = 1
1221 // bits[14:12] DnPreqCBC = 0
1222 // bits[19:16] ProbeCBC = 8
1223 // bits[23:20] IsocReqCBC = 1
1224 // bits[26:24] IsocPreqCBC = 1
1225 // bits[31:28] DRReqCBC = D
1226   {
1227     CoreCountsPciRegister,
1228     {
1229       AMD_FAMILY_10,                      // CpuFamily
1230       AMD_F10_ALL                         // CpuRevision
1231     },
1232     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
1233     {{
1234       PERFORMANCE_REFRESH_REQUEST_32B,        // Features
1235       (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
1236       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
1237       0xD1180101,                           // regData
1238       0xF7FF7777,                           // regMask
1239     }}
1240   },
1241 // F3x74 - XBAR_to_SRI Command Buffer Count
1242 // bits[2:0]   UpReqCBC = 1
1243 // bits[6:4]   DnReqCBC = 0
1244 // bits[10:8]  UpPreqCBC = 1
1245 // bits[14:12] DnPreqCBC = 0
1246 // bits[19:16] ProbeCBC = 8
1247 // bits[23:20] IsocReqCBC = 1
1248 // bits[26:24] IsocPreqCBC = 1
1249 // bits[31:28] DRReqCBC = D
1250   {
1251     CoreCountsPciRegister,
1252     {
1253       AMD_FAMILY_10,                      // CpuFamily
1254       AMD_F10_ALL                         // CpuRevision
1255     },
1256     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
1257     {{
1258       PERFORMANCE_REFRESH_REQUEST_32B,        // Features
1259       (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
1260       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
1261       0xD1180101,                           // regData
1262       0xF7FF7777,                           // regMask
1263     }}
1264   },
1265
1266 // F3x74 - XBAR_to_SRI Command Buffer Count
1267 // bits[2:0]   UpReqCBC = 1
1268 // bits[6:4]   DnReqCBC = 0
1269 // bits[10:8]  UpPreqCBC = 1
1270 // bits[14:12] DnPreqCBC = 0
1271 // bits[19:16] ProbeCBC = 8
1272 // bits[23:20] IsocReqCBC = 8
1273 // bits[26:24] IsocPreqCBC = 1
1274 // bits[31:28] DRReqCBC = 0
1275   {
1276     PciRegister,
1277     {
1278       AMD_FAMILY_10,                      // CpuFamily
1279       AMD_F10_ALL                         // CpuRevision
1280     },
1281     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, // platform Features
1282     {{
1283       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
1284       0x01880101,                           // regData
1285       0xF7FF7777,                           // regMask
1286     }}
1287   },
1288 // F3x7C - Free List Buffer Count
1289 // bits[4:0]  Xbar2SriFreeListCBC = 20
1290 // bits[11:8] Sri2XbarFreeXreqCBC = 9
1291 // bits[15:12] Sri2XbarFreeRspCBC = 0
1292 // bits[19:16] Sri2XbarFreeXreqDBC = 9
1293 // bits[22:20] Sri2XbarFreeRspDBC = 0
1294   {
1295     PciRegister,
1296     {
1297       AMD_FAMILY_10,                      // CpuFamily
1298       AMD_F10_ALL                         // CpuRevision
1299     },
1300     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) },  // platform Features
1301     {{
1302       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1303       0x00090914,                           // regData
1304       0x007FFF1F,                           // regMask
1305     }}
1306   },
1307 // F3x7C - Free List Buffer Count
1308 // No Mct Variable Priority or 32 byte requests.
1309 // bits[4:0]  Xbar2SriFreeListCBC = 15
1310 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1311 // bits[15:12] Sri2XbarFreeRspCBC = 0
1312 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1313 // bits[22:20] Sri2XbarFreeRspDBC = 0
1314   {
1315     PciRegister,
1316     {
1317       AMD_FAMILY_10,                      // CpuFamily
1318       AMD_F10_ALL                         // CpuRevision
1319     },
1320     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
1321     {{
1322       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1323       0x0007080F,                           // regData
1324       0x007FFF1F,                           // regMask
1325     }}
1326   },
1327 // F3x7C - Free List Buffer Count
1328 // No Mct Variable Priority or 32 byte requests.
1329 // bits[4:0]  Xbar2SriFreeListCBC = 15
1330 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1331 // bits[15:12] Sri2XbarFreeRspCBC = 0
1332 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1333 // bits[22:20] Sri2XbarFreeRspDBC = 0
1334   {
1335     PciRegister,
1336     {
1337       AMD_FAMILY_10,                      // CpuFamily
1338       AMD_F10_ALL                         // CpuRevision
1339     },
1340     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
1341     {{
1342       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1343       0x0007080F,                           // regData
1344       0x007FFF1F,                           // regMask
1345     }}
1346   },
1347 // F3x7C - Free List Buffer Count
1348 // bits[4:0]  Xbar2SriFreeListCBC = 12
1349 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1350 // bits[15:12] Sri2XbarFreeRspCBC = 0
1351 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1352 // bits[22:20] Sri2XbarFreeRspDBC = 0
1353   {
1354     ProfileFixup,
1355     {
1356       AMD_FAMILY_10,                      // CpuFamily
1357       AMD_F10_ALL                         // CpuRevision
1358     },
1359     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
1360     {{
1361       PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
1362       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1363       0x0007080C,                           // regData
1364       0x007FFF1F,                           // regMask
1365     }}
1366   },
1367 // F3x7C - Free List Buffer Count
1368 // bits[4:0]  Xbar2SriFreeListCBC = 12
1369 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1370 // bits[15:12] Sri2XbarFreeRspCBC = 0
1371 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1372 // bits[22:20] Sri2XbarFreeRspDBC = 0
1373   {
1374     ProfileFixup,
1375     {
1376       AMD_FAMILY_10,                      // CpuFamily
1377       AMD_F10_ALL                         // CpuRevision
1378     },
1379     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
1380     {{
1381       PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
1382       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1383       0x0007080C,                           // regData
1384       0x007FFF1F,                           // regMask
1385     }}
1386   },
1387 // F3x7C - Free List Buffer Count
1388 // bits[4:0]  Xbar2SriFreeListCBC = 9
1389 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1390 // bits[15:12] Sri2XbarFreeRspCBC = 0
1391 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1392 // bits[22:20] Sri2XbarFreeRspDBC = 0
1393   {
1394     ProfileFixup,
1395     {
1396       AMD_FAMILY_10,                      // CpuFamily
1397       AMD_F10_ALL                         // CpuRevision
1398     },
1399     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
1400     {{
1401       PERFORMANCE_REFRESH_REQUEST_32B,              // Features
1402       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1403       0x00070809,                           // regData
1404       0x007FFF1F,                           // regMask
1405     }}
1406   },
1407 // F3x7C - Free List Buffer Count
1408 // bits[4:0]  Xbar2SriFreeListCBC = 9
1409 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1410 // bits[15:12] Sri2XbarFreeRspCBC = 0
1411 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1412 // bits[22:20] Sri2XbarFreeRspDBC = 0
1413   {
1414     ProfileFixup,
1415     {
1416       AMD_FAMILY_10,                      // CpuFamily
1417       AMD_F10_ALL                         // CpuRevision
1418     },
1419     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
1420     {{
1421       PERFORMANCE_REFRESH_REQUEST_32B ,              // Features
1422       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1423       0x00070809,                           // regData
1424       0x007FFF1F,                           // regMask
1425     }}
1426   },
1427 // F3x7C - Free List Buffer Count
1428 // bits[4:0]  Xbar2SriFreeListCBC = 17
1429 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1430 // bits[15:12] Sri2XbarFreeRspCBC = 0
1431 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1432 // bits[22:20] Sri2XbarFreeRspDBC = 0
1433   {
1434     PciRegister,
1435     {
1436       AMD_FAMILY_10,                      // CpuFamily
1437       AMD_F10_ALL                         // CpuRevision
1438     },
1439     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },  // platform Features
1440     {{
1441       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1442       0x00070811,                           // regData
1443       0x007FFF1F,                           // regMask
1444     }}
1445   },
1446 // F3x7C - Free List Buffer Count
1447 // bits[4:0]  Xbar2SriFreeListCBC = 20
1448 // bits[11:8] Sri2XbarFreeXreqCBC = 9
1449 // bits[15:12] Sri2XbarFreeRspCBC = 0
1450 // bits[19:16] Sri2XbarFreeXreqDBC = 9
1451 // bits[22:20] Sri2XbarFreeRspDBC = 0
1452   {
1453     PciRegister,
1454     {
1455       AMD_FAMILY_10,                      // CpuFamily
1456       AMD_F10_ALL                         // CpuRevision
1457     },
1458     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },  // platform Features
1459     {{
1460       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1461       0x00090914,                           // regData
1462       0x007FFF1F,                           // regMask
1463     }}
1464   },
1465 // F3x7C - Free List Buffer Count
1466 // No Mct Variable Priority or 32 byte requests.
1467 // bits[4:0]  Xbar2SriFreeListCBC = 14
1468 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1469 // bits[15:12] Sri2XbarFreeRspCBC = 0
1470 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1471 // bits[22:20] Sri2XbarFreeRspDBC = 0
1472   {
1473     CoreCountsPciRegister,
1474     {
1475       AMD_FAMILY_10,                      // CpuFamily
1476       AMD_F10_ALL                         // CpuRevision
1477     },
1478     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
1479     {{
1480       PERFORMANCE_PROFILE_ALL,
1481       (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
1482       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1483       0x0007080E,                           // regData
1484       0x007FFF1F,                           // regMask
1485     }}
1486   },
1487 // F3x7C - Free List Buffer Count
1488 // No Mct Variable Priority or 32 byte requests.
1489 // bits[4:0]  Xbar2SriFreeListCBC = 14
1490 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1491 // bits[15:12] Sri2XbarFreeRspCBC = 0
1492 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1493 // bits[22:20] Sri2XbarFreeRspDBC = 0
1494   {
1495     CoreCountsPciRegister,
1496     {
1497       AMD_FAMILY_10,                      // CpuFamily
1498       AMD_F10_ALL                         // CpuRevision
1499     },
1500     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
1501     {{
1502       PERFORMANCE_PROFILE_ALL,
1503       (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
1504       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1505       0x0007080E,                           // regData
1506       0x007FFF1F,                           // regMask
1507     }}
1508   },
1509 // F3x7C - Free List Buffer Count
1510 // No Mct Variable Priority or 32 byte requests.
1511 // bits[4:0]  Xbar2SriFreeListCBC = 13
1512 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1513 // bits[15:12] Sri2XbarFreeRspCBC = 0
1514 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1515 // bits[22:20] Sri2XbarFreeRspDBC = 0
1516   {
1517     CoreCountsPciRegister,
1518     {
1519       AMD_FAMILY_10,                      // CpuFamily
1520       AMD_F10_ALL                         // CpuRevision
1521     },
1522     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
1523     {{
1524       PERFORMANCE_PROFILE_ALL,
1525       (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
1526       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1527       0x0007080D,                           // regData
1528       0x007FFF1F,                           // regMask
1529     }}
1530   },
1531 // F3x7C - Free List Buffer Count
1532 // No Mct Variable Priority or 32 byte requests.
1533 // bits[4:0]  Xbar2SriFreeListCBC = 13
1534 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1535 // bits[15:12] Sri2XbarFreeRspCBC = 0
1536 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1537 // bits[22:20] Sri2XbarFreeRspDBC = 0
1538   {
1539     CoreCountsPciRegister,
1540     {
1541       AMD_FAMILY_10,                      // CpuFamily
1542       AMD_F10_ALL                         // CpuRevision
1543     },
1544     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
1545     {{
1546       PERFORMANCE_PROFILE_ALL,
1547       (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
1548       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1549       0x0007080D,                           // regData
1550       0x007FFF1F,                           // regMask
1551     }}
1552   },
1553 // F3x7C - Free List Buffer Count
1554 // bits[4:0]  Xbar2SriFreeListCBC = 11
1555 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1556 // bits[15:12] Sri2XbarFreeRspCBC = 0
1557 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1558 // bits[22:20] Sri2XbarFreeRspDBC = 0
1559   {
1560     CoreCountsPciRegister,
1561     {
1562       AMD_FAMILY_10,                      // CpuFamily
1563       AMD_F10_ALL                         // CpuRevision
1564     },
1565     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
1566     {{
1567       PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
1568       (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
1569       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1570       0x0007080B,                           // regData
1571       0x007FFF1F,                           // regMask
1572     }}
1573   },
1574 // F3x7C - Free List Buffer Count
1575 // bits[4:0]  Xbar2SriFreeListCBC = 11
1576 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1577 // bits[15:12] Sri2XbarFreeRspCBC = 0
1578 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1579 // bits[22:20] Sri2XbarFreeRspDBC = 0
1580   {
1581     CoreCountsPciRegister,
1582     {
1583       AMD_FAMILY_10,                      // CpuFamily
1584       AMD_F10_ALL                         // CpuRevision
1585     },
1586     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
1587     {{
1588       PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
1589       (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
1590       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1591       0x0007080B,                           // regData
1592       0x007FFF1F,                           // regMask
1593     }}
1594   },
1595 // F3x7C - Free List Buffer Count
1596 // bits[4:0]  Xbar2SriFreeListCBC = 10
1597 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1598 // bits[15:12] Sri2XbarFreeRspCBC = 0
1599 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1600 // bits[22:20] Sri2XbarFreeRspDBC = 0
1601   {
1602     CoreCountsPciRegister,
1603     {
1604       AMD_FAMILY_10,                      // CpuFamily
1605       AMD_F10_ALL                         // CpuRevision
1606     },
1607     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
1608     {{
1609       PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
1610       (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
1611       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1612       0x0007080A,                           // regData
1613       0x007FFF1F,                           // regMask
1614     }}
1615   },
1616 // F3x7C - Free List Buffer Count
1617 // bits[4:0]  Xbar2SriFreeListCBC = 10
1618 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1619 // bits[15:12] Sri2XbarFreeRspCBC = 0
1620 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1621 // bits[22:20] Sri2XbarFreeRspDBC = 0
1622   {
1623     CoreCountsPciRegister,
1624     {
1625       AMD_FAMILY_10,                      // CpuFamily
1626       AMD_F10_ALL                         // CpuRevision
1627     },
1628     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
1629     {{
1630       PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
1631       (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
1632       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1633       0x0007080A,                           // regData
1634       0x007FFF1F,                           // regMask
1635     }}
1636   },
1637 // F3x7C - Free List Buffer Count
1638 // bits[4:0]  Xbar2SriFreeListCBC = 8
1639 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1640 // bits[15:12] Sri2XbarFreeRspCBC = 0
1641 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1642 // bits[22:20] Sri2XbarFreeRspDBC = 0
1643   {
1644     CoreCountsPciRegister,
1645     {
1646       AMD_FAMILY_10,                      // CpuFamily
1647       AMD_F10_ALL                         // CpuRevision
1648     },
1649     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
1650     {{
1651       PERFORMANCE_REFRESH_REQUEST_32B,              // Features
1652       (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
1653       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1654       0x00070808,                           // regData
1655       0x007FFF1F,                           // regMask
1656     }}
1657   },
1658 // F3x7C - Free List Buffer Count
1659 // bits[4:0]  Xbar2SriFreeListCBC = 8
1660 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1661 // bits[15:12] Sri2XbarFreeRspCBC = 0
1662 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1663 // bits[22:20] Sri2XbarFreeRspDBC = 0
1664   {
1665     CoreCountsPciRegister,
1666     {
1667       AMD_FAMILY_10,                      // CpuFamily
1668       AMD_F10_ALL                         // CpuRevision
1669     },
1670     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
1671     {{
1672       PERFORMANCE_REFRESH_REQUEST_32B ,              // Features
1673       (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
1674       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1675       0x00070808,                           // regData
1676       0x007FFF1F,                           // regMask
1677     }}
1678   },
1679 // F3x7C - Free List Buffer Count
1680 // bits[4:0]  Xbar2SriFreeListCBC = 7
1681 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1682 // bits[15:12] Sri2XbarFreeRspCBC = 0
1683 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1684 // bits[22:20] Sri2XbarFreeRspDBC = 0
1685   {
1686     CoreCountsPciRegister,
1687     {
1688       AMD_FAMILY_10,                      // CpuFamily
1689       AMD_F10_ALL                         // CpuRevision
1690     },
1691     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
1692     {{
1693       PERFORMANCE_REFRESH_REQUEST_32B,              // Features
1694       (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
1695       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1696       0x00070807,                           // regData
1697       0x007FFF1F,                           // regMask
1698     }}
1699   },
1700 // F3x7C - Free List Buffer Count
1701 // bits[4:0]  Xbar2SriFreeListCBC = 7
1702 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1703 // bits[15:12] Sri2XbarFreeRspCBC = 0
1704 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1705 // bits[22:20] Sri2XbarFreeRspDBC = 0
1706   {
1707     CoreCountsPciRegister,
1708     {
1709       AMD_FAMILY_10,                      // CpuFamily
1710       AMD_F10_ALL                         // CpuRevision
1711     },
1712     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
1713     {{
1714       PERFORMANCE_REFRESH_REQUEST_32B ,              // Features
1715       (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
1716       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1717       0x00070807,                           // regData
1718       0x007FFF1F,                           // regMask
1719     }}
1720   },
1721 // F3x7C - Free List Buffer Count
1722 // bits[4:0]  Xbar2SriFreeListCBC = 16
1723 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1724 // bits[15:12] Sri2XbarFreeRspCBC = 0
1725 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1726 // bits[22:20] Sri2XbarFreeRspDBC = 0
1727   {
1728     CoreCountsPciRegister,
1729     {
1730       AMD_FAMILY_10,                      // CpuFamily
1731       AMD_F10_ALL                         // CpuRevision
1732     },
1733     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },  // platform Features
1734     {{
1735       PERFORMANCE_PROFILE_ALL,
1736       (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
1737       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1738       0x00070810,                           // regData
1739       0x707FFF1F,                           // regMask
1740     }}
1741   },
1742 // F3x7C - Free List Buffer Count
1743 // bits[4:0]  Xbar2SriFreeListCBC = 15
1744 // bits[11:8] Sri2XbarFreeXreqCBC = 8
1745 // bits[15:12] Sri2XbarFreeRspCBC = 0
1746 // bits[19:16] Sri2XbarFreeXreqDBC = 7
1747 // bits[22:20] Sri2XbarFreeRspDBC = 0
1748   {
1749     CoreCountsPciRegister,
1750     {
1751       AMD_FAMILY_10,                      // CpuFamily
1752       AMD_F10_ALL                         // CpuRevision
1753     },
1754     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },  // platform Features
1755     {{
1756       PERFORMANCE_PROFILE_ALL,
1757       (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
1758       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
1759       0x0007080F,                           // regData
1760       0x707FFF1F,                           // regMask
1761     }}
1762   },
1763 // F3x7C - Free List Buffer Count
1764 // bits[4:0]  Xbar2SriFreeListCBC = 22, 1-core without L3 cache is 22
1765   {
1766     CoreCountsPciRegister,
1767     {
1768       AMD_FAMILY_10,                      // CpuFamily
1769       AMD_F10_ALL                         // CpuRevision
1770     },
1771     {AMD_PF_SINGLE_LINK},                   // platformFeatures
1772     {{
1773       PERFORMANCE_NO_L3_CACHE,
1774       (CORE_RANGE_0 (1, 1) | COUNT_RANGE_NONE), // 1 core.
1775       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
1776       0x00000016,                               // regData
1777       0x0000001F,                               // regMask
1778     }}
1779   },
1780 // F3x7C - Free List Buffer Count
1781 // bits[4:0]  Xbar2SriFreeListCBC = 20, 2-core is 20
1782   {
1783     CoreCountsPciRegister,
1784     {
1785       AMD_FAMILY_10,                      // CpuFamily
1786       AMD_F10_ALL                         // CpuRevision
1787     },
1788     {AMD_PF_SINGLE_LINK},                   // platformFeatures
1789     {{
1790       PERFORMANCE_NO_L3_CACHE,
1791       (CORE_RANGE_0 (2, 2) | COUNT_RANGE_NONE), // 2 core.
1792       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
1793       0x00000014,                               // regData
1794       0x0000001F,                               // regMask
1795     }}
1796   },
1797 // F3x7C - Free List Buffer Count
1798 // bits[4:0]  Xbar2SriFreeListCBC = 18, 3-core without L3 cache is 18.
1799   {
1800     CoreCountsPciRegister,
1801     {
1802       AMD_FAMILY_10,                      // CpuFamily
1803       AMD_F10_ALL                         // CpuRevision
1804     },
1805     {AMD_PF_SINGLE_LINK},                   // platformFeatures
1806     {{
1807       PERFORMANCE_NO_L3_CACHE,
1808       (CORE_RANGE_0 (3, 3) | COUNT_RANGE_NONE), // 3 core.
1809       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
1810       0x00000012,                               // regData
1811       0x0000001F,                               // regMask
1812     }}
1813   },
1814 // F3x7C - Free List Buffer Count
1815 // bits[4:0]  Xbar2SriFreeListCBC = 14, 4-core without L3 cache is 16.
1816   {
1817     CoreCountsPciRegister,
1818     {
1819       AMD_FAMILY_10,                      // CpuFamily
1820       AMD_F10_ALL                         // CpuRevision
1821     },
1822     {AMD_PF_SINGLE_LINK},                   // platformFeatures
1823     {{
1824       PERFORMANCE_NO_L3_CACHE,
1825       (CORE_RANGE_0 (4, 4) | COUNT_RANGE_NONE), // 4 core.
1826       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
1827       0x00000010,                               // regData
1828       0x0000001F,                               // regMask
1829     }}
1830   },
1831 // F3x7C - Free List Buffer Count
1832 // bits[4:0]  Xbar2SriFreeListCBC = 14, 5-core without L3 cache is 14.
1833   {
1834     CoreCountsPciRegister,
1835     {
1836       AMD_FAMILY_10,                      // CpuFamily
1837       AMD_F10_ALL                         // CpuRevision
1838     },
1839     {AMD_PF_SINGLE_LINK},                   // platformFeatures
1840     {{
1841       PERFORMANCE_NO_L3_CACHE,
1842       (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 core.
1843       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
1844       0x0000000E,                               // regData
1845       0x0000001F,                               // regMask
1846     }}
1847   },
1848 // F3x7C - Free List Buffer Count
1849 // bits[4:0]  Xbar2SriFreeListCBC = 12, 6-core without L3 cache is 12.
1850   {
1851     CoreCountsPciRegister,
1852     {
1853       AMD_FAMILY_10,                      // CpuFamily
1854       AMD_F10_ALL                         // CpuRevision
1855     },
1856     {AMD_PF_SINGLE_LINK},                   // platformFeatures
1857     {{
1858       PERFORMANCE_NO_L3_CACHE,
1859       (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 core.
1860       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
1861       0x0000000C,                               // regData
1862       0x0000001F,                               // regMask
1863     }}
1864   },
1865 // F3x140 - SRI_to_XCS Token Count
1866 // bits[1:0] UpReqTok = 2
1867 // bits[3:2] DnReqTok = 1
1868 // bits[5:4] UpPreqTokC = 1
1869 // bits[7:6] DnPreqTok = 1
1870 // bits[9:8] UpRspTok = 3
1871 // bits[11:10] DnRspTok = 1
1872 // bits[13:12] IsocReqTok = 0
1873 // bits[15:14] IsocPreqTok = 0
1874 // bits[17:16] IsocRspTok = 0
1875 // bits[23:20] FreeTok = 8
1876   {
1877     PciRegister,
1878     {
1879       AMD_FAMILY_10,                      // CpuFamily
1880       AMD_F10_ALL                         // CpuRevision
1881     },
1882     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) },  // platform Features
1883     {{
1884       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
1885       0x00800756,                           // regData
1886       0x00F3FFFF,                           // regMask
1887     }}
1888   },
1889 // F3x140 - SRI_to_XCS Token Count
1890 // bits[1:0] UpReqTok = 2
1891 // bits[3:2] DnReqTok = 1
1892 // bits[5:4] UpPreqTokC = 1
1893 // bits[7:6] DnPreqTok = 1
1894 // bits[9:8] UpRspTok = 3
1895 // bits[11:10] DnRspTok = 1
1896 // bits[13:12] IsocReqTok = 3
1897 // bits[15:14] IsocPreqTok = 1
1898 // bits[17:16] IsocRspTok = 3
1899 // bits[23:20] FreeTok = 12
1900   {
1901     PciRegister,
1902     {
1903       AMD_FAMILY_10,                      // CpuFamily
1904       AMD_F10_ALL                         // CpuRevision
1905     },
1906     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
1907     {{
1908       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
1909       0x00C37756,                           // regData
1910       0x00F3FFFF,                           // regMask
1911     }}
1912   },
1913 // F3x140 - SRI_to_XCS Token Count
1914 // bits[1:0] UpReqTok = 2
1915 // bits[3:2] DnReqTok = 1
1916 // bits[5:4] UpPreqTokC = 1
1917 // bits[7:6] DnPreqTok = 1
1918 // bits[9:8] UpRspTok = 3
1919 // bits[11:10] DnRspTok = 1
1920 // bits[13:12] IsocReqTok = 3
1921 // bits[15:14] IsocPreqTok = 1
1922 // bits[17:16] IsocRspTok = 3
1923 // bits[23:20] FreeTok = 12
1924   {
1925     PciRegister,
1926     {
1927       AMD_FAMILY_10,                      // CpuFamily
1928       AMD_F10_ALL                         // CpuRevision
1929     },
1930     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
1931     {{
1932       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
1933       0x00C37756,                           // regData
1934       0x00F3FFFF,                           // regMask
1935     }}
1936   },
1937 // F3x140 - SRI_to_XCS Token Count
1938 // bits[1:0] UpReqTok = 2
1939 // bits[3:2] DnReqTok = 1
1940 // bits[5:4] UpPreqTokC = 1
1941 // bits[7:6] DnPreqTok = 1
1942 // bits[9:8] UpRspTok = 2
1943 // bits[11:10] DnRspTok = 1
1944 // bits[13:12] IsocReqTok = 3
1945 // bits[15:14] IsocPreqTok = 1
1946 // bits[17:16] IsocRspTok = 3
1947 // bits[23:20] FreeTok = 12
1948   {
1949     PciRegister,
1950     {
1951       AMD_FAMILY_10,                      // CpuFamily
1952       AMD_F10_ALL                         // CpuRevision
1953     },
1954     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },  // platform Features
1955     {{
1956       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
1957       0x00C37656,                           // regData
1958       0x00F3FFFF,                           // regMask
1959     }}
1960   },
1961 // F3x140 - SRI_to_XCS Token Count
1962 // bits[1:0] UpReqTok = 2
1963 // bits[3:2] DnReqTok = 1
1964 // bits[5:4] UpPreqTokC = 1
1965 // bits[7:6] DnPreqTok = 1
1966 // bits[9:8] UpRspTok = 3
1967 // bits[11:10] DnRspTok = 1
1968 // bits[13:12] IsocReqTok = 1
1969 // bits[15:14] IsocPreqTok = 1
1970 // bits[17:16] IsocRspTok = 1
1971 // bits[23:20] FreeTok = 8
1972   {
1973     PciRegister,
1974     {
1975       AMD_FAMILY_10,                      // CpuFamily
1976       AMD_F10_ALL                         // CpuRevision
1977     },
1978     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },  // platform Features
1979     {{
1980       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
1981       0x00815756,                           // regData
1982       0x00F3FFFF,                           // regMask
1983     }}
1984   },
1985 // F3x144 - MCT to XCS Token Count
1986 // bits[3:0] RspTok = 3
1987 // bits[7:4] ProbeTok = 3
1988   {
1989     PciRegister,
1990     {
1991       AMD_FAMILY_10,                      // CpuFamily
1992       AMD_F10_ALL                         // CpuRevision
1993     },
1994     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) },  // platform Features
1995     {{
1996       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
1997       0x00000033,                           // regData
1998       0x000000FF,                           // regMask
1999     }}
2000   },
2001 // F3x144 - MCT to XCS Token Count
2002 // bits[3:0] RspTok = 6
2003 // bits[7:4] ProbeTok = 3
2004   {
2005     PciRegister,
2006     {
2007       AMD_FAMILY_10,                      // CpuFamily
2008       AMD_F10_ALL                         // CpuRevision
2009     },
2010     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
2011     {{
2012       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
2013       0x00000036,                           // regData
2014       0x000000FF,                           // regMask
2015     }}
2016   },
2017 // F3x144 - MCT to XCS Token Count
2018 // bits[3:0] RspTok = 6
2019 // bits[7:4] ProbeTok = 3
2020   {
2021     PciRegister,
2022     {
2023       AMD_FAMILY_10,                      // CpuFamily
2024       AMD_F10_ALL                         // CpuRevision
2025     },
2026     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
2027     {{
2028       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
2029       0x00000036,                           // regData
2030       0x000000FF,                           // regMask
2031     }}
2032   },
2033 // F3x144 - MCT to XCS Token Count
2034 // bits[3:0] RspTok = 6
2035 // bits[7:4] ProbeTok = 3
2036   {
2037     PciRegister,
2038     {
2039       AMD_FAMILY_10,                      // CpuFamily
2040       AMD_F10_ALL                         // CpuRevision
2041     },
2042     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },  // platform Features
2043     {{
2044       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
2045       0x00000036,                           // regData
2046       0x000000FF,                           // regMask
2047     }}
2048   },
2049 // F3x144 - MCT to XCS Token Count
2050 // bits[3:0] RspTok = 3
2051 // bits[7:4] ProbeTok = 3
2052   {
2053     PciRegister,
2054     {
2055       AMD_FAMILY_10,                      // CpuFamily
2056       AMD_F10_ALL                         // CpuRevision
2057     },
2058     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },  // platform Features
2059     {{
2060       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
2061       0x00000033,                           // regData
2062       0x000000FF,                           // regMask
2063     }}
2064   },
2065 // F3x148 - Link to XCS Token Count
2066 // bits[1:0] ReqTok0 = 2
2067 // bits[3:2] PReqTok0 = 2
2068 // bits[5:4] RspTok0 = 2
2069 // bits[7:6] ProbeTok0 = 2
2070 // bits[9:8] IsocReqTok0 = 0
2071 // bits[11:10] IsocPreqTok0 = 0
2072 // bits[13:12] IsocRspTok0 = 0
2073 // bits[15:14] FreeTok[1:0] = 3
2074 // bits[17:16] ReqTok1 = 0
2075 // bits[19:18] PReqTok1 = 0
2076 // bits[21:20] RspTok1 = 0
2077 // bits[23:22] ProbeTok1= 0
2078 // bits[24] IsocReqTok1 = 0
2079 // bits[25] IsocPreqTok1 = 0
2080 // bits[28] IsocRspTok1 = 0
2081 // bits[31:30] FreeTok[3:2] = 0
2082   {
2083     PciRegister,
2084     {
2085       AMD_FAMILY_10,                      // CpuFamily
2086       AMD_F10_ALL                         // CpuRevision
2087     },
2088     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) },  // platform Features
2089     {{
2090       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
2091       0x0000C0AA,                           // regData
2092       0xD5FFFFFF,                           // regMask
2093     }}
2094   },
2095 // F3x148 - Link to XCS Token Count
2096 // bits[1:0] ReqTok0 = 2
2097 // bits[3:2] PReqTok0 = 2
2098 // bits[5:4] RspTok0 = 2
2099 // bits[7:6] ProbeTok0 = 0
2100 // bits[9:8] IsocReqTok0 = 1
2101 // bits[11:10] IsocPreqTok0 = 1
2102 // bits[13:12] IsocRspTok0 = 0
2103 // bits[15:14] FreeTok[1:0] = 0
2104 // bits[17:16] ReqTok1 = 0
2105 // bits[19:18] PReqTok1 = 0
2106 // bits[21:20] RspTok1 = 0
2107 // bits[23:22] ProbeTok1= 0
2108 // bits[24] IsocReqTok1 = 0
2109 // bits[25] IsocPreqTok1 = 0
2110 // bits[28] IsocRspTok1 = 0
2111 // bits[31:30] FreeTok[3:2] = 2
2112   {
2113     PciRegister,
2114     {
2115       AMD_FAMILY_10,                      // CpuFamily
2116       AMD_F10_ALL                         // CpuRevision
2117     },
2118     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
2119     {{
2120       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
2121       0x8000052A,                           // regData
2122       0xD5FFFFFF,                           // regMask
2123     }}
2124   },
2125 // F3x148 - Link to XCS Token Count
2126 // bits[1:0] ReqTok0 = 2
2127 // bits[3:2] PReqTok0 = 2
2128 // bits[5:4] RspTok0 = 2
2129 // bits[7:6] ProbeTok0 = 0
2130 // bits[9:8] IsocReqTok0 = 1
2131 // bits[11:10] IsocPreqTok0 = 1
2132 // bits[13:12] IsocRspTok0 = 0
2133 // bits[15:14] FreeTok[1:0] = 0
2134 // bits[17:16] ReqTok1 = 0
2135 // bits[19:18] PReqTok1 = 0
2136 // bits[21:20] RspTok1 = 0
2137 // bits[23:22] ProbeTok1= 0
2138 // bits[24] IsocReqTok1 = 0
2139 // bits[25] IsocPreqTok1 = 0
2140 // bits[28] IsocRspTok1 = 0
2141 // bits[31:30] FreeTok[3:2] = 2
2142   {
2143     PciRegister,
2144     {
2145       AMD_FAMILY_10,                      // CpuFamily
2146       AMD_F10_ALL                         // CpuRevision
2147     },
2148     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
2149     {{
2150       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
2151       0x8000052A,                           // regData
2152       0xD5FFFFFF,                           // regMask
2153     }}
2154   },
2155 // F3x148 - Link to XCS Token Count
2156 // bits[1:0] ReqTok0 = 2
2157 // bits[3:2] PReqTok0 = 2
2158 // bits[5:4] RspTok0 = 2
2159 // bits[7:6] ProbeTok0 = 2
2160 // bits[9:8] IsocReqTok0 = 0
2161 // bits[11:10] IsocPreqTok0 = 0
2162 // bits[13:12] IsocRspTok0 = 0
2163 // bits[15:14] FreeTok[1:0] = 3
2164 // bits[17:16] ReqTok1 = 0
2165 // bits[19:18] PReqTok1 = 0
2166 // bits[21:20] RspTok1 = 0
2167 // bits[23:22] ProbeTok1= 0
2168 // bits[24] IsocReqTok1 = 0
2169 // bits[25] IsocPreqTok1 = 0
2170 // bits[28] IsocRspTok1 = 0
2171 // bits[31:30] FreeTok[3:2] = 0
2172   {
2173     PciRegister,
2174     {
2175       AMD_FAMILY_10,                      // CpuFamily
2176       AMD_F10_ALL                         // CpuRevision
2177     },
2178     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },  // platform Features
2179     {{
2180       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
2181       0x0000C0AA,                           // regData
2182       0xD5FFFFFF,                           // regMask
2183     }}
2184   },
2185 // F3x148 - Link to XCS Token Count
2186 // bits[1:0] ReqTok0 = 2
2187 // bits[3:2] PReqTok0 = 2
2188 // bits[5:4] RspTok0 = 2
2189 // bits[7:6] ProbeTok0 = 0
2190 // bits[9:8] IsocReqTok0 = 1
2191 // bits[11:10] IsocPreqTok0 = 1
2192 // bits[13:12] IsocRspTok0 = 0
2193 // bits[15:14] FreeTok[1:0] = 2
2194 // bits[17:16] ReqTok1 = 0
2195 // bits[19:18] PReqTok1 = 0
2196 // bits[21:20] RspTok1 = 0
2197 // bits[23:22] ProbeTok1= 3
2198 // bits[24] IsocReqTok1 = 0
2199 // bits[25] IsocPreqTok1 = 0
2200 // bits[28] IsocRspTok1 = 0
2201 // bits[31:30] FreeTok[3:2] = 0
2202   {
2203     PciRegister,
2204     {
2205       AMD_FAMILY_10,                      // CpuFamily
2206       AMD_F10_ALL                         // CpuRevision
2207     },
2208     { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },  // platform Features
2209     {{
2210       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
2211       0x0500852A,                           // regData
2212       0xC000FFFF,                           // regMask
2213     }}
2214   },
2215   // F3x158 - Link to XCS Token Count Registers
2216   // bits [3:0]LnkToXcsDRToken = 0
2217   {
2218     PciRegister,
2219     {
2220       AMD_FAMILY_10,                      // CpuFamily
2221       AMD_F10_ALL                         // CpuRevision
2222     },
2223     { (AMD_PF_NFCM | AMD_PF_IFCM | AMD_PF_IOMMU) },
2224     {{
2225       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
2226       0x00000000,
2227       0x0000000F
2228     }}
2229   },
2230   // F3x158 - Link to XCS Token Count Registers
2231   // bits [3:0]LnkToXcsDRToken = 3
2232   {
2233     PciRegister,
2234     {
2235       AMD_FAMILY_10,                      // CpuFamily
2236       AMD_F10_ALL                         // CpuRevision
2237     },
2238     { (AMD_PF_UMA_IFCM | AMD_PF_UMA) },
2239     {{
2240       MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
2241       0x00000003,
2242       0x0000000F
2243     }}
2244   },
2245 };
2246
2247 CONST REGISTER_TABLE ROMDATA F10SingleLinkPciRegisterTable = {
2248   PrimaryCores,
2249   (sizeof (F10SingleLinkPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
2250   F10SingleLinkPciRegisters,
2251 };