src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10IoCstate.c

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * AMD Family_10 IO C-state feature support functions.
   6  *
   7  * Provides the functions necessary to initialize the IO C-state feature.
   8  *
   9  * @xrefitem bom "File Content Label" "Release Content"
  10  * @e project:      AGESA
  11  * @e sub-project:  CPU/F10
  12  * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
  13  *
  14  */
  15 /*
  16  ******************************************************************************
  17  *
  18  * Copyright (C) 2012 Advanced Micro Devices, Inc.
  19  * All rights reserved.
  20  *
  21  * Redistribution and use in source and binary forms, with or without
  22  * modification, are permitted provided that the following conditions are met:
  23  *     * Redistributions of source code must retain the above copyright
  24  *       notice, this list of conditions and the following disclaimer.
  25  *     * Redistributions in binary form must reproduce the above copyright
  26  *       notice, this list of conditions and the following disclaimer in the
  27  *       documentation and/or other materials provided with the distribution.
  28  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  29  *       its contributors may be used to endorse or promote products derived
  30  *       from this software without specific prior written permission.
  31  *
  32  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  36  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  39  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42  *
  43  ******************************************************************************
  44  */
  45 /*----------------------------------------------------------------------------------------
  46  *                             M O D U L E S    U S E D
  47  *----------------------------------------------------------------------------------------
  48  */
  49
  50 #include "AGESA.h"
  51 #include "amdlib.h"
  52 #include "Ids.h"
  53 #include "cpuFeatures.h"
  54 #include "cpuIoCstate.h"
  55 #include "cpuF10PowerMgmt.h"
  56 #include "cpuLateInit.h"
  57 #include "cpuRegisters.h"
  58 #include "cpuServices.h"
  59 #include "cpuApicUtilities.h"
  60 #include "cpuFamilyTranslation.h"
  61 #include "CommonReturns.h"
  62 #include "Filecode.h"
  63 CODE_GROUP (G1_PEICC)
  64 RDATA_GROUP (G2_PEI)
  65 #define FILECODE PROC_CPU_FAMILY_0X10_F10IOCSTATE_FILECODE
  66
  67 /*----------------------------------------------------------------------------------------
  68  *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
  69  *----------------------------------------------------------------------------------------
  70  */
  71 VOID
  72 STATIC
  73 F10InitializeIoCstateOnCore (
  74   IN       VOID *CstateBaseMsr,
  75   IN       AMD_CONFIG_PARAMS *StdHeader
  76   );
  77
  78 BOOLEAN
  79 F10IsIoCstateFeatureSupported (
  80   IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
  81   IN       UINT32                    Socket,
  82   IN       AMD_CONFIG_PARAMS         *StdHeader
  83   );
  84
  85 /*----------------------------------------------------------------------------------------
  86  *                   D E F I N I T I O N S    A N D    M A C R O S
  87  *----------------------------------------------------------------------------------------
  88  */
  89 extern CPU_FAMILY_SUPPORT_TABLE            IoCstateFamilyServiceTable;
  90
  91 /*----------------------------------------------------------------------------------------
  92  *                          E X P O R T E D    F U N C T I O N S
  93  *----------------------------------------------------------------------------------------
  94  */
  95
  96 /*---------------------------------------------------------------------------------------*/
  97 /**
  98  *  Enable IO Cstate on a family 10h CPU.
  99  *
 100  * @param[in]    IoCstateServices   Pointer to this CPU's IO Cstate family services.
 101  * @param[in]    EntryPoint         Timepoint designator.
 102  * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
 103  * @param[in]    StdHeader          Config Handle for library, services.
 104  *
 105  * @return       AGESA_SUCCESS      Always succeeds.
 106  *
 107  */
 108 AGESA_STATUS
 109 STATIC
 110 F10InitializeIoCstate (
 111   IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
 112   IN       UINT64                    EntryPoint,
 113   IN       PLATFORM_CONFIGURATION    *PlatformConfig,
 114   IN       AMD_CONFIG_PARAMS         *StdHeader
 115   )
 116 {
 117   UINT64   LocalMsrRegister;
 118   AP_TASK  TaskPtr;
 119
 120   if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
 121     // Initialize MSRC001_0073[CstateAddr] on each core to a region of
 122     // the IO address map with 8 consecutive available addresses.
 123     LocalMsrRegister = 0;
 124
 125     ((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
 126
 127     TaskPtr.FuncAddress.PfApTaskI = F10InitializeIoCstateOnCore;
 128     TaskPtr.DataTransfer.DataSizeInDwords = 2;
 129     TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister;
 130     TaskPtr.DataTransfer.DataTransferFlags = 0;
 131     TaskPtr.ExeFlags = WAIT_FOR_CORE;
 132     ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
 133   }
 134   return AGESA_SUCCESS;
 135 }
 136
 137 /*---------------------------------------------------------------------------------------*/
 138 /**
 139  *  Enable CState on a family 10h core.
 140  *
 141  * @param[in]    CstateBaseMsr      MSR value to write to C001_0073 as determined by core 0.
 142  * @param[in]    StdHeader          Config Handle for library, services.
 143  *
 144  */
 145 VOID
 146 STATIC
 147 F10InitializeIoCstateOnCore (
 148   IN       VOID *CstateBaseMsr,
 149   IN       AMD_CONFIG_PARAMS *StdHeader
 150   )
 151 {
 152   // Initialize MSRC001_0073[CstateAddr] on each core
 153   LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
 154 }
 155
 156 /*---------------------------------------------------------------------------------------*/
 157 /**
 158  *  Returns the size of CST object
 159  *
 160  * @param[in]    IoCstateServices   IO Cstate services.
 161  * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data
 162  * @param[in]    StdHeader          Config Handle for library, services.
 163  *
 164  * @retval       CstObjSize         Size of CST Object
 165  *
 166  */
 167 UINT32
 168 STATIC
 169 F10GetAcpiCstObj (
 170   IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
 171   IN       PLATFORM_CONFIGURATION    *PlatformConfig,
 172   IN       AMD_CONFIG_PARAMS         *StdHeader
 173   )
 174 {
 175   return (CST_HEADER_SIZE + CST_BODY_SIZE);
 176 }
 177
 178 /*---------------------------------------------------------------------------------------*/
 179 /**
 180  *  Routine to generate the C-State ACPI objects
 181  *
 182  * @param[in]      IoCstateServices       IO Cstate services.
 183  * @param[in]      LocalApicId            Local Apic Id for each core.
 184  * @param[in, out] **PstateAcpiBufferPtr  Pointer to the Acpi Buffer Pointer.
 185  * @param[in]      StdHeader              Config Handle for library, services.
 186  *
 187  */
 188 VOID
 189 STATIC
 190 F10CreateAcpiCstObj (
 191   IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
 192   IN       UINT8                     LocalApicId,
 193   IN OUT   VOID                      **PstateAcpiBufferPtr,
 194   IN       AMD_CONFIG_PARAMS         *StdHeader
 195   )
 196 {
 197   UINT64            MsrData;
 198   CST_HEADER_STRUCT *CstHeaderPtr;
 199   CST_BODY_STRUCT   *CstBodyPtr;
 200
 201   // Read from MSR C0010073 to obtain CstateAddr
 202   LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader);
 203   ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr != 0) &&
 204           (((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr <= 0xFFF8));
 205
 206   // Typecast the pointer
 207   CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr;
 208
 209   // Set CST Header
 210   CstHeaderPtr->NameOpcode  = NAME_OPCODE;
 211   CstHeaderPtr->CstName_a__ = CST_NAME__;
 212   CstHeaderPtr->CstName_a_C = CST_NAME_C;
 213   CstHeaderPtr->CstName_a_S = CST_NAME_S;
 214   CstHeaderPtr->CstName_a_T = CST_NAME_T;
 215
 216   // Typecast the pointer
 217   CstHeaderPtr++;
 218   CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr;
 219
 220   // Set CST Body
 221   CstBodyPtr->PkgOpcode      = PACKAGE_OPCODE;
 222   CstBodyPtr->PkgLength      = CST_LENGTH;
 223   CstBodyPtr->PkgElements    = CST_NUM_OF_ELEMENTS;
 224   CstBodyPtr->BytePrefix     = BYTE_PREFIX_OPCODE;
 225   CstBodyPtr->Count          = CST_COUNT;
 226   CstBodyPtr->PkgOpcode2     = PACKAGE_OPCODE;
 227   CstBodyPtr->PkgLength2     = CST_PKG_LENGTH;
 228   CstBodyPtr->PkgElements2   = CST_PKG_ELEMENTS;
 229   CstBodyPtr->BufferOpcode   = BUFFER_OPCODE;
 230   CstBodyPtr->BufferLength   = CST_SUBPKG_LENGTH;
 231   CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS;
 232   CstBodyPtr->BufferOpcode2  = BUFFER_OPCODE;
 233   CstBodyPtr->GdrOpcode      = GENERIC_REG_DESCRIPTION;
 234   CstBodyPtr->GdrLength      = CST_GDR_LENGTH;
 235   CstBodyPtr->AddrSpaceId    = GDR_ASI_SYSTEM_IO;
 236   CstBodyPtr->RegBitWidth    = 0x08;
 237   CstBodyPtr->RegBitOffset   = 0x00;
 238   CstBodyPtr->AddressSize    = GDR_ASZ_BYTE_ACCESS;
 239   CstBodyPtr->RegisterAddr   = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr;
 240   CstBodyPtr->EndTag         = 0x0079;
 241   CstBodyPtr->BytePrefix2    = BYTE_PREFIX_OPCODE;
 242   CstBodyPtr->Type           = CST_C2_TYPE;
 243   CstBodyPtr->WordPrefix     = WORD_PREFIX_OPCODE;
 244   CstBodyPtr->Latency        = 0x4B;
 245   CstBodyPtr->DWordPrefix    = DWORD_PREFIX_OPCODE;
 246   CstBodyPtr->Power          = 0;
 247
 248   CstBodyPtr++;
 249
 250   //Update the pointer
 251   *PstateAcpiBufferPtr = CstBodyPtr;
 252 }
 253
 254 /*---------------------------------------------------------------------------------------*/
 255 /**
 256  * Routine to check whether IO Cstate should be supported.
 257  *
 258  * @param[in]      IoCstateServices      IO Cstate services.
 259  * @param[in]      Socket                Zero-based socket number.
 260  * @param[in]      StdHeader             Config Handle for library, services.
 261  *
 262  * @retval         TRUE                  Support IO Cstate.
 263  * @retval         FALSE                 Do not support IO Cstate.
 264  *
 265  */
 266 BOOLEAN
 267 F10IsIoCstateFeatureSupported (
 268   IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
 269   IN       UINT32                    Socket,
 270   IN       AMD_CONFIG_PARAMS         *StdHeader
 271   )
 272 {
 273   UINT64 LocalMsrRegister;
 274   CPUID_DATA     CpuId;
 275   CPU_LOGICAL_ID LogicalId;
 276
 277   GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
 278   // Only Rev.E processor with CPB enabled and ucode 010000BF or later loaded
 279   // MSR_C001_0073 can be programmed
 280   if ((LogicalId.Revision & AMD_F10_Ex) != 0) {
 281     LibAmdCpuidRead (AMD_CPUID_APM, &CpuId, StdHeader);
 282     if (((CpuId.EDX_Reg & 0x00000200) >> 9) == 1) {
 283       LibAmdMsrRead (MSR_PATCH_LEVEL, &LocalMsrRegister, StdHeader);
 284       if ((LocalMsrRegister & 0xffffffff) >= 0x010000BF) {
 285         return TRUE;
 286       }
 287     }
 288   }
 289   return FALSE;
 290 }
 291
 292 CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport =
 293 {
 294   0,
 295   F10IsIoCstateFeatureSupported,
 296   F10InitializeIoCstate,
 297   F10GetAcpiCstObj,
 298   F10CreateAcpiCstObj,
 299   (PF_IO_CSTATE_IS_CSD_GENERATED) CommonReturnFalse
 300 };