1 ; ****************************************************************************
5 ; * AMD Platform Specific Memory Configuration
7 ; * Contains AMD AGESA Memory Configuration Override Interface
9 ; * @xrefitem bom "File Content Label" "Release Content"
11 ; * @e sub-project: Include
12 ; * @e \$Revision: 22910 $ @e \$Date: 2009-11-27 04:50:20 -0600 (Fri, 27 Nov 2009) $
14 ; ****************************************************************************
16 ; * Copyright (C) 2012 Advanced Micro Devices, Inc.
17 ; * All rights reserved.
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20 ; * modification, are permitted provided that the following conditions are met:
21 ; * * Redistributions of source code must retain the above copyright
22 ; * notice, this list of conditions and the following disclaimer.
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24 ; * notice, this list of conditions and the following disclaimer in the
25 ; * documentation and/or other materials provided with the distribution.
26 ; * * Neither the name of Advanced Micro Devices, Inc. nor the names of
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30 ; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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34 ; * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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39 ; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 ; **************************************************************************
44 PSO_ENTRY TEXTEQU <UINT8>; < Platform Configuration Table Entry
46 ; *****************************************************************************************
48 ; * PLATFORM SPECIFIC MEMORY DEFINITIONS
50 ; *****************************************************************************************
53 ; < Memory Speed and DIMM Population Masks
57 ANY_SPEED EQU 0FFFFFFFFh
58 DDR400 EQU ( 1 SHL (DDR400_FREQUENCY / 66))
59 DDR533 EQU ( 1 SHL (DDR533_FREQUENCY / 66))
60 DDR667 EQU ( 1 SHL (DDR667_FREQUENCY / 66))
61 DDR800 EQU ( 1 SHL (DDR800_FREQUENCY / 66))
62 DDR1066 EQU ( 1 SHL (DDR1066_FREQUENCY / 66))
63 DDR1333 EQU ( 1 SHL (DDR1333_FREQUENCY / 66))
64 DDR1600 EQU ( 1 SHL (DDR1600_FREQUENCY / 66))
65 DDR1866 EQU ( 1 SHL (DDR1866_FREQUENCY / 66))
66 DDR2133 EQU ( 1 SHL (DDR2133_FREQUENCY / 66))
67 DDR2400 EQU ( 1 SHL (DDR2400_FREQUENCY / 66))
69 ; < DIMM POPULATION MASKS
93 ; < CS POPULATION MASKS
124 ; *****************************************************************************************
126 ; * Platform Specific Override Definitions for Socket, Channel and Dimm
127 ; * This indicates where a platform override will be applied.
129 ; *****************************************************************************************
159 ; REGISTER ACCESS MASKS
167 ACCESS_DCT_XT EQU 06h
168 ; *****************************************************************************************
170 ; * Platform Specific Overriding Table Definitions
172 ; *****************************************************************************************
173 PSO_END EQU 0 ; < Table End
174 PSO_CKE_TRI EQU 1 ; < CKE Tristate Map
175 PSO_ODT_TRI EQU 2 ; < ODT Tristate Map
176 PSO_CS_TRI EQU 3 ; < CS Tristate Map
177 PSO_MAX_DIMMS EQU 4 ; < Max Dimms per channel
178 PSO_CLK_SPEED EQU 5 ; < Clock Speed
179 PSO_DIMM_TYPE EQU 6 ; < Dimm Type
180 PSO_MEMCLK_DIS EQU 7 ; < MEMCLK Disable Map
181 PSO_MAX_CHNLS EQU 8 ; < Max Channels per Socket
182 PSO_BUS_SPEED EQU 9 ; < Max Memory Bus Speed
183 PSO_MAX_CHIPSELS EQU 10 ; < Max Chipsel per Channel
184 PSO_MEM_TECH EQU 11 ; < Channel Memory Type
185 PSO_WL_SEED EQU 12 ; < DDR3 Write Levelization Seed delay
186 PSO_RXEN_SEED EQU 13 ; < Hardwared based RxEn seed
187 PSO_NO_LRDIMM_CS67_ROUTING EQU 14 ; < CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
188 PSO_SOLDERED_DOWN_SODIMM_TYPE EQU 15 ; < Soldered down SODIMM type
189 PSO_LVDIMM_VOLT1_5_SUPPORT EQU 16 ; < Force LvDimm voltage to 1.5V
190 PSO_MIN_RD_WR_DATAEYE_WIDTH EQU 17 ; < Min RD/WR dataeye width
191 PSO_CPU_FAMILY_TO_OVERRIDE EQU 18 ; < CPU family signature to tell following PSO macros are CPU family dependent
192 ; **********************************
193 ; * CONDITIONAL PSO SPECIFIC ENTRIES
194 ; **********************************
196 CONDITIONAL_PSO_MIN EQU 100 ; < Start of Conditional Entry Types
197 PSO_CONDITION_AND EQU 100 ; < And Block - Start of Conditional block
198 PSO_CONDITION_LOC EQU 101 ; < Location - Specify Socket, Channel, Dimms to be affected
199 PSO_CONDITION_SPD EQU 102 ; < SPD - Specify a specific SPD value on a Dimm on the channel
200 PSO_CONDITION_REG EQU 103 ; Reserved
201 PSO_CONDITION_MAX EQU 103 ; < End Of Condition Entry Types
203 PSO_ACTION_MIN EQU 120 ; < Start of Action Entry Types
204 PSO_ACTION_ODT EQU 120 ; < ODT values to override
205 PSO_ACTION_ADDRTMG EQU 121 ; < Address/Timing values to override
206 PSO_ACTION_ODCCONTROL EQU 122 ; < ODC Control values to override
207 PSO_ACTION_SLEWRATE EQU 123 ; < Slew Rate value to override
208 PSO_ACTION_REG EQU 124 ; Reserved
209 PSO_ACTION_SPEEDLIMIT EQU 125 ; < Memory Bus speed Limit based on configuration
210 PSO_ACTION_MAX EQU 125 ; < End of Action Entry Types
211 CONDITIONAL_PSO_MAX EQU 139 ; < End of Conditional Entry Types
212 ; **********************************
213 ; * TABLE DRIVEN PSO SPECIFIC ENTRIES
214 ; **********************************
215 ; Condition descriptor
216 PSO_TBLDRV_CONFIG EQU 200 ; < Configuration Descriptor
218 ; Overriding entry types
219 PSO_TBLDRV_START EQU 210 ; < Start of Table Driven Overriding Entry Types
220 PSO_TBLDRV_SPEEDLIMIT EQU 210 ; < Speed Limit
221 PSO_TBLDRV_ODT_RTTNOM EQU 211 ; < RttNom
222 PSO_TBLDRV_ODT_RTTWR EQU 212 ; < RttWr
223 PSO_TBLDRV_ODTPATTERN EQU 213 ; < Odt Patterns
224 PSO_TBLDRV_ADDRTMG EQU 214 ; < Address/Timing values
225 PSO_TBLDRV_ODCCTRL EQU 215 ; < ODC Control values
226 PSO_TBLDRV_SLOWACCMODE EQU 216 ; < Slow Access Mode
227 PSO_TBLDRV_MR0_CL EQU 217 ; < MR0[CL]
228 PSO_TBLDRV_MR0_WR EQU 218 ; < MR0[WR]
229 PSO_TBLDRV_RC2_IBT EQU 219 ; < RC2[IBT]
230 PSO_TBLDRV_RC10_OPSPEED EQU 220 ; < RC10[Opearting Speed]
231 PSO_TBLDRV_LRDIMM_IBT EQU 221 ; < LrDIMM IBT
232 PSO_TBLDRV____TRAINING EQU 222 ; < training
233 PSO_TBLDRV_INVALID_TYPE EQU 223 ; < Invalid Type
234 PSO_TBLDRV_END EQU 223 ; < End of Table Driven Overriding Entry Types
237 ; *****************************************************************************************
239 ; * CONDITIONAL OVERRIDE TABLE MACROS
241 ; *****************************************************************************************
242 CPU_FAMILY_TO_OVERRIDE MACRO CpuFamilyRevision:REQ
243 DB PSO_CPU_FAMILY_TO_OVERRIDE
248 MEMCLK_DIS_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
264 CKE_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ
274 ODT_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ
286 CS_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
302 NUMBER_OF_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ
308 DB NumberOfDimmSlotsPerChannel
311 NUMBER_OF_CHIP_SELECTS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ
317 DB NumberOfChipSelectsPerChannel
320 NUMBER_OF_CHANNELS_SUPPORTED MACRO SocketID:REQ, NumberOfChannelsPerSocket:REQ
326 DB NumberOfChannelsPerSocket
329 OVERRIDE_DDR_BUS_SPEED MACRO SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ
339 DRAM_TECHNOLOGY MACRO SocketID:REQ, MemTechType:REQ
348 WRITE_LEVELING_SEED MACRO SocketID:REQ, ChannelID:REQ, DimmID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
349 Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
366 HW_RXEN_SEED MACRO SocketID:REQ, ChannelID:REQ, DimmID: REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
367 Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
384 NO_LRDIMM_CS67_ROUTING MACRO SocketID:REQ, ChannelID:REQ
385 DB PSO_NO_LRDIMM_CS67_ROUTING
393 SOLDERED_DOWN_SODIMM_TYPE MACRO SocketID:REQ, ChannelID:REQ
394 DB PSO_SOLDERED_DOWN_SODIMM_TYPE
402 LVDIMM_FORCE_VOLT1_5_FOR_D0 MACRO
403 DB PSO_LVDIMM_VOLT1_5_SUPPORT
411 MIN_RD_WR_DATAEYE_WIDTH MACRO SocketID:REQ, ChannelID:REQ, MinRdDataeyeWidth:REQ, MinWrDataeyeWidth:REQ
412 DB PSO_MIN_RD_WR_DATAEYE_WIDTH
421 ; *****************************************************************************************
423 ; * CONDITIONAL OVERRIDE TABLE MACROS
425 ; *****************************************************************************************
431 COND_LOC MACRO SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ
439 COND_SPD MACRO Byte:REQ, Mask:REQ, Value:REQ
447 COND_REG MACRO Access:REQ, Offset:REQ, Mask:REQ, Value:REQ
456 ACTION_ODT MACRO Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ
467 ACTION_ADDRTMG MACRO Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ
468 DB PSO_ACTION_ADDRTMG
475 ACTION_ODCCTRL MACRO Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ
476 DB PSO_ACTION_ODCCONTROL
483 ACTION_SLEWRATE MACRO Frequency:REQ, DimmConfig:REQ, SlewRate:REQ
484 DB PSO_ACTION_SLEWRATE
491 ACTION_SPEEDLIMIT MACRO DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ
492 DB PSO_ACTION_SPEEDLIMIT
501 ; *****************************************************************************************
503 ; * END OF CONDITIONAL OVERRIDE TABLE MACROS
505 ; *****************************************************************************************
506 ; *****************************************************************************************
508 ; * TABLE DRIVEN OVERRIDE MACROS
510 ; *****************************************************************************************
511 ; Configuration sub-descriptors
513 CONFIG_SPEEDLIMIT EQU 1
515 CONFIG_DONT_CARE EQU 3
516 Config_Type TEXTEQU <DWORD>
518 ; Configuration Macros
520 TBLDRV_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ
530 TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Dimms:REQ, NumOfSR:REQ, NumOfDR:REQ, NumOfQR:REQ, NumOfLRDimm:REQ
542 TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ, NumOfReg:REQ
555 TBLDRV_CONFIG_ENTRY_SPEEDLIMIT MACRO SpeedLimit1_5:REQ, SpeedLimit1_35:REQ, SpeedLimit1_25:REQ
556 DB PSO_TBLDRV_SPEEDLIMIT
563 TBLDRV_CONFIG_ENTRY_ODT_RTTNOM MACRO TgtCS:REQ, RttNom:REQ
564 DB PSO_TBLDRV_ODT_RTTNOM
570 TBLDRV_CONFIG_ENTRY_ODT_RTTWR MACRO TgtCS:REQ, RttWr:REQ
571 DB PSO_TBLDRV_ODT_RTTWR
577 TBLDRV_CONFIG_ENTRY_ODTPATTERN MACRO RdODTCSHigh:REQ, RdODTCSLow:REQ, WrODTCSHigh:REQ, WrODTCSLow:REQ
578 DB PSO_TBLDRV_ODTPATTERN
586 TBLDRV_CONFIG_ENTRY_ADDRTMG MACRO AddrTmg:REQ
587 DB PSO_TBLDRV_ADDRTMG
592 TBLDRV_CONFIG_ENTRY_ODCCTRL MACRO OdcCtrl:REQ
593 DB PSO_TBLDRV_ODCCTRL
598 TBLDRV_CONFIG_ENTRY_SLOWACCMODE MACRO SlowAccMode:REQ
599 DB PSO_TBLDRV_SLOWACCMODE
604 TBLDRV_CONFIG_ENTRY_RC2_IBT MACRO TgtDimm:REQ, IBT:REQ
605 DB PSO_TBLDRV_RC2_IBT
611 TBLDRV_OVERRIDE_MR0_CL MACRO RegValOfTcl:REQ, MR0CL13:REQ, MR0CL0:REQ
622 TBLDRV_OVERRIDE_MR0_WR MACRO RegValOfTwr:REQ, MR0WR:REQ
632 TBLDRV_OVERRIDE_RC10_OPSPEED MACRO Frequency:REQ, MR10OPSPEED:REQ
636 DB PSO_TBLDRV_RC10_OPSPEED
642 TBLDRV_CONFIG_ENTRY_LRDMM_IBT MACRO F0RC8:REQ, F1RC0:REQ, F1RC1:REQ, F1RC2:REQ
643 DB PSO_TBLDRV_LRDIMM_IBT
651 TBLDRV_CONFIG_ENTRY____TRAINING MACRO Training__Mode:REQ
652 DB PSO_TBLDRV____TRAINING
658 ; Macros for removing entries
660 INVALID_CONFIG_FLAG EQU 8000h
662 TBLDRV_INVALID_CONFIG MACRO
663 DB PSO_TBLDRV_INVALID_TYPE
666 ; *****************************************************************************************
668 ; * END OF TABLE DRIVEN OVERRIDE MACROS
670 ; *****************************************************************************************