src/vendorcode/amd/agesa/f15/Include/OptionFamily10hInstall.h

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * Install of family 10h support
   6  *
   7  * This file generates the defaults tables for family 10h processors.
   8  *
   9  * @xrefitem bom "File Content Label" "Release Content"
  10  * @e project:      AGESA
  11  * @e sub-project:  Core
  12  * @e \$Revision: 60726 $   @e \$Date: 2011-10-20 17:08:02 -0600 (Thu, 20 Oct 2011) $
  13  */
  14 /*****************************************************************************
  15  *
  16  * Copyright (C) 2012 Advanced Micro Devices, Inc.
  17  * All rights reserved.
  18  *
  19  * Redistribution and use in source and binary forms, with or without
  20  * modification, are permitted provided that the following conditions are met:
  21  *     * Redistributions of source code must retain the above copyright
  22  *       notice, this list of conditions and the following disclaimer.
  23  *     * Redistributions in binary form must reproduce the above copyright
  24  *       notice, this list of conditions and the following disclaimer in the
  25  *       documentation and/or other materials provided with the distribution.
  26  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  27  *       its contributors may be used to endorse or promote products derived
  28  *       from this software without specific prior written permission.
  29  *
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  31  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  32  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  33  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  34  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  35  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  36  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  37  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  39  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  *
  42  ***************************************************************************/
  43
  44 #ifndef _OPTION_FAMILY_10H_INSTALL_H_
  45 #define _OPTION_FAMILY_10H_INSTALL_H_
  46
  47 /*
  48  * Common Family 10h routines
  49  */
  50 extern F_CPU_DISABLE_PSTATE F10DisablePstate;
  51 extern F_CPU_TRANSITION_PSTATE F10TransitionPstate;
  52 extern F_CPU_GET_TSC_RATE F10GetTscRate;
  53 extern F_CPU_GET_NB_FREQ F10GetCurrentNbFrequency;
  54 extern F_CPU_AP_INITIAL_LAUNCH F10LaunchApCore;
  55 extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F10GetApMailboxFromHardware;
  56 extern F_CPU_SET_AP_CORE_NUMBER F10SetApCoreNumber;
  57 extern F_CPU_GET_AP_CORE_NUMBER F10GetApCoreNumber;
  58 extern F_CPU_TRANSFER_AP_CORE_NUMBER F10TransferApCoreNumber;
  59 extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F10CpuAmdCoreIdPositionInInitialApicId;
  60 extern F_CPU_SAVE_FEATURES F10SaveFeatures;
  61 extern F_CPU_WRITE_FEATURES F10WriteFeatures;
  62 extern F_CPU_SET_WARM_RESET_FLAG F10SetAgesaWarmResetFlag;
  63 extern F_CPU_GET_WARM_RESET_FLAG F10GetAgesaWarmResetFlag;
  64 extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BrandIdString1;
  65 extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BrandIdString2;
  66 extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10CacheInfo;
  67 extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10SysPmTable;
  68 extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10WheaInitData;
  69 extern F_CPU_SET_CFOH_REG SetF10CacheFlushOnHaltRegister;
  70 extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F10GetPlatformTypeSpecificInfo;
  71 extern F_NEXT_LINK_HAS_HTFPY_FEATS F10NextLinkHasHtPhyFeats;
  72 extern F_SET_HT_PHY_REGISTER F10SetHtPhyRegister;
  73 extern F_GET_NEXT_HT_LINK_FEATURES F10GetNextHtLinkFeatures;
  74 extern CONST REGISTER_TABLE ROMDATA F10PciRegisterTable;
  75 extern CONST REGISTER_TABLE ROMDATA F10MsrRegisterTable;
  76 extern CONST REGISTER_TABLE ROMDATA F10HtPhyRegisterTable;
  77 extern CONST REGISTER_TABLE ROMDATA F10MultiLinkPciRegisterTable;
  78 extern CONST REGISTER_TABLE ROMDATA F10SingleLinkPciRegisterTable;
  79 extern CONST REGISTER_TABLE ROMDATA F10WorkaroundsTable;
  80 extern F_GET_EARLY_INIT_TABLE GetF10EarlyInitOnCoreTable;
  81
  82
  83 /*
  84  * Install family 10h model 5 support
  85  */
  86 #ifdef OPTION_FAMILY10H_BL
  87   #if OPTION_FAMILY10H_BL == TRUE
  88     extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
  89     extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
  90     extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
  91     extern CONST REGISTER_TABLE ROMDATA F10BlPciRegisterTable;
  92     extern CONST REGISTER_TABLE ROMDATA F10BlMsrRegisterTable;
  93     extern CONST REGISTER_TABLE ROMDATA F10BlHtPhyRegisterTable;
  94     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BlMicroCodePatchesStruct;
  95     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BlMicrocodeEquivalenceTable;
  96     extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
  97     extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo;
  98     extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevCGetMinMaxNbFrequency;
  99     extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
 100     extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
 101     extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevCGetNumberOfPhysicalCores;
 102
 103     #if USES_REGISTER_TABLES == TRUE
 104       CONST REGISTER_TABLE ROMDATA *F10BlRegisterTables[] =
 105       {
 106         #if BASE_FAMILY_PCI == TRUE
 107           &F10PciRegisterTable,
 108         #endif
 109         #if MODEL_SPECIFIC_PCI == TRUE
 110           &F10SingleLinkPciRegisterTable,
 111         #endif
 112         #if MODEL_SPECIFIC_PCI == TRUE
 113           &F10RevCPciRegisterTable,
 114         #endif
 115         #if MODEL_SPECIFIC_PCI == TRUE
 116           &F10BlPciRegisterTable,
 117         #endif
 118         #if BASE_FAMILY_MSR == TRUE
 119           &F10MsrRegisterTable,
 120         #endif
 121         #if MODEL_SPECIFIC_MSR == TRUE
 122           &F10RevCMsrRegisterTable,
 123         #endif
 124         #if MODEL_SPECIFIC_MSR == TRUE
 125           &F10BlMsrRegisterTable,
 126         #endif
 127         #if MODEL_SPECIFIC_HT_PCI == TRUE
 128           &F10HtPhyRegisterTable,
 129         #endif
 130         #if MODEL_SPECIFIC_HT_PCI == TRUE
 131           &F10RevCHtPhyRegisterTable,
 132         #endif
 133         #if MODEL_SPECIFIC_HT_PCI == TRUE
 134           &F10BlHtPhyRegisterTable,
 135         #endif
 136         #if BASE_FAMILY_WORKAROUNDS == TRUE
 137           &F10WorkaroundsTable,
 138         #endif
 139         // the end.
 140         NULL
 141       };
 142     #endif
 143
 144     #if USES_REGISTER_TABLES == TRUE
 145       CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10BlTableEntryTypeDescriptors[] =
 146       {
 147         {MsrRegister, SetRegisterForMsrEntry},
 148         {PciRegister, SetRegisterForPciEntry},
 149         {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
 150         {HtPhyRegister, SetRegisterForHtPhyEntry},
 151         {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
 152         {DeemphasisRegister, SetRegisterForDeemphasisEntry},
 153         {ProfileFixup, SetRegisterForPerformanceProfileEntry},
 154         {HtHostPciRegister, SetRegisterForHtHostEntry},
 155         {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
 156         {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
 157         {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
 158         {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
 159         {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
 160         // End
 161         {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
 162       };
 163     #endif
 164
 165     CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10BlServices =
 166     {
 167       0,
 168       #if DISABLE_PSTATE == TRUE
 169         F10DisablePstate,
 170       #else
 171         (PF_CPU_DISABLE_PSTATE) CommonAssert,
 172       #endif
 173       #if TRANSITION_PSTATE == TRUE
 174         F10TransitionPstate,
 175       #else
 176         (PF_CPU_TRANSITION_PSTATE) CommonAssert,
 177       #endif
 178       #if PROC_IDD_MAX == TRUE
 179         F10CommonRevCGetProcIddMax,
 180       #else
 181         (PF_CPU_GET_IDD_MAX) CommonAssert,
 182       #endif
 183       #if GET_TSC_RATE == TRUE
 184         F10GetTscRate,
 185       #else
 186         (PF_CPU_GET_TSC_RATE) CommonAssert,
 187       #endif
 188       #if GET_NB_FREQ == TRUE
 189         F10GetCurrentNbFrequency,
 190       #else
 191         (PF_CPU_GET_NB_FREQ) CommonAssert,
 192       #endif
 193       #if GET_NB_FREQ == TRUE
 194         F10RevCGetMinMaxNbFrequency,
 195       #else
 196         (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
 197       #endif
 198       #if GET_NB_FREQ == TRUE
 199         F10CommonRevCGetNbPstateInfo,
 200       #else
 201         (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
 202       #endif
 203       #if IS_NBCOF_INIT_NEEDED == TRUE
 204         F10CommonRevCGetNbCofVidUpdate,
 205       #else
 206         (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
 207       #endif
 208       #if GET_NB_IDD_MAX == TRUE
 209         (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
 210       #else
 211         (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
 212       #endif
 213       #if AP_INITIAL_LAUNCH == TRUE
 214         F10LaunchApCore,
 215       #else
 216         (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
 217       #endif
 218       #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
 219         F10CommonRevCGetNumberOfPhysicalCores,
 220       #else
 221         (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
 222       #endif
 223       #if GET_AP_MAILBOX_FROM_HW == TRUE
 224         F10GetApMailboxFromHardware,
 225       #else
 226         (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
 227       #endif
 228       #if SET_AP_CORE_NUMBER == TRUE
 229         F10SetApCoreNumber,
 230       #else
 231         (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
 232       #endif
 233       #if GET_AP_CORE_NUMBER == TRUE
 234         F10GetApCoreNumber,
 235       #else
 236         (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
 237       #endif
 238       #if TRANSFER_AP_CORE_NUMBER == TRUE
 239         F10TransferApCoreNumber,
 240       #else
 241         (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
 242       #endif
 243       #if ID_POSITION_INITIAL_APICID == TRUE
 244         F10CpuAmdCoreIdPositionInInitialApicId,
 245       #else
 246         (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
 247       #endif
 248       #if SAVE_FEATURES == TRUE
 249         F10SaveFeatures,
 250       #else
 251         (PF_CPU_SAVE_FEATURES) CommonAssert,
 252       #endif
 253       #if WRITE_FEATURES == TRUE
 254         F10WriteFeatures,
 255       #else
 256         (PF_CPU_WRITE_FEATURES) CommonAssert,
 257       #endif
 258       #if SET_WARM_RESET_FLAG == TRUE
 259         F10SetAgesaWarmResetFlag,
 260       #else
 261         (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
 262       #endif
 263       #if GET_WARM_RESET_FLAG == TRUE
 264         F10GetAgesaWarmResetFlag,
 265       #else
 266         (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
 267       #endif
 268       #if BRAND_STRING1 == TRUE
 269         GetF10BrandIdString1,
 270       #else
 271         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 272       #endif
 273       #if BRAND_STRING2 == TRUE
 274         GetF10BrandIdString2,
 275       #else
 276         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 277       #endif
 278       #if GET_PATCHES == TRUE
 279         GetF10BlMicroCodePatchesStruct,
 280       #else
 281         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 282       #endif
 283       #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
 284         GetF10BlMicrocodeEquivalenceTable,
 285       #else
 286         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 287       #endif
 288       #if GET_CACHE_INFO == TRUE
 289         GetF10CacheInfo,
 290       #else
 291         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 292       #endif
 293       #if GET_SYSTEM_PM_TABLE == TRUE
 294         GetF10SysPmTable,
 295       #else
 296         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 297       #endif
 298       #if GET_WHEA_INIT == TRUE
 299         GetF10WheaInitData,
 300       #else
 301         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 302       #endif
 303       #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
 304         F10GetPlatformTypeSpecificInfo,
 305       #else
 306         (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
 307       #endif
 308       #if IS_NB_PSTATE_ENABLED == TRUE
 309         F10CommonRevCIsNbPstateEnabled,
 310       #else
 311         (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
 312       #endif
 313       #if (BASE_FAMILY_HT_PCI == TRUE)
 314         F10NextLinkHasHtPhyFeats,
 315       #else
 316         (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
 317       #endif
 318       #if (BASE_FAMILY_HT_PCI == TRUE)
 319         F10SetHtPhyRegister,
 320       #else
 321         (PF_SET_HT_PHY_REGISTER) CommonAssert,
 322       #endif
 323       #if BASE_FAMILY_PCI == TRUE
 324         F10GetNextHtLinkFeatures,
 325       #else
 326         (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
 327       #endif
 328       #if USES_REGISTER_TABLES == TRUE
 329         (REGISTER_TABLE **) F10BlRegisterTables,
 330       #else
 331         NULL,
 332       #endif
 333       #if USES_REGISTER_TABLES == TRUE
 334         (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10BlTableEntryTypeDescriptors,
 335       #else
 336         NULL,
 337       #endif
 338       NULL,
 339       NULL,
 340       InitCacheDisabled,
 341       #if AGESA_ENTRY_INIT_EARLY == TRUE
 342         GetF10EarlyInitOnCoreTable
 343       #else
 344         (PF_GET_EARLY_INIT_TABLE) CommonVoid
 345       #endif
 346     };
 347
 348     #define BL_SOCKETS 1
 349     #define BL_MODULES 1
 350     #define BL_RECOVERY_SOCKETS 1
 351     #define BL_RECOVERY_MODULES 1
 352     extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10BlLogicalIdAndRev;
 353     #define OPT_F10_BL_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10BlLogicalIdAndRev,
 354     #ifndef ADVCFG_PLATFORM_SOCKETS
 355       #define ADVCFG_PLATFORM_SOCKETS BL_SOCKETS
 356     #else
 357       #if ADVCFG_PLATFORM_SOCKETS < BL_SOCKETS
 358         #undef ADVCFG_PLATFORM_SOCKETS
 359         #define ADVCFG_PLATFORM_SOCKETS BL_SOCKETS
 360       #endif
 361     #endif
 362     #ifndef ADVCFG_PLATFORM_MODULES
 363       #define ADVCFG_PLATFORM_MODULES BL_MODULES
 364     #else
 365       #if ADVCFG_PLATFORM_MODULES < BL_MODULES
 366         #undef ADVCFG_PLATFORM_MODULES
 367         #define ADVCFG_PLATFORM_MODULES BL_MODULES
 368       #endif
 369     #endif
 370
 371     #if GET_PATCHES == TRUE
 372       #define F10_BL_UCODE_C6
 373       #define F10_BL_UCODE_C8
 374
 375       // If a patch is required for recovery mode to function properly, add a
 376       // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
 377       #if AGESA_ENTRY_INIT_EARLY == TRUE
 378         #if OPTION_AM3_SOCKET_SUPPORT == TRUE
 379           extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c6;
 380           #undef F10_BL_UCODE_C6
 381           #define F10_BL_UCODE_C6 &CpuF10MicrocodePatch010000c6,
 382         #endif
 383         #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE) || (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
 384           extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8;
 385           #undef F10_BL_UCODE_C8
 386           #define F10_BL_UCODE_C8 &CpuF10MicrocodePatch010000c8,
 387         #endif
 388       #endif
 389
 390       CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[] =
 391       {
 392         F10_BL_UCODE_C6
 393         F10_BL_UCODE_C8
 394         NULL
 395       };
 396
 397       CONST UINT8 ROMDATA CpuF10BlNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10BlMicroCodePatchArray) / sizeof (CpuF10BlMicroCodePatchArray[0])) - 1);
 398     #endif
 399
 400     #define OPT_F10_BL_CPU {AMD_FAMILY_10_BL, &cpuF10BlServices},
 401   #else
 402     #define OPT_F10_BL_CPU
 403     #define OPT_F10_BL_ID
 404   #endif
 405 #else
 406   #define OPT_F10_BL_CPU
 407   #define OPT_F10_BL_ID
 408 #endif
 409
 410 /*
 411  * Install family 10h model 6 support
 412  */
 413 #ifdef OPTION_FAMILY10H_DA
 414   #if OPTION_FAMILY10H_DA == TRUE
 415     extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
 416     extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
 417     extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
 418     extern CONST REGISTER_TABLE ROMDATA F10DaPciRegisterTable;
 419     extern CONST REGISTER_TABLE ROMDATA F10DaMsrRegisterTable;
 420     extern CONST REGISTER_TABLE ROMDATA F10DaHtPhyRegisterTable;
 421     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10DaMicroCodePatchesStruct;
 422     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10DaMicrocodeEquivalenceTable;
 423     extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
 424     extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo;
 425     extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevCGetMinMaxNbFrequency;
 426     extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
 427     extern F_CPU_SET_CFOH_REG SetF10DaCacheFlushOnHaltRegister;
 428     extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
 429     extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevCGetNumberOfPhysicalCores;
 430
 431     #if USES_REGISTER_TABLES == TRUE
 432       CONST REGISTER_TABLE ROMDATA *F10DaRegisterTables[] =
 433       {
 434         #if BASE_FAMILY_PCI == TRUE
 435           &F10PciRegisterTable,
 436         #endif
 437         #if MODEL_SPECIFIC_PCI == TRUE
 438           &F10SingleLinkPciRegisterTable,
 439         #endif
 440         #if MODEL_SPECIFIC_PCI == TRUE
 441           &F10RevCPciRegisterTable,
 442         #endif
 443         #if MODEL_SPECIFIC_PCI == TRUE
 444           &F10DaPciRegisterTable,
 445         #endif
 446         #if BASE_FAMILY_MSR == TRUE
 447           &F10MsrRegisterTable,
 448         #endif
 449         #if MODEL_SPECIFIC_MSR == TRUE
 450           &F10RevCMsrRegisterTable,
 451         #endif
 452         #if MODEL_SPECIFIC_MSR == TRUE
 453           &F10DaMsrRegisterTable,
 454         #endif
 455         #if MODEL_SPECIFIC_HT_PCI == TRUE
 456           &F10HtPhyRegisterTable,
 457         #endif
 458         #if MODEL_SPECIFIC_HT_PCI == TRUE
 459           &F10RevCHtPhyRegisterTable,
 460         #endif
 461         #if MODEL_SPECIFIC_HT_PCI == TRUE
 462           &F10DaHtPhyRegisterTable,
 463         #endif
 464         #if BASE_FAMILY_WORKAROUNDS == TRUE
 465           &F10WorkaroundsTable,
 466         #endif
 467         // the end.
 468         NULL
 469       };
 470     #endif
 471
 472     #if USES_REGISTER_TABLES == TRUE
 473       CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10DaTableEntryTypeDescriptors[] =
 474       {
 475         {MsrRegister, SetRegisterForMsrEntry},
 476         {PciRegister, SetRegisterForPciEntry},
 477         {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
 478         {HtPhyRegister, SetRegisterForHtPhyEntry},
 479         {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
 480         {DeemphasisRegister, SetRegisterForDeemphasisEntry},
 481         {ProfileFixup, SetRegisterForPerformanceProfileEntry},
 482         {HtHostPciRegister, SetRegisterForHtHostEntry},
 483         {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
 484         {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
 485         {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
 486         {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
 487         {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
 488         // End
 489         {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
 490       };
 491     #endif
 492
 493     CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10DaServices =
 494     {
 495       0,
 496       #if DISABLE_PSTATE == TRUE
 497         F10DisablePstate,
 498       #else
 499         (PF_CPU_DISABLE_PSTATE) CommonAssert,
 500       #endif
 501       #if TRANSITION_PSTATE == TRUE
 502         F10TransitionPstate,
 503       #else
 504         (PF_CPU_TRANSITION_PSTATE) CommonAssert,
 505       #endif
 506       #if PROC_IDD_MAX == TRUE
 507         F10CommonRevCGetProcIddMax,
 508       #else
 509         (PF_CPU_GET_IDD_MAX) CommonAssert,
 510       #endif
 511       #if GET_TSC_RATE == TRUE
 512         F10GetTscRate,
 513       #else
 514         (PF_CPU_GET_TSC_RATE) CommonAssert,
 515       #endif
 516       #if GET_NB_FREQ == TRUE
 517         F10GetCurrentNbFrequency,
 518       #else
 519         (PF_CPU_GET_NB_FREQ) CommonAssert,
 520       #endif
 521       #if GET_NB_FREQ == TRUE
 522         F10RevCGetMinMaxNbFrequency,
 523       #else
 524         (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
 525       #endif
 526       #if GET_NB_FREQ == TRUE
 527         F10CommonRevCGetNbPstateInfo,
 528       #else
 529         (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
 530       #endif
 531       #if IS_NBCOF_INIT_NEEDED == TRUE
 532         F10CommonRevCGetNbCofVidUpdate,
 533       #else
 534         (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
 535       #endif
 536       #if GET_NB_IDD_MAX == TRUE
 537         (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
 538       #else
 539         (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
 540       #endif
 541       #if AP_INITIAL_LAUNCH == TRUE
 542         F10LaunchApCore,
 543       #else
 544         (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
 545       #endif
 546       #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
 547         F10CommonRevCGetNumberOfPhysicalCores,
 548       #else
 549         (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
 550       #endif
 551       #if GET_AP_MAILBOX_FROM_HW == TRUE
 552         F10GetApMailboxFromHardware,
 553       #else
 554         (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
 555       #endif
 556       #if SET_AP_CORE_NUMBER == TRUE
 557         F10SetApCoreNumber,
 558       #else
 559         (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
 560       #endif
 561       #if GET_AP_CORE_NUMBER == TRUE
 562         F10GetApCoreNumber,
 563       #else
 564         (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
 565       #endif
 566       #if TRANSFER_AP_CORE_NUMBER == TRUE
 567         F10TransferApCoreNumber,
 568       #else
 569         (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
 570       #endif
 571       #if ID_POSITION_INITIAL_APICID == TRUE
 572         F10CpuAmdCoreIdPositionInInitialApicId,
 573       #else
 574         (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
 575       #endif
 576       #if SAVE_FEATURES == TRUE
 577         F10SaveFeatures,
 578       #else
 579         (PF_CPU_SAVE_FEATURES) CommonAssert,
 580       #endif
 581       #if WRITE_FEATURES == TRUE
 582         F10WriteFeatures,
 583       #else
 584         (PF_CPU_WRITE_FEATURES) CommonAssert,
 585       #endif
 586       #if SET_WARM_RESET_FLAG == TRUE
 587         F10SetAgesaWarmResetFlag,
 588       #else
 589         (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
 590       #endif
 591       #if GET_WARM_RESET_FLAG == TRUE
 592         F10GetAgesaWarmResetFlag,
 593       #else
 594         (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
 595       #endif
 596       #if BRAND_STRING1 == TRUE
 597         GetF10BrandIdString1,
 598       #else
 599         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 600       #endif
 601       #if BRAND_STRING2 == TRUE
 602         GetF10BrandIdString2,
 603       #else
 604         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 605       #endif
 606       #if GET_PATCHES == TRUE
 607         GetF10DaMicroCodePatchesStruct,
 608       #else
 609         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 610       #endif
 611       #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
 612         GetF10DaMicrocodeEquivalenceTable,
 613       #else
 614         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 615       #endif
 616       #if GET_CACHE_INFO == TRUE
 617         GetF10CacheInfo,
 618       #else
 619         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 620       #endif
 621       #if GET_SYSTEM_PM_TABLE == TRUE
 622         GetF10SysPmTable,
 623       #else
 624         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 625       #endif
 626       #if GET_WHEA_INIT == TRUE
 627         GetF10WheaInitData,
 628       #else
 629         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 630       #endif
 631       #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
 632         F10GetPlatformTypeSpecificInfo,
 633       #else
 634         (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
 635       #endif
 636       #if IS_NB_PSTATE_ENABLED == TRUE
 637         F10CommonRevCIsNbPstateEnabled,
 638       #else
 639         (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
 640       #endif
 641       #if (BASE_FAMILY_HT_PCI == TRUE)
 642         F10NextLinkHasHtPhyFeats,
 643       #else
 644         (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
 645       #endif
 646       #if (BASE_FAMILY_HT_PCI == TRUE)
 647         F10SetHtPhyRegister,
 648       #else
 649         (PF_SET_HT_PHY_REGISTER) CommonAssert,
 650       #endif
 651       #if BASE_FAMILY_PCI == TRUE
 652         F10GetNextHtLinkFeatures,
 653       #else
 654         (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
 655       #endif
 656       #if USES_REGISTER_TABLES == TRUE
 657         (REGISTER_TABLE **) F10DaRegisterTables,
 658       #else
 659         NULL,
 660       #endif
 661       #if USES_REGISTER_TABLES == TRUE
 662         (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10DaTableEntryTypeDescriptors,
 663       #else
 664         NULL,
 665       #endif
 666       NULL,
 667       NULL,
 668       InitCacheDisabled,
 669       #if AGESA_ENTRY_INIT_EARLY == TRUE
 670         GetF10EarlyInitOnCoreTable
 671       #else
 672         (PF_GET_EARLY_INIT_TABLE) CommonVoid
 673       #endif
 674     };
 675
 676     #define DA_SOCKETS 1
 677     #define DA_MODULES 1
 678     #define DA_RECOVERY_SOCKETS 1
 679     #define DA_RECOVERY_MODULES 1
 680     extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10DaLogicalIdAndRev;
 681     #define OPT_F10_DA_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10DaLogicalIdAndRev,
 682     #ifndef ADVCFG_PLATFORM_SOCKETS
 683       #define ADVCFG_PLATFORM_SOCKETS DA_SOCKETS
 684     #else
 685       #if ADVCFG_PLATFORM_SOCKETS < DA_SOCKETS
 686         #undef ADVCFG_PLATFORM_SOCKETS
 687         #define ADVCFG_PLATFORM_SOCKETS DA_SOCKETS
 688       #endif
 689     #endif
 690     #ifndef ADVCFG_PLATFORM_MODULES
 691       #define ADVCFG_PLATFORM_MODULES DA_MODULES
 692     #else
 693       #if ADVCFG_PLATFORM_MODULES < DA_MODULES
 694         #undef ADVCFG_PLATFORM_MODULES
 695         #define ADVCFG_PLATFORM_MODULES DA_MODULES
 696       #endif
 697     #endif
 698
 699     #if GET_PATCHES == TRUE
 700       #define F10_DA_UCODE_C7
 701       #define F10_DA_UCODE_C8
 702
 703       // If a patch is required for recovery mode to function properly, add a
 704       // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
 705       #if AGESA_ENTRY_INIT_EARLY == TRUE
 706         #if (OPTION_S1G3_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE)
 707           extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c7;
 708           #undef F10_DA_UCODE_C7
 709           #define F10_DA_UCODE_C7 &CpuF10MicrocodePatch010000c7,
 710         #endif
 711         #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE) || (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
 712           extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8;
 713           #undef F10_DA_UCODE_C8
 714           #define F10_DA_UCODE_C8 &CpuF10MicrocodePatch010000c8,
 715         #endif
 716       #endif
 717
 718       CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[] =
 719       {
 720         F10_DA_UCODE_C7
 721         F10_DA_UCODE_C8
 722         NULL
 723       };
 724
 725       CONST UINT8 ROMDATA CpuF10DaNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10DaMicroCodePatchArray) / sizeof (CpuF10DaMicroCodePatchArray[0])) - 1);
 726     #endif
 727
 728     #define OPT_F10_DA_CPU {AMD_FAMILY_10_DA, &cpuF10DaServices},
 729   #else
 730     #define OPT_F10_DA_CPU
 731     #define OPT_F10_DA_ID
 732   #endif
 733 #else
 734   #define OPT_F10_DA_CPU
 735   #define OPT_F10_DA_ID
 736 #endif
 737
 738 /*
 739  * Install family 10h models 8 & 9 support
 740  */
 741 #ifdef OPTION_FAMILY10H_HY
 742   #if OPTION_FAMILY10H_HY == TRUE
 743     extern CONST REGISTER_TABLE ROMDATA F10HyPciRegisterTable;
 744     extern CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable;
 745     extern CONST REGISTER_TABLE ROMDATA F10HyHtPhyRegisterTable;
 746     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10HyMicroCodePatchesStruct;
 747     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10HyMicrocodeEquivalenceTable;
 748     extern F_CPU_GET_IDD_MAX F10CommonRevDGetProcIddMax;
 749     extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevDGetNbPstateInfo;
 750     extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevDGetMinMaxNbFrequency;
 751     extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevDGetNbCofVidUpdate;
 752     extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam10RevDPackageLinkMap[];
 753     extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevDGetNumberOfPhysicalCores;
 754     extern F_GET_EARLY_INIT_TABLE GetF10HyEarlyInitOnCoreTable;
 755
 756     #if USES_REGISTER_TABLES == TRUE
 757       CONST REGISTER_TABLE ROMDATA *F10HyRegisterTables[] =
 758       {
 759         #if BASE_FAMILY_PCI == TRUE
 760           &F10PciRegisterTable,
 761         #endif
 762         #if MODEL_SPECIFIC_PCI == TRUE
 763           &F10MultiLinkPciRegisterTable,
 764         #endif
 765         #if MODEL_SPECIFIC_PCI == TRUE
 766           &F10HyPciRegisterTable,
 767         #endif
 768         #if BASE_FAMILY_MSR == TRUE
 769           &F10MsrRegisterTable,
 770         #endif
 771         #if MODEL_SPECIFIC_MSR == TRUE
 772           &F10HyMsrRegisterTable,
 773         #endif
 774         #if MODEL_SPECIFIC_HT_PCI == TRUE
 775           &F10HtPhyRegisterTable,
 776         #endif
 777         #if MODEL_SPECIFIC_HT_PCI == TRUE
 778           &F10HyHtPhyRegisterTable,
 779         #endif
 780         #if BASE_FAMILY_WORKAROUNDS == TRUE
 781           &F10WorkaroundsTable,
 782         #endif
 783         // the end.
 784         NULL
 785       };
 786     #endif
 787
 788     #if USES_REGISTER_TABLES == TRUE
 789       CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10HyTableEntryTypeDescriptors[] =
 790       {
 791         {MsrRegister, SetRegisterForMsrEntry},
 792         {PciRegister, SetRegisterForPciEntry},
 793         {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
 794         {HtPhyRegister, SetRegisterForHtPhyEntry},
 795         {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
 796         {DeemphasisRegister, SetRegisterForDeemphasisEntry},
 797         {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
 798         {ProfileFixup, SetRegisterForPerformanceProfileEntry},
 799         {HtHostPciRegister, SetRegisterForHtHostEntry},
 800         {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
 801         {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
 802         {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
 803         {TokenPciRegister, SetRegisterForTokenPciEntry},
 804         {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
 805         {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
 806         // End
 807         {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
 808       };
 809     #endif
 810
 811     CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10HyServices =
 812     {
 813       0,
 814       #if DISABLE_PSTATE == TRUE
 815         F10DisablePstate,
 816       #else
 817         (PF_CPU_DISABLE_PSTATE) CommonAssert,
 818       #endif
 819       #if TRANSITION_PSTATE == TRUE
 820         F10TransitionPstate,
 821       #else
 822         (PF_CPU_TRANSITION_PSTATE) CommonAssert,
 823       #endif
 824       #if PROC_IDD_MAX == TRUE
 825         F10CommonRevDGetProcIddMax,
 826       #else
 827         (PF_CPU_GET_IDD_MAX) CommonAssert,
 828       #endif
 829       #if GET_TSC_RATE == TRUE
 830         F10GetTscRate,
 831       #else
 832         (PF_CPU_GET_TSC_RATE) CommonAssert,
 833       #endif
 834       #if GET_NB_FREQ == TRUE
 835         F10GetCurrentNbFrequency,
 836       #else
 837         (PF_CPU_GET_NB_FREQ) CommonAssert,
 838       #endif
 839       #if GET_NB_FREQ == TRUE
 840         F10RevDGetMinMaxNbFrequency,
 841       #else
 842         (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
 843       #endif
 844       #if GET_NB_FREQ == TRUE
 845         F10CommonRevDGetNbPstateInfo,
 846       #else
 847         (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
 848       #endif
 849       #if IS_NBCOF_INIT_NEEDED == TRUE
 850         F10CommonRevDGetNbCofVidUpdate,
 851       #else
 852         (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
 853       #endif
 854       #if GET_NB_IDD_MAX == TRUE
 855         (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
 856       #else
 857         (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
 858       #endif
 859       #if AP_INITIAL_LAUNCH == TRUE
 860         F10LaunchApCore,
 861       #else
 862         (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
 863       #endif
 864       #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
 865         F10CommonRevDGetNumberOfPhysicalCores,
 866       #else
 867         (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
 868       #endif
 869       #if GET_AP_MAILBOX_FROM_HW == TRUE
 870         F10GetApMailboxFromHardware,
 871       #else
 872         (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
 873       #endif
 874       #if SET_AP_CORE_NUMBER == TRUE
 875         F10SetApCoreNumber,
 876       #else
 877         (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
 878       #endif
 879       #if GET_AP_CORE_NUMBER == TRUE
 880         F10GetApCoreNumber,
 881       #else
 882         (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
 883       #endif
 884       #if TRANSFER_AP_CORE_NUMBER == TRUE
 885         F10TransferApCoreNumber,
 886       #else
 887         (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
 888       #endif
 889       #if ID_POSITION_INITIAL_APICID == TRUE
 890         F10CpuAmdCoreIdPositionInInitialApicId,
 891       #else
 892         (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
 893       #endif
 894       #if SAVE_FEATURES == TRUE
 895         F10SaveFeatures,
 896       #else
 897         (PF_CPU_SAVE_FEATURES) CommonAssert,
 898       #endif
 899       #if WRITE_FEATURES == TRUE
 900         F10WriteFeatures,
 901       #else
 902         (PF_CPU_WRITE_FEATURES) CommonAssert,
 903       #endif
 904       #if SET_WARM_RESET_FLAG == TRUE
 905         F10SetAgesaWarmResetFlag,
 906       #else
 907         (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
 908       #endif
 909       #if GET_WARM_RESET_FLAG == TRUE
 910         F10GetAgesaWarmResetFlag,
 911       #else
 912         (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
 913       #endif
 914       #if BRAND_STRING1 == TRUE
 915         GetF10BrandIdString1,
 916       #else
 917         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 918       #endif
 919       #if BRAND_STRING2 == TRUE
 920         GetF10BrandIdString2,
 921       #else
 922         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 923       #endif
 924       #if GET_PATCHES == TRUE
 925         GetF10HyMicroCodePatchesStruct,
 926       #else
 927         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 928       #endif
 929       #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
 930         GetF10HyMicrocodeEquivalenceTable,
 931       #else
 932         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 933       #endif
 934       #if GET_CACHE_INFO == TRUE
 935         GetF10CacheInfo,
 936       #else
 937         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 938       #endif
 939       #if GET_SYSTEM_PM_TABLE == TRUE
 940         GetF10SysPmTable,
 941       #else
 942         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 943       #endif
 944       #if GET_WHEA_INIT == TRUE
 945         GetF10WheaInitData,
 946       #else
 947         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
 948       #endif
 949       #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
 950         F10GetPlatformTypeSpecificInfo,
 951       #else
 952         (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
 953       #endif
 954       #if IS_NB_PSTATE_ENABLED == TRUE
 955         (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
 956       #else
 957         (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
 958       #endif
 959       #if (BASE_FAMILY_HT_PCI == TRUE)
 960         F10NextLinkHasHtPhyFeats,
 961       #else
 962         (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
 963       #endif
 964       #if (BASE_FAMILY_HT_PCI == TRUE)
 965         F10SetHtPhyRegister,
 966       #else
 967         (PF_SET_HT_PHY_REGISTER) CommonAssert,
 968       #endif
 969       #if BASE_FAMILY_PCI == TRUE
 970         F10GetNextHtLinkFeatures,
 971       #else
 972         (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
 973       #endif
 974       #if USES_REGISTER_TABLES == TRUE
 975         (REGISTER_TABLE **) F10HyRegisterTables,
 976       #else
 977         NULL,
 978       #endif
 979       #if USES_REGISTER_TABLES == TRUE
 980         (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10HyTableEntryTypeDescriptors,
 981       #else
 982         NULL,
 983       #endif
 984       #if MODEL_SPECIFIC_HT_PCI == TRUE
 985         (PACKAGE_HTLINK_MAP) &HtFam10RevDPackageLinkMap,
 986       #else
 987         NULL,
 988       #endif
 989       NULL,
 990       InitCacheDisabled,
 991       #if AGESA_ENTRY_INIT_EARLY == TRUE
 992         #if OPTION_C32_SOCKET_SUPPORT == TRUE
 993           GetF10HyEarlyInitOnCoreTable
 994         #else
 995           GetF10EarlyInitOnCoreTable
 996         #endif
 997       #else
 998         (PF_GET_EARLY_INIT_TABLE) CommonVoid
 999       #endif
1000     };
1001
1002     #define HY_SOCKETS 8
1003     #if (OPTION_G34_SOCKET_SUPPORT == TRUE)
1004       #define HY_MODULES 2
1005     #else
1006       #define HY_MODULES 1
1007     #endif
1008     #define HY_RECOVERY_SOCKETS 1
1009     #define HY_RECOVERY_MODULES 1
1010     extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10HyLogicalIdAndRev;
1011     #define OPT_F10_HY_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10HyLogicalIdAndRev,
1012     #ifndef ADVCFG_PLATFORM_SOCKETS
1013       #define ADVCFG_PLATFORM_SOCKETS HY_SOCKETS
1014     #else
1015       #if ADVCFG_PLATFORM_SOCKETS < HY_SOCKETS
1016         #undef ADVCFG_PLATFORM_SOCKETS
1017         #define ADVCFG_PLATFORM_SOCKETS HY_SOCKETS
1018       #endif
1019     #endif
1020     #ifndef ADVCFG_PLATFORM_MODULES
1021       #define ADVCFG_PLATFORM_MODULES HY_MODULES
1022     #else
1023       #if ADVCFG_PLATFORM_MODULES < HY_MODULES
1024         #undef ADVCFG_PLATFORM_MODULES
1025         #define ADVCFG_PLATFORM_MODULES HY_MODULES
1026       #endif
1027     #endif
1028
1029     #if GET_PATCHES == TRUE
1030       #define F10_HY_UCODE_D9
1031       #define F10_HY_UCODE_C5
1032
1033       // If a patch is required for recovery mode to function properly, add a
1034       // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
1035       #if AGESA_ENTRY_INIT_EARLY == TRUE
1036         #if OPTION_C32_SOCKET_SUPPORT == TRUE
1037           extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c5;
1038           #undef F10_HY_UCODE_C5
1039           #define F10_HY_UCODE_C5 &CpuF10MicrocodePatch010000c5,
1040         #endif
1041         #if (OPTION_C32_SOCKET_SUPPORT == TRUE) || (OPTION_G34_SOCKET_SUPPORT == TRUE)
1042           extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000d9;
1043           #undef F10_HY_UCODE_D9
1044           #define F10_HY_UCODE_D9 &CpuF10MicrocodePatch010000d9,
1045         #endif
1046       #endif
1047
1048       CONST MICROCODE_PATCHES ROMDATA *CpuF10HyMicroCodePatchArray[] =
1049       {
1050         F10_HY_UCODE_D9
1051         F10_HY_UCODE_C5
1052         NULL
1053       };
1054
1055       CONST UINT8 ROMDATA CpuF10HyNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10HyMicroCodePatchArray) / sizeof (CpuF10HyMicroCodePatchArray[0])) - 1);
1056     #endif
1057
1058     #define OPT_F10_HY_CPU {AMD_FAMILY_10_HY, &cpuF10HyServices},
1059   #else
1060     #define OPT_F10_HY_CPU
1061     #define OPT_F10_HY_ID
1062   #endif
1063 #else
1064   #define OPT_F10_HY_CPU
1065   #define OPT_F10_HY_ID
1066 #endif
1067
1068 /*
1069  * Install family 10h model 10 support
1070  */
1071 #ifdef OPTION_FAMILY10H_PH
1072   #if OPTION_FAMILY10H_PH == TRUE
1073     extern CONST REGISTER_TABLE ROMDATA F10RevEPciRegisterTable;
1074     extern CONST REGISTER_TABLE ROMDATA F10RevEMsrRegisterTable;
1075     extern CONST REGISTER_TABLE ROMDATA F10RevEHtPhyRegisterTable;
1076     extern CONST REGISTER_TABLE ROMDATA F10PhPciRegisterTable;
1077     extern CONST REGISTER_TABLE ROMDATA F10PhMsrRegisterTable;
1078     extern CONST REGISTER_TABLE ROMDATA F10PhHtPhyRegisterTable;
1079     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10PhMicroCodePatchesStruct;
1080     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10PhMicrocodeEquivalenceTable;
1081     extern F_CPU_GET_IDD_MAX F10CommonRevEGetProcIddMax;
1082     extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevEGetNbPstateInfo;
1083     extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevEGetMinMaxNbFrequency;
1084     extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevEGetNbCofVidUpdate;
1085     extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevEGetNumberOfPhysicalCores;
1086
1087     #if USES_REGISTER_TABLES == TRUE
1088       CONST REGISTER_TABLE ROMDATA *F10PhRegisterTables[] =
1089       {
1090         #if BASE_FAMILY_PCI == TRUE
1091           &F10PciRegisterTable,
1092         #endif
1093         #if MODEL_SPECIFIC_PCI == TRUE
1094           &F10SingleLinkPciRegisterTable,
1095         #endif
1096         #if MODEL_SPECIFIC_PCI == TRUE
1097           &F10RevEPciRegisterTable,
1098         #endif
1099         #if BASE_FAMILY_MSR == TRUE
1100           &F10MsrRegisterTable,
1101         #endif
1102         #if MODEL_SPECIFIC_MSR == TRUE
1103           &F10RevEMsrRegisterTable,
1104         #endif
1105         #if MODEL_SPECIFIC_HT_PCI == TRUE
1106           &F10HtPhyRegisterTable,
1107         #endif
1108         #if MODEL_SPECIFIC_HT_PCI == TRUE
1109           &F10RevEHtPhyRegisterTable,
1110         #endif
1111         #if MODEL_SPECIFIC_HT_PCI == TRUE
1112           &F10PhHtPhyRegisterTable,
1113         #endif
1114         #if BASE_FAMILY_WORKAROUNDS == TRUE
1115           &F10WorkaroundsTable,
1116         #endif
1117         // the end.
1118         NULL
1119       };
1120     #endif
1121
1122     #if USES_REGISTER_TABLES == TRUE
1123       CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10PhTableEntryTypeDescriptors[] =
1124       {
1125         {MsrRegister, SetRegisterForMsrEntry},
1126         {PciRegister, SetRegisterForPciEntry},
1127         {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
1128         {HtPhyRegister, SetRegisterForHtPhyEntry},
1129         {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
1130         {DeemphasisRegister, SetRegisterForDeemphasisEntry},
1131         {ProfileFixup, SetRegisterForPerformanceProfileEntry},
1132         {HtHostPciRegister, SetRegisterForHtHostEntry},
1133         {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
1134         {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
1135         {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
1136         {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
1137         {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
1138         // End
1139         {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
1140       };
1141     #endif
1142
1143     CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10PhServices =
1144     {
1145       0,
1146       #if DISABLE_PSTATE == TRUE
1147         F10DisablePstate,
1148       #else
1149         (PF_CPU_DISABLE_PSTATE) CommonAssert,
1150       #endif
1151       #if TRANSITION_PSTATE == TRUE
1152         F10TransitionPstate,
1153       #else
1154         (PF_CPU_TRANSITION_PSTATE) CommonAssert,
1155       #endif
1156       #if PROC_IDD_MAX == TRUE
1157         F10CommonRevEGetProcIddMax,
1158       #else
1159         (PF_CPU_GET_IDD_MAX) CommonAssert,
1160       #endif
1161       #if GET_TSC_RATE == TRUE
1162         F10GetTscRate,
1163       #else
1164         (PF_CPU_GET_TSC_RATE) CommonAssert,
1165       #endif
1166       #if GET_NB_FREQ == TRUE
1167         F10GetCurrentNbFrequency,
1168       #else
1169         (PF_CPU_GET_NB_FREQ) CommonAssert,
1170       #endif
1171       #if GET_NB_FREQ == TRUE
1172         F10RevEGetMinMaxNbFrequency,
1173       #else
1174         (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
1175       #endif
1176       #if GET_NB_FREQ == TRUE
1177         F10CommonRevEGetNbPstateInfo,
1178       #else
1179         (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
1180       #endif
1181       #if IS_NBCOF_INIT_NEEDED == TRUE
1182         F10CommonRevEGetNbCofVidUpdate,
1183       #else
1184         (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
1185       #endif
1186       #if GET_NB_IDD_MAX == TRUE
1187         (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
1188       #else
1189         (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
1190       #endif
1191       #if AP_INITIAL_LAUNCH == TRUE
1192         F10LaunchApCore,
1193       #else
1194         (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
1195       #endif
1196       #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
1197         F10CommonRevEGetNumberOfPhysicalCores,
1198       #else
1199         (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
1200       #endif
1201       #if GET_AP_MAILBOX_FROM_HW == TRUE
1202         F10GetApMailboxFromHardware,
1203       #else
1204         (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
1205       #endif
1206       #if SET_AP_CORE_NUMBER == TRUE
1207         F10SetApCoreNumber,
1208       #else
1209         (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
1210       #endif
1211       #if GET_AP_CORE_NUMBER == TRUE
1212         F10GetApCoreNumber,
1213       #else
1214         (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
1215       #endif
1216       #if TRANSFER_AP_CORE_NUMBER == TRUE
1217         F10TransferApCoreNumber,
1218       #else
1219         (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
1220       #endif
1221       #if ID_POSITION_INITIAL_APICID == TRUE
1222         F10CpuAmdCoreIdPositionInInitialApicId,
1223       #else
1224         (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
1225       #endif
1226       #if SAVE_FEATURES == TRUE
1227         F10SaveFeatures,
1228       #else
1229         (PF_CPU_SAVE_FEATURES) CommonAssert,
1230       #endif
1231       #if WRITE_FEATURES == TRUE
1232         F10WriteFeatures,
1233       #else
1234         (PF_CPU_WRITE_FEATURES) CommonAssert,
1235       #endif
1236       #if SET_WARM_RESET_FLAG == TRUE
1237         F10SetAgesaWarmResetFlag,
1238       #else
1239         (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
1240       #endif
1241       #if GET_WARM_RESET_FLAG == TRUE
1242         F10GetAgesaWarmResetFlag,
1243       #else
1244         (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
1245       #endif
1246       #if BRAND_STRING1 == TRUE
1247         GetF10BrandIdString1,
1248       #else
1249         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1250       #endif
1251       #if BRAND_STRING2 == TRUE
1252         GetF10BrandIdString2,
1253       #else
1254         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1255       #endif
1256       #if GET_PATCHES == TRUE
1257         GetF10PhMicroCodePatchesStruct,
1258       #else
1259         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1260       #endif
1261       #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
1262         GetF10PhMicrocodeEquivalenceTable,
1263       #else
1264         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1265       #endif
1266       #if GET_CACHE_INFO == TRUE
1267         GetF10CacheInfo,
1268       #else
1269         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1270       #endif
1271       #if GET_SYSTEM_PM_TABLE == TRUE
1272         GetF10SysPmTable,
1273       #else
1274         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1275       #endif
1276       #if GET_WHEA_INIT == TRUE
1277         GetF10WheaInitData,
1278       #else
1279         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1280       #endif
1281       #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
1282         F10GetPlatformTypeSpecificInfo,
1283       #else
1284         (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
1285       #endif
1286       #if IS_NB_PSTATE_ENABLED == TRUE
1287         (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
1288       #else
1289         (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
1290       #endif
1291       #if (BASE_FAMILY_HT_PCI == TRUE)
1292         F10NextLinkHasHtPhyFeats,
1293       #else
1294         (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
1295       #endif
1296       #if (BASE_FAMILY_HT_PCI == TRUE)
1297         F10SetHtPhyRegister,
1298       #else
1299         (PF_SET_HT_PHY_REGISTER) CommonAssert,
1300       #endif
1301       #if BASE_FAMILY_PCI == TRUE
1302         F10GetNextHtLinkFeatures,
1303       #else
1304         (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
1305       #endif
1306       #if USES_REGISTER_TABLES == TRUE
1307         (REGISTER_TABLE **) F10PhRegisterTables,
1308       #else
1309         NULL,
1310       #endif
1311       #if USES_REGISTER_TABLES == TRUE
1312         (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10PhTableEntryTypeDescriptors,
1313       #else
1314         NULL,
1315       #endif
1316       NULL,
1317       NULL,
1318       InitCacheDisabled,
1319       #if AGESA_ENTRY_INIT_EARLY == TRUE
1320         GetF10EarlyInitOnCoreTable
1321       #else
1322         (PF_GET_EARLY_INIT_TABLE) CommonVoid
1323       #endif
1324     };
1325
1326     #define PH_SOCKETS 1
1327     #define PH_MODULES 1
1328     #define PH_RECOVERY_SOCKETS 1
1329     #define PH_RECOVERY_MODULES 1
1330     extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10PhLogicalIdAndRev;
1331     #define OPT_F10_PH_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10PhLogicalIdAndRev,
1332     #ifndef ADVCFG_PLATFORM_SOCKETS
1333       #define ADVCFG_PLATFORM_SOCKETS PH_SOCKETS
1334     #else
1335       #if ADVCFG_PLATFORM_SOCKETS < PH_SOCKETS
1336         #undef ADVCFG_PLATFORM_SOCKETS
1337         #define ADVCFG_PLATFORM_SOCKETS PH_SOCKETS
1338       #endif
1339     #endif
1340     #ifndef ADVCFG_PLATFORM_MODULES
1341       #define ADVCFG_PLATFORM_MODULES PH_MODULES
1342     #else
1343       #if ADVCFG_PLATFORM_MODULES < PH_MODULES
1344         #undef ADVCFG_PLATFORM_MODULES
1345         #define ADVCFG_PLATFORM_MODULES PH_MODULES
1346       #endif
1347     #endif
1348
1349     #if GET_PATCHES == TRUE
1350       #define F10_PH_UCODE_BF
1351
1352       // If a patch is required for recovery mode to function properly, add a
1353       // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
1354       #if AGESA_ENTRY_INIT_EARLY == TRUE
1355         #if OPTION_AM3_SOCKET_SUPPORT == TRUE
1356           extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000bf;
1357           #undef F10_PH_UCODE_BF
1358           #define F10_PH_UCODE_BF &CpuF10MicrocodePatch010000bf,
1359         #endif
1360       #endif
1361
1362       CONST MICROCODE_PATCHES ROMDATA *CpuF10PhMicroCodePatchArray[] =
1363       {
1364         F10_PH_UCODE_BF
1365         NULL
1366       };
1367
1368       CONST UINT8 ROMDATA CpuF10PhNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10PhMicroCodePatchArray) / sizeof (CpuF10PhMicroCodePatchArray[0])) - 1);
1369     #endif
1370
1371     #define OPT_F10_PH_CPU {AMD_FAMILY_10_PH, &cpuF10PhServices},
1372   #else
1373     #define OPT_F10_PH_CPU
1374     #define OPT_F10_PH_ID
1375   #endif
1376 #else
1377   #define OPT_F10_PH_CPU
1378   #define OPT_F10_PH_ID
1379 #endif
1380
1381
1382 /*
1383  * Install family 10h model 4 support
1384  */
1385 #ifdef OPTION_FAMILY10H_RB
1386   #if OPTION_FAMILY10H_RB == TRUE
1387     extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
1388     extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
1389     extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
1390     extern CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable;
1391     extern CONST REGISTER_TABLE ROMDATA F10RbMsrRegisterTable;
1392     extern CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable;
1393     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10RbMicroCodePatchesStruct;
1394     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10RbMicrocodeEquivalenceTable;
1395     extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
1396     extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo;
1397     extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevCGetMinMaxNbFrequency;
1398     extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
1399     extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
1400     extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevCGetNumberOfPhysicalCores;
1401
1402     #if USES_REGISTER_TABLES == TRUE
1403       CONST REGISTER_TABLE ROMDATA *F10RbRegisterTables[] =
1404       {
1405         #if BASE_FAMILY_PCI == TRUE
1406           &F10PciRegisterTable,
1407         #endif
1408         #if MODEL_SPECIFIC_PCI == TRUE
1409           &F10MultiLinkPciRegisterTable,
1410           &F10SingleLinkPciRegisterTable,
1411         #endif
1412         #if MODEL_SPECIFIC_PCI == TRUE
1413           &F10RevCPciRegisterTable,
1414         #endif
1415         #if MODEL_SPECIFIC_PCI == TRUE
1416           &F10RbPciRegisterTable,
1417         #endif
1418         #if BASE_FAMILY_MSR == TRUE
1419           &F10MsrRegisterTable,
1420         #endif
1421         #if MODEL_SPECIFIC_MSR == TRUE
1422           &F10RevCMsrRegisterTable,
1423         #endif
1424         #if MODEL_SPECIFIC_MSR == TRUE
1425           &F10RbMsrRegisterTable,
1426         #endif
1427         #if MODEL_SPECIFIC_HT_PCI == TRUE
1428           &F10HtPhyRegisterTable,
1429         #endif
1430         #if MODEL_SPECIFIC_HT_PCI == TRUE
1431           &F10RevCHtPhyRegisterTable,
1432         #endif
1433         #if MODEL_SPECIFIC_HT_PCI == TRUE
1434           &F10RbHtPhyRegisterTable,
1435         #endif
1436         #if BASE_FAMILY_WORKAROUNDS == TRUE
1437           &F10WorkaroundsTable,
1438         #endif
1439         // the end.
1440         NULL
1441       };
1442     #endif
1443
1444     #if USES_REGISTER_TABLES == TRUE
1445       CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10RbTableEntryTypeDescriptors[] =
1446       {
1447         {MsrRegister, SetRegisterForMsrEntry},
1448         {PciRegister, SetRegisterForPciEntry},
1449         {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
1450         {HtPhyRegister, SetRegisterForHtPhyEntry},
1451         {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
1452         {DeemphasisRegister, SetRegisterForDeemphasisEntry},
1453         {ProfileFixup, SetRegisterForPerformanceProfileEntry},
1454         {HtHostPciRegister, SetRegisterForHtHostEntry},
1455         {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
1456         {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
1457         {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
1458         {TokenPciRegister, SetRegisterForTokenPciEntry},
1459         {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
1460         {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
1461         // End
1462         {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
1463       };
1464     #endif
1465
1466     CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10RbServices =
1467     {
1468       0,
1469       #if DISABLE_PSTATE == TRUE
1470         F10DisablePstate,
1471       #else
1472         (PF_CPU_DISABLE_PSTATE) CommonAssert,
1473       #endif
1474       #if TRANSITION_PSTATE == TRUE
1475         F10TransitionPstate,
1476       #else
1477         (PF_CPU_TRANSITION_PSTATE) CommonAssert,
1478       #endif
1479       #if PROC_IDD_MAX == TRUE
1480         F10CommonRevCGetProcIddMax,
1481       #else
1482         (PF_CPU_GET_IDD_MAX) CommonAssert,
1483       #endif
1484       #if GET_TSC_RATE == TRUE
1485         F10GetTscRate,
1486       #else
1487         (PF_CPU_GET_TSC_RATE) CommonAssert,
1488       #endif
1489       #if GET_NB_FREQ == TRUE
1490         F10GetCurrentNbFrequency,
1491       #else
1492         (PF_CPU_GET_NB_FREQ) CommonAssert,
1493       #endif
1494       #if GET_NB_FREQ == TRUE
1495         F10RevCGetMinMaxNbFrequency,
1496       #else
1497         (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
1498       #endif
1499       #if GET_NB_FREQ == TRUE
1500         F10CommonRevCGetNbPstateInfo,
1501       #else
1502         (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
1503       #endif
1504       #if IS_NBCOF_INIT_NEEDED == TRUE
1505         F10CommonRevCGetNbCofVidUpdate,
1506       #else
1507         (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
1508       #endif
1509       #if GET_NB_IDD_MAX == TRUE
1510         (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
1511       #else
1512         (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
1513       #endif
1514       #if AP_INITIAL_LAUNCH == TRUE
1515         F10LaunchApCore,
1516       #else
1517         (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
1518       #endif
1519       #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
1520         F10CommonRevCGetNumberOfPhysicalCores,
1521       #else
1522         (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
1523       #endif
1524       #if GET_AP_MAILBOX_FROM_HW == TRUE
1525         F10GetApMailboxFromHardware,
1526       #else
1527         (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
1528       #endif
1529       #if SET_AP_CORE_NUMBER == TRUE
1530         F10SetApCoreNumber,
1531       #else
1532         (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
1533       #endif
1534       #if GET_AP_CORE_NUMBER == TRUE
1535         F10GetApCoreNumber,
1536       #else
1537         (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
1538       #endif
1539       #if TRANSFER_AP_CORE_NUMBER == TRUE
1540         F10TransferApCoreNumber,
1541       #else
1542         (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
1543       #endif
1544       #if ID_POSITION_INITIAL_APICID == TRUE
1545         F10CpuAmdCoreIdPositionInInitialApicId,
1546       #else
1547         (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
1548       #endif
1549       #if SAVE_FEATURES == TRUE
1550         F10SaveFeatures,
1551       #else
1552         (PF_CPU_SAVE_FEATURES) CommonAssert,
1553       #endif
1554       #if WRITE_FEATURES == TRUE
1555         F10WriteFeatures,
1556       #else
1557         (PF_CPU_WRITE_FEATURES) CommonAssert,
1558       #endif
1559       #if SET_WARM_RESET_FLAG == TRUE
1560         F10SetAgesaWarmResetFlag,
1561       #else
1562         (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
1563       #endif
1564       #if GET_WARM_RESET_FLAG == TRUE
1565         F10GetAgesaWarmResetFlag,
1566       #else
1567         (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
1568       #endif
1569       #if BRAND_STRING1 == TRUE
1570         GetF10BrandIdString1,
1571       #else
1572         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1573       #endif
1574       #if BRAND_STRING2 == TRUE
1575         GetF10BrandIdString2,
1576       #else
1577         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1578       #endif
1579       #if GET_PATCHES == TRUE
1580         GetF10RbMicroCodePatchesStruct,
1581       #else
1582         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1583       #endif
1584       #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
1585         GetF10RbMicrocodeEquivalenceTable,
1586       #else
1587         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1588       #endif
1589       #if GET_CACHE_INFO == TRUE
1590         GetF10CacheInfo,
1591       #else
1592         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1593       #endif
1594       #if GET_SYSTEM_PM_TABLE == TRUE
1595         GetF10SysPmTable,
1596       #else
1597         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1598       #endif
1599       #if GET_WHEA_INIT == TRUE
1600         GetF10WheaInitData,
1601       #else
1602         (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1603       #endif
1604       #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
1605         F10GetPlatformTypeSpecificInfo,
1606       #else
1607         (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
1608       #endif
1609       #if IS_NB_PSTATE_ENABLED == TRUE
1610         F10CommonRevCIsNbPstateEnabled,
1611       #else
1612         (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
1613       #endif
1614       #if (BASE_FAMILY_HT_PCI == TRUE)
1615         F10NextLinkHasHtPhyFeats,
1616       #else
1617         (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
1618       #endif
1619       #if (BASE_FAMILY_HT_PCI == TRUE)
1620         F10SetHtPhyRegister,
1621       #else
1622         (PF_SET_HT_PHY_REGISTER) CommonAssert,
1623       #endif
1624       #if BASE_FAMILY_PCI == TRUE
1625         F10GetNextHtLinkFeatures,
1626       #else
1627         (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
1628       #endif
1629       #if USES_REGISTER_TABLES == TRUE
1630         (REGISTER_TABLE **) F10RbRegisterTables,
1631       #else
1632         NULL,
1633       #endif
1634       #if USES_REGISTER_TABLES == TRUE
1635         (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10RbTableEntryTypeDescriptors,
1636       #else
1637         NULL,
1638       #endif
1639       NULL,
1640       NULL,
1641       InitCacheDisabled,
1642       #if AGESA_ENTRY_INIT_EARLY == TRUE
1643         GetF10EarlyInitOnCoreTable
1644       #else
1645         (PF_GET_EARLY_INIT_TABLE) CommonVoid
1646       #endif
1647     };
1648
1649     #define RB_SOCKETS 8
1650     #define RB_MODULES 1
1651     #define RB_RECOVERY_SOCKETS 1
1652     #define RB_RECOVERY_MODULES 1
1653     extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10RbLogicalIdAndRev;
1654     #define OPT_F10_RB_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10RbLogicalIdAndRev,
1655     #ifndef ADVCFG_PLATFORM_SOCKETS
1656       #define ADVCFG_PLATFORM_SOCKETS RB_SOCKETS
1657     #else
1658       #if ADVCFG_PLATFORM_SOCKETS < RB_SOCKETS
1659         #undef ADVCFG_PLATFORM_SOCKETS
1660         #define ADVCFG_PLATFORM_SOCKETS RB_SOCKETS
1661       #endif
1662     #endif
1663     #ifndef ADVCFG_PLATFORM_MODULES
1664       #define ADVCFG_PLATFORM_MODULES RB_MODULES
1665     #else
1666       #if ADVCFG_PLATFORM_MODULES < RB_MODULES
1667         #undef ADVCFG_PLATFORM_MODULES
1668         #define ADVCFG_PLATFORM_MODULES RB_MODULES
1669       #endif
1670     #endif
1671
1672     #if GET_PATCHES == TRUE
1673       #define F10_RB_UCODE_85
1674       #define F10_RB_UCODE_C6
1675       #define F10_RB_UCODE_C8
1676
1677       // If a patch is required for recovery mode to function properly, add a
1678       // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
1679       #if AGESA_ENTRY_INIT_EARLY == TRUE
1680         #if OPTION_AM3_SOCKET_SUPPORT == TRUE
1681           extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000085;
1682           extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c6;
1683           extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8;
1684           #undef F10_RB_UCODE_85
1685           #define F10_RB_UCODE_85 &CpuF10MicrocodePatch01000085,
1686           #undef F10_RB_UCODE_C6
1687           #define F10_RB_UCODE_C6 &CpuF10MicrocodePatch010000c6,
1688           #undef F10_RB_UCODE_C8
1689           #define F10_RB_UCODE_C8 &CpuF10MicrocodePatch010000c8,
1690         #endif
1691       #endif
1692
1693       CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[] =
1694       {
1695         F10_RB_UCODE_85
1696         F10_RB_UCODE_C6
1697         F10_RB_UCODE_C8
1698         NULL
1699       };
1700
1701       CONST UINT8 ROMDATA CpuF10RbNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10RbMicroCodePatchArray) / sizeof (CpuF10RbMicroCodePatchArray[0])) - 1);
1702     #endif
1703
1704     #define OPT_F10_RB_CPU {AMD_FAMILY_10_RB, &cpuF10RbServices},
1705   #else
1706     #define OPT_F10_RB_CPU
1707     #define OPT_F10_RB_ID
1708   #endif
1709 #else
1710   #define OPT_F10_RB_CPU
1711   #define OPT_F10_RB_ID
1712 #endif
1713
1714
1715 /*
1716  * Install unknown family 10h support
1717  */
1718
1719 #if USES_REGISTER_TABLES == TRUE
1720   CONST REGISTER_TABLE ROMDATA *F10UnknownRegisterTables[] =
1721   {
1722     #if BASE_FAMILY_PCI == TRUE
1723       &F10PciRegisterTable,
1724     #endif
1725     #if BASE_FAMILY_MSR == TRUE
1726       &F10MsrRegisterTable,
1727     #endif
1728     #if BASE_FAMILY_HT_PCI == TRUE
1729       &F10HtPhyRegisterTable,
1730     #endif
1731     #if OPTION_MULTISOCKET == TRUE
1732       #if MODEL_SPECIFIC_PCI == TRUE
1733         &F10MultiLinkPciRegisterTable,
1734       #endif
1735     #endif
1736     #if OPTION_MULTISOCKET == FALSE
1737       #if MODEL_SPECIFIC_PCI == TRUE
1738         &F10SingleLinkPciRegisterTable,
1739       #endif
1740     #endif
1741     #if BASE_FAMILY_WORKAROUNDS == TRUE
1742       &F10WorkaroundsTable,
1743     #endif
1744     // the end.
1745     NULL
1746   };
1747 #endif
1748
1749 #if USES_REGISTER_TABLES == TRUE
1750   CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10UnknownTableEntryTypeDescriptors[] =
1751   {
1752     {MsrRegister, SetRegisterForMsrEntry},
1753     {PciRegister, SetRegisterForPciEntry},
1754     {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
1755     {HtPhyRegister, SetRegisterForHtPhyEntry},
1756     {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
1757     {DeemphasisRegister, SetRegisterForDeemphasisEntry},
1758     {ProfileFixup, SetRegisterForPerformanceProfileEntry},
1759     {HtHostPciRegister, SetRegisterForHtHostEntry},
1760     {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
1761     {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
1762     {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
1763     {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
1764     // End
1765     {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
1766   };
1767 #endif
1768
1769
1770 CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10UnknownServices =
1771 {
1772   0,
1773   #if DISABLE_PSTATE == TRUE
1774     F10DisablePstate,
1775   #else
1776     (PF_CPU_DISABLE_PSTATE) CommonAssert,
1777   #endif
1778   #if TRANSITION_PSTATE == TRUE
1779     F10TransitionPstate,
1780   #else
1781     (PF_CPU_TRANSITION_PSTATE) CommonAssert,
1782   #endif
1783   #if PROC_IDD_MAX == TRUE
1784     (PF_CPU_GET_IDD_MAX) CommonReturnFalse,
1785   #else
1786     (PF_CPU_GET_IDD_MAX) CommonAssert,
1787   #endif
1788   #if GET_TSC_RATE == TRUE
1789     F10GetTscRate,
1790   #else
1791     (PF_CPU_GET_TSC_RATE) CommonAssert,
1792   #endif
1793   #if GET_NB_FREQ == TRUE
1794     F10GetCurrentNbFrequency,
1795   #else
1796     (PF_CPU_GET_NB_FREQ) CommonAssert,
1797   #endif
1798   #if GET_NB_FREQ == TRUE
1799     (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonReturnFalse,
1800   #else
1801     (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
1802   #endif
1803   #if GET_NB_FREQ == TRUE
1804     (PF_CPU_GET_NB_PSTATE_INFO) CommonReturnFalse,
1805   #else
1806     (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
1807   #endif
1808   #if IS_NBCOF_INIT_NEEDED == TRUE
1809     (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse,
1810   #else
1811     (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
1812   #endif
1813   #if GET_NB_IDD_MAX == TRUE
1814     (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
1815   #else
1816     (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
1817   #endif
1818   #if AP_INITIAL_LAUNCH == TRUE
1819     F10LaunchApCore,
1820   #else
1821     (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
1822   #endif
1823   #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
1824     (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonReturnZero8,
1825   #else
1826     (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
1827   #endif
1828   #if GET_AP_MAILBOX_FROM_HW == TRUE
1829     F10GetApMailboxFromHardware,
1830   #else
1831     (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
1832   #endif
1833   #if SET_AP_CORE_NUMBER == TRUE
1834     F10SetApCoreNumber,
1835   #else
1836     (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
1837   #endif
1838   #if GET_AP_CORE_NUMBER == TRUE
1839     F10GetApCoreNumber,
1840   #else
1841     (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
1842   #endif
1843   #if TRANSFER_AP_CORE_NUMBER == TRUE
1844     F10TransferApCoreNumber,
1845   #else
1846     (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
1847   #endif
1848   #if ID_POSITION_INITIAL_APICID == TRUE
1849     F10CpuAmdCoreIdPositionInInitialApicId,
1850   #else
1851     (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
1852   #endif
1853   #if SAVE_FEATURES == TRUE
1854     F10SaveFeatures,
1855   #else
1856     (PF_CPU_SAVE_FEATURES) CommonAssert,
1857   #endif
1858   #if WRITE_FEATURES == TRUE
1859     F10WriteFeatures,
1860   #else
1861     (PF_CPU_WRITE_FEATURES) CommonAssert,
1862   #endif
1863   #if SET_WARM_RESET_FLAG == TRUE
1864     F10SetAgesaWarmResetFlag,
1865   #else
1866     (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
1867   #endif
1868   #if GET_WARM_RESET_FLAG == TRUE
1869     F10GetAgesaWarmResetFlag,
1870   #else
1871     (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
1872   #endif
1873   #if BRAND_STRING1 == TRUE
1874     GetF10BrandIdString1,
1875   #else
1876     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1877   #endif
1878   #if BRAND_STRING2 == TRUE
1879     GetF10BrandIdString2,
1880   #else
1881     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1882   #endif
1883   #if GET_PATCHES == TRUE
1884     GetEmptyArray,
1885   #else
1886     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1887   #endif
1888   #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
1889     GetEmptyArray,
1890   #else
1891     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1892   #endif
1893   #if GET_CACHE_INFO == TRUE
1894     GetF10CacheInfo,
1895   #else
1896     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1897   #endif
1898   #if GET_SYSTEM_PM_TABLE == TRUE
1899     GetF10SysPmTable,
1900   #else
1901     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1902   #endif
1903   #if GET_WHEA_INIT == TRUE
1904     GetF10WheaInitData,
1905   #else
1906     (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1907   #endif
1908   #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
1909     F10GetPlatformTypeSpecificInfo,
1910   #else
1911     (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
1912   #endif
1913   #if IS_NB_PSTATE_ENABLED == TRUE
1914     (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
1915   #else
1916     (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
1917   #endif
1918   #if (BASE_FAMILY_HT_PCI == TRUE)
1919     F10NextLinkHasHtPhyFeats,
1920   #else
1921     (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
1922   #endif
1923   #if (BASE_FAMILY_HT_PCI == TRUE)
1924     F10SetHtPhyRegister,
1925   #else
1926     (PF_SET_HT_PHY_REGISTER) CommonVoid,
1927   #endif
1928   #if BASE_FAMILY_PCI == TRUE
1929     F10GetNextHtLinkFeatures,
1930   #else
1931     (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
1932   #endif
1933   #if USES_REGISTER_TABLES == TRUE
1934     (REGISTER_TABLE **) F10UnknownRegisterTables,
1935   #else
1936     NULL,
1937   #endif
1938   #if USES_REGISTER_TABLES == TRUE
1939     (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10UnknownTableEntryTypeDescriptors,
1940   #else
1941     NULL,
1942   #endif
1943   NULL,
1944   NULL,
1945   InitCacheDisabled,
1946   #if AGESA_ENTRY_INIT_EARLY == TRUE
1947     GetF10EarlyInitOnCoreTable
1948   #else
1949     (PF_GET_EARLY_INIT_TABLE) CommonVoid
1950   #endif
1951 };
1952
1953 // Family 10h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate.
1954 #if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull)
1955   #undef  FAMILY_MMIO_BASE_MASK
1956   #define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull)
1957 #endif
1958
1959 #undef OPT_F10_ID_TABLE
1960 #define OPT_F10_ID_TABLE {0x10, {AMD_FAMILY_10, AMD_F10_UNKNOWN}, F10LogicalIdTable, (sizeof (F10LogicalIdTable) / sizeof (F10LogicalIdTable[0]))},
1961 #define OPT_F10_UNKNOWN_CPU {AMD_FAMILY_10, &cpuF10UnknownServices},
1962
1963 #undef OPT_F10_TABLE
1964 #define OPT_F10_TABLE   OPT_F10_BL_CPU  OPT_F10_DA_CPU  OPT_F10_HY_CPU  OPT_F10_PH_CPU  OPT_F10_RB_CPU  OPT_F10_UNKNOWN_CPU
1965
1966 #if OPTION_G34_SOCKET_SUPPORT == TRUE
1967   extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayG34;
1968   extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayG34;
1969   #define F10_G34_BRANDSTRING1 &F10BrandIdString1ArrayG34,
1970   #define F10_G34_BRANDSTRING2 &F10BrandIdString2ArrayG34,
1971 #else
1972   #define F10_G34_BRANDSTRING1
1973   #define F10_G34_BRANDSTRING2
1974 #endif
1975 #if OPTION_C32_SOCKET_SUPPORT == TRUE
1976   extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayC32;
1977   extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayC32;
1978   #define F10_C32_BRANDSTRING1 &F10BrandIdString1ArrayC32,
1979   #define F10_C32_BRANDSTRING2 &F10BrandIdString2ArrayC32,
1980 #else
1981   #define F10_C32_BRANDSTRING1
1982   #define F10_C32_BRANDSTRING2
1983 #endif
1984 #if OPTION_S1G3_SOCKET_SUPPORT == TRUE
1985   extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g3;
1986   extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g3;
1987   #define F10_S1G3_BRANDSTRING1 &F10BrandIdString1ArrayS1g3,
1988   #define F10_S1G3_BRANDSTRING2 &F10BrandIdString2ArrayS1g3,
1989 #else
1990   #define F10_S1G3_BRANDSTRING1
1991   #define F10_S1G3_BRANDSTRING2
1992 #endif
1993 #if OPTION_S1G4_SOCKET_SUPPORT == TRUE
1994   extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g4;
1995   extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g4;
1996   #define F10_S1G4_BRANDSTRING1 &F10BrandIdString1ArrayS1g4,
1997   #define F10_S1G4_BRANDSTRING2 &F10BrandIdString2ArrayS1g4,
1998 #else
1999   #define F10_S1G4_BRANDSTRING1
2000   #define F10_S1G4_BRANDSTRING2
2001 #endif
2002 #if OPTION_ASB2_SOCKET_SUPPORT == TRUE
2003   extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAsb2;
2004   extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAsb2;
2005   #define F10_ASB2_BRANDSTRING1 &F10BrandIdString1ArrayAsb2,
2006   #define F10_ASB2_BRANDSTRING2 &F10BrandIdString2ArrayAsb2,
2007 #else
2008   #define F10_ASB2_BRANDSTRING1
2009   #define F10_ASB2_BRANDSTRING2
2010 #endif
2011 #if OPTION_AM3_SOCKET_SUPPORT == TRUE
2012   extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAm3;
2013   extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAm3;
2014   #define F10_AM3_BRANDSTRING1 &F10BrandIdString1ArrayAm3,
2015   #define F10_AM3_BRANDSTRING2 &F10BrandIdString2ArrayAm3,
2016 #else
2017   #define F10_AM3_BRANDSTRING1
2018   #define F10_AM3_BRANDSTRING2
2019 #endif
2020
2021 #if BRAND_STRING1 == TRUE
2022   CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString1Tables[] =
2023   {
2024     F10_G34_BRANDSTRING1
2025     F10_C32_BRANDSTRING1
2026     F10_S1G3_BRANDSTRING1
2027     F10_S1G4_BRANDSTRING1
2028     F10_ASB2_BRANDSTRING1
2029     F10_AM3_BRANDSTRING1
2030   };
2031
2032   CONST UINT8 F10BrandIdString1TableCount = (sizeof (F10BrandIdString1Tables) / sizeof (F10BrandIdString1Tables[0]));
2033 #endif
2034
2035 #if BRAND_STRING2 == TRUE
2036   CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString2Tables[] =
2037   {
2038     F10_G34_BRANDSTRING2
2039     F10_C32_BRANDSTRING2
2040     F10_S1G3_BRANDSTRING2
2041     F10_S1G4_BRANDSTRING2
2042     F10_ASB2_BRANDSTRING2
2043     F10_AM3_BRANDSTRING2
2044   };
2045
2046   CONST UINT8 F10BrandIdString2TableCount = (sizeof (F10BrandIdString2Tables) / sizeof (F10BrandIdString2Tables[0]));
2047 #endif
2048
2049 CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F10LogicalIdTable[] =
2050 {
2051   OPT_F10_BL_ID
2052   OPT_F10_DA_ID
2053   OPT_F10_HY_ID
2054   OPT_F10_PH_ID
2055   OPT_F10_RB_ID
2056 };
2057
2058 #endif  // _OPTION_FAMILY_10H_INSTALL_H_