5 * PCIe component definitions.
9 * @xrefitem bom "File Content Label" "Release Content"
12 * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $
16 *****************************************************************************
18 * Copyright (c) 2011, Advanced Micro Devices, Inc.
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43 * ***************************************************************************
50 #pragma pack (push, 1)
52 #ifndef MAX_NUMBER_OF_COMPLEXES
53 #define MAX_NUMBER_OF_COMPLEXES 1
56 #define DESCRIPTOR_ALLOCATED 0x40000000ull
57 #define DESCRIPTOR_VIRTUAL 0x20000000ull
58 #define DESCRIPTOR_COMPLEX 0x08000000ull
59 #define DESCRIPTOR_SILICON 0x04000000ull
60 #define DESCRIPTOR_PCIE_WRAPPER 0x00400000ull
61 #define DESCRIPTOR_DDI_WRAPPER 0x00200000ull
62 #define DESCRIPTOR_PCIE_ENGINE 0x00040000ull
63 #define DESCRIPTOR_DDI_ENGINE 0x00020000ull
64 #define DESCRIPTOR_ALL_WRAPPERS (DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_PCIE_WRAPPER)
65 #define DESCRIPTOR_ALL_ENGINES (DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_PCIE_ENGINE)
67 #define UNUSED_LANE_ID 128
69 #define IS_LAST_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) == 0) : (1==0))
71 // Get lowest PHY lane on engine
72 #define PcieLibGetLoPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) : 0xFF)
73 // Get highest PHY lane on engine
74 #define PcieLibGetHiPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.StartLane : Engine->EngineData.EndLane) : 0xFF)
75 // Get number of lanes on wrapper
76 #define PcieLibWrapperNumberOfLanes(Wrapper) (Wrapper != NULL ? ((UINT8)(Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1)) : 0)
77 // Check if virtual descriptor
78 #define PcieLibIsVirtualDesciptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_VIRTUAL) != 0) : (1==0))
79 // Check if it is allocated descriptor
80 #define PcieLibIsEngineAllocated(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_ALLOCATED) != 0) : (1==0))
81 // Check if it is last descriptor in list
82 #define PcieLibIsLastDescriptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) : (1==1))
83 // Check if descriptor a PCIe engine
84 #define PcieLibIsPcieEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_PCIE_ENGINE) != 0) : (1==0))
85 // Check if descriptor a DDI engine
86 #define PcieLibIsDdiEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_DDI_ENGINE) != 0) : (1==0))
87 // Check if descriptor a DDI wrapper
88 #define PcieLibIsDdiWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_DDI_WRAPPER) != 0) : (1==0))
89 // Check if descriptor a PCIe wrapper
90 #define PcieLibIsPcieWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_PCIE_WRAPPER) != 0) : (1==0))
91 // Check if descriptor a PCIe wrapper
92 #define PcieLibGetNextDescriptor(Descriptor) (Descriptor != NULL ? (((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : ((++Descriptor) != NULL ? Descriptor : NULL)) : NULL)
96 #define LANE_TYPE_PCIE_ALL 0x0001
97 #define LANE_TYPE_PCIE_ALLOCATED 0x0002
98 #define LANE_TYPE_PCIE_ACTIVE 0x0004
99 #define LANE_TYPE_PCIE_SB 0x0008
100 #define LANE_TYPE_PCIE_HOTPLUG 0x0010
102 #define LANE_TYPE_PCIE_LANES 0x000FFF
104 #define LANE_TYPE_DDI_ALL 0x1000
105 #define LANE_TYPE_DDI_ALLOCATED 0x2000
106 #define LANE_TYPE_DDI_ACTIVE 0x4000
108 #define LANE_TYPE_DDI_LANES 0xFFF000
110 #define LANE_TYPE_ALL (LANE_TYPE_PCIE_ALL | LANE_TYPE_DDI_ALL)
111 #define LANE_TYPE_ACTIVE (LANE_TYPE_PCIE_ACTIVE | LANE_TYPE_DDI_ACTIVE)
112 #define LANE_TYPE_ALLOCATED (LANE_TYPE_PCIE_ALLOCATED | LANE_TYPE_DDI_ALLOCATED)
114 //typedef UINT64 PPCIe_ENGINE_CONFIG;
115 //typedef UINT64 PPCIe_WRAPPER_CONFIG;
116 //typedef UINT64 PPCIe_SILICON_CONFIG;
118 #define INIT_STATUS_PCIE_PORT_GEN2_RECOVERY 0x00000001ull
119 #define INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY 0x00000002ull
120 #define INIT_STATUS_PCIE_PORT_TRAINING_FAIL 0x00000004ull
121 #define INIT_STATUS_PCIE_TRAINING_SUCCESS 0x00000008ull
122 #define INIT_STATUS_PCIE_EP_NOT_PRESENT 0x00000010ull
123 #define INIT_STATUS_PCIE_PORT_IN_COMPLIANCE 0x00000020ull
124 #define INIT_STATUS_DDI_ACTIVE 0x00000040ull
125 #define INIT_STATUS_ALLOCATED 0x00000080ull
127 #define PCIE_PORT_GEN_CAP_BOOT 0x00000001
128 #define PCIE_PORT_GEN_CAP_MAX 0x00000002
129 #define PCIE_GLOBAL_GEN_CAP_ALL_PORTS 0x00000010
130 #define PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS 0x00000011
131 #define PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS 0x00000012
133 /// PCIe Link Training State
135 PcieTrainingStandard, ///< Standard training algorithm. Training contained to AmdEarlyInit.
136 ///< PCIe device accessible after AmdEarlyInit complete
137 PcieTrainingDistributed, ///< Distribute training algorithm. Training distributed across AmdEarlyInit/AmdPostInit/AmdS3LateRestore
138 ///< PCIe device accessible after AmdPostInit complete.
139 ///< Algorithm potentially save up to 60ms in S3 resume time by skipping training empty slots.
140 } PCIE_TRAINING_ALGORITHM;
142 /// PCIe port configuration info
144 PCIe_PORT_DATA PortData; ///< Port data
145 UINT16 StartCoreLane; ///< Start Core Lane
146 UINT16 EndCoreLane; ///< End Core lane
147 UINT8 NativeDevNumber; ///< Native PCI device number of the port
148 UINT8 NativeFunNumber; ///< Native PCI function number of the port
149 UINT8 CoreId; ///< PCIe core ID
150 UINT8 PortId; ///< Port id on wrapper
151 PCI_ADDR Address; ///< PCI address of the port
152 BOOLEAN IsSB; ///< Is it NB to SB link?
153 UINT8 State; ///< Training state
154 UINT32 TimeStamp; ///< Time stamp used to during training process
155 UINT8 GfxWrkRetryCount; ///< Number of retry for GFX workaround
158 /// DDI (Digital Display Interface) configuration info
160 PCIe_DDI_DATA DdiData; ///< DDI Data
161 UINT8 DisplayPriorityIndex; ///< Display priority index
162 UINT8 ConnectorId; ///< Connector id determined by enumeration
163 UINT8 DisplayDeviceId; ///< Display device id determined by enumeration
166 /// Engine configuration data
168 UINT32 Flags; /**< Descriptor flags
169 * @li @b Bit31 - last descriptor on wrapper
170 * @li @b Bit30 - Descriptor allocated for PCIe port or DDI
172 VOID *Wrapper; ///< Pointer to parent wrapper
173 PCIe_ENGINE_DATA EngineData; ///< Engine Data
174 UINT32 InitStatus; ///< Initialization Status
175 UINT8 Scratch; ///< Scratch pad
177 PCIe_PORT_CONFIG Port; ///< PCIe port configuration data
178 PCIe_DDI_CONFIG Ddi; ///< DDI configuration data
180 } PCIe_ENGINE_CONFIG;
182 #define PcieEngineGetParentWrapper(mEnginerPtr) ((PCIe_WRAPPER_CONFIG *) (mEnginerPtr->Wrapper))
184 /// Wrapper configuration data
186 UINT32 Flags; /**< Descriptor flags
187 * @li @b Bit31 - last descriptor on silicon
189 UINT8 WrapId; ///< Wrapper ID
190 UINT8 NumberOfPIFs; ///< Number of PIFs on wrapper
191 UINT8 StartPhyLane; ///< Start PHY Lane
192 UINT8 EndPhyLane; ///< End PHY Lane
193 UINT8 StartPcieCoreId; ///< Start PCIe Core ID
194 UINT8 EndPcieCoreId; ///< End PCIe Core ID
196 UINT8 PowerOffUnusedLanes:1; ///< Power Off unused lanes
197 UINT8 PowerOffUnusedPlls:1; ///< Power Off unused Plls
198 UINT8 ClkGating:1; ///< TXCLK gating
199 UINT8 LclkGating:1; ///< LCLK gating
200 UINT8 TxclkGatingPllPowerDown:1; ///< TXCLK clock gating PLL power down
201 UINT8 PllOffInL1:1; ///< PLL off in L1
203 VOID *EngineList; ///< Pointer to Engine list
204 VOID *Silicon; ///< Pointer to parent silicon
205 VOID *FmWrapper; ///< Pointer to family Specific configuration data
206 } PCIe_WRAPPER_CONFIG;
209 #define PcieWrapperGetEngineList(mWrapperPtr) ((PCIe_ENGINE_CONFIG *)(mWrapperPtr->EngineList))
210 #define PcieWrapperGetParentSilicon(mWrapperPtr) ((PCIe_SILICON_CONFIG *)(mWrapperPtr->Silicon))
212 /// Silicon configuration data
214 UINT32 Flags; /**< Descriptor flags
215 * @li @b Bit31 - last descriptor on complex
217 PCI_ADDR Address; ///< PCI address of GNB host bridge
218 VOID *WrapperList; ///< Pointer to wrapper list
219 VOID *FmSilicon; ///< Pointer to family Specific configuration data
220 } PCIe_SILICON_CONFIG;
222 #define PcieSiliconGetWrapperList(mSiliconPtr) ((PCIe_WRAPPER_CONFIG *) (mSiliconPtr->WrapperList))
224 /// Complex configuration data
226 UINT32 Flags; /**< Descriptor flags
227 * @li @b Bit31 - last descriptor on platform
229 UINT8 SocketId; ///< Processor socket ID
230 VOID *SiliconList; ///< Pointer to silicon list
231 } PCIe_COMPLEX_CONFIG;
233 #define PcieComplexGetSiliconList(mComplexPtr) ((PCIe_SILICON_CONFIG *)(UINTN)((mComplexPtr)->SiliconList))
235 /// PCIe platform configuration info
237 AMD_CONFIG_PARAMS *StdHeader; ///< Standard configuration header
238 UINT64 This; ///< base structure Base
239 UINT32 LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
240 UINT32 LinkL0Pooling; ///< Pooling for link to get to L0 in us
241 UINT32 LinkGpioResetAssertionTime; ///< Gpio reset assertion time in us
242 UINT32 LinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us ///
243 UINT8 GfxCardWorkaround; ///< GFX Card Workaround
244 UINT8 PsppPolicy; ///< PSPP policy
245 UINT8 TrainingExitState; ///< State at which training should exit (see PCIE_LINK_TRAINING_STATE)
246 UINT8 TrainingAlgorithm; ///< Training algorithm (see PCIE_TRAINING_ALGORITHM)
247 PCIe_COMPLEX_CONFIG ComplexList[MAX_NUMBER_OF_COMPLEXES]; ///<
248 } PCIe_PLATFORM_CONFIG;
250 /// PCIe Engine Description
252 UINT32 Flags; /**< Descriptor flags
253 * @li @b Bit31 - last descriptor on wrapper
254 * @li @b Bit30 - Descriptor allocated for PCIe port or DDI
256 PCIe_ENGINE_DATA EngineData; ///< Engine Data
257 } PCIe_ENGINE_DESCRIPTOR;
259 /// PCIe Link Training State
261 LinkStateResetAssert, ///< Assert port GPIO reset
262 LinkStateResetDuration, ///< Timeout for reset duration
263 LinkStateResetExit, ///< Deassert port GPIO reset
264 LinkTrainingResetTimeout, ///< Port GPIO reset timeout
265 LinkStateReleaseTraining, ///< Release link training
266 LinkStateDetectPresence, ///< Detect device presence
267 LinkStateDetecting, ///< Detect link training.
268 LinkStateBrokenLane, ///< Check and handle broken lane
269 LinkStateGen2Fail, ///< Check and handle device that fail training if GEN2 capability advertised
270 LinkStateL0, ///< Device trained to L0
271 LinkStateVcoNegotiation, ///< Check VCO negotiation complete
272 LinkStateRetrain, ///< Force retrain link.
273 LinkStateTrainingFail, ///< Link training fail
274 LinkStateTrainingSuccess, ///< Link training success
275 LinkStateGfxWorkaround, ///< GFX workaround
276 LinkStateCompliance, ///< Link in compliance mode
277 LinkStateDeviceNotPresent, ///< Link is not connected
278 LinkStateTrainingCompleted ///< Link training completed
279 } PCIE_LINK_TRAINING_STATE;
281 /// PCIe Port Visibility
283 UnhidePorts, ///< Command to unhide port
284 HidePorts, ///< Command to hide unused ports
285 } PCIE_PORT_VISIBILITY;
288 /// Table Register Entry
290 UINT16 Reg; ///< Address
291 UINT32 Mask; ///< Mask
292 UINT32 Data; ///< Data
293 } PCIE_PORT_REGISTER_ENTRY;
295 /// Table Register Entry
297 UINT32 Reg; ///< Address
298 UINT32 Mask; ///< Mask
299 UINT32 Data; ///< Data
300 } PCIE_HOST_REGISTER_ENTRY;
304 PCI_ADDR DownstreamPort; ///< PCI address of downstream port
305 PCIE_ASPM_TYPE DownstreamAspm ; ///< Downstream Device Aspm
306 PCI_ADDR UpstreamPort; ///< PCI address of upstream port
307 PCIE_ASPM_TYPE UpstreamAspm; ///< Upstream Device Capability
308 PCIE_ASPM_TYPE RequestedAspm; ///< Requested ASPM
311 ///PCIe ASPM Latency Information
313 UINT8 MaxL0sExitLatency; ///< Max L0s exit latency in us
314 UINT8 MaxL1ExitLatency; ///< Max L1 exit latency in us
315 } PCIe_ASPM_LATENCY_INFO;
317 /// PCI address association
319 UINT8 NewDeviceAddress; ///< New PCI address (Device,Fucntion)
320 UINT8 NativeDeviceAddress; ///< Native PCI address (Device,Fucntion)
323 /// The return status for GFX Card Workaround.
325 GFX_WORKAROUND_DEVICE_NOT_READY, ///< GFX Workaround device is not ready.
326 GFX_WORKAROUND_RESET_DEVICE, ///< GFX Workaround device need reset.
327 GFX_WORKAROUND_SUCCESS ///< The service completed normally.
328 } GFX_WORKAROUND_STATUS;
330 /// GFX workaround control
332 GfxWorkaroundDisable, ///< GFX Workaround disabled
333 GfxWorkaroundEnable ///< GFX Workaround enabled
334 } GFX_WORKAROUND_CONTROL;
336 /// PIF lane power state
338 PifPowerStateL0, ///<
339 PifPowerStateLS1, ///<
340 PifPowerStateLS2, ///<
341 PifPowerStateOff = 0x7, ///<
342 } PCIE_PIF_POWER_STATE;
344 /// PIF lane power control
348 } PCIE_PIF_POWER_CONTROL;
354 } PCIE_PLL_RAMPUP_TIME;