5 * ACPI S3 support definitions.
7 * @xrefitem bom "File Content Label" "Release Content"
10 * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
14 *****************************************************************************
16 * Copyright (c) 2011, Advanced Micro Devices, Inc.
17 * All rights reserved.
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41 * ***************************************************************************
49 /*---------------------------------------------------------------------------------------
50 * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
51 *---------------------------------------------------------------------------------------
55 /*---------------------------------------------------------------------------------------
56 * D E F I N I T I O N S A N D M A C R O S
57 *---------------------------------------------------------------------------------------
61 /*---------------------------------------------------------------------------------------
62 * T Y P E D E F S, S T R U C T U R E S, E N U M S
63 *---------------------------------------------------------------------------------------
66 /* Device related definitions */
68 /// Header at the beginning of a context save buffer.
70 UINT16 Version; ///< Version of header
71 UINT16 NumDevices; ///< Number of devices in the list
72 UINT16 RelativeOrMaskOffset; ///< Size of device list + header
73 } DEVICE_BLOCK_HEADER;
77 DEV_TYPE_PCI_PRE_ESR, ///< PCI device before exiting self-refresh
78 DEV_TYPE_PCI, ///< PCI device after exiting self-refresh
79 DEV_TYPE_CPCI_PRE_ESR, ///< 'conditional' PCI device before exiting self-refresh
80 DEV_TYPE_CPCI, ///< 'conditional' PCI device after exiting self-refresh
81 DEV_TYPE_MSR_PRE_ESR, ///< MSR device before exiting self-refresh
82 DEV_TYPE_MSR, ///< MSR device after exiting self-refresh
83 DEV_TYPE_CMSR_PRE_ESR, ///< 'conditional' MSR device before exiting self-refresh
84 DEV_TYPE_CMSR ///< 'conditional' MSR device after exiting self-refresh
87 /// S3 restoration call points
89 INIT_RESUME, ///< AMD_INIT_RESUME
90 S3_LATE_RESTORE ///< AMD_S3LATE_RESTORE
93 /// S3 device common header
95 UINT32 RegisterListID; ///< Unique ID of this device
96 UINT8 Type; ///< Appropriate S3_DEVICE_TYPES type
99 /// S3 PCI device header
101 UINT32 RegisterListID; ///< Unique ID of this device
102 UINT8 Type; ///< DEV_TYPE_PCI / DEV_TYPE_PCI_PRE_ESR
103 UINT8 Node; ///< Zero-based node number
104 } PCI_DEVICE_DESCRIPTOR;
106 /// S3 'conditional' PCI device header
108 UINT32 RegisterListID; ///< Unique ID of this device
109 UINT8 Type; ///< DEV_TYPE_CPCI / DEV_TYPE_CPCI_PRE_ESR
110 UINT8 Node; ///< Zero-based node number
111 UINT8 Mask1; ///< Conditional mask 1
112 UINT8 Mask2; ///< Conditional mask 2
113 } CONDITIONAL_PCI_DEVICE_DESCRIPTOR;
115 /// S3 MSR device header
117 UINT32 RegisterListID; ///< Unique ID of this device
118 UINT8 Type; ///< DEV_TYPE_MSR / DEV_TYPE_MSR_PRE_ESR
119 } MSR_DEVICE_DESCRIPTOR;
121 /// S3 'conditional' MSR device header
123 UINT32 RegisterListID; ///< Unique ID of this device
124 UINT8 Type; ///< DEV_TYPE_CMSR / DEV_TYPE_CMSR_PRE_ESR
125 UINT8 Mask1; ///< Conditional mask 1
126 UINT8 Mask2; ///< Conditional mask 2
127 } CONDITIONAL_MSR_DEVICE_DESCRIPTOR;
129 /* Special case related definitions */
132 * PCI special case save handler
134 * @param[in] AccessWidth 8, 16, or 32 bit wide access
135 * @param[in] Address full PCI address of the register to save
136 * @param[out] Value Value read from the register
137 * @param[in] ConfigPtr AMD standard header config parameter
140 typedef VOID (*PF_S3_SPECIAL_PCI_SAVE) (
141 IN ACCESS_WIDTH AccessWidth,
148 * PCI special case restore handler
150 * @param[in] AccessWidth 8, 16, or 32 bit wide access
151 * @param[in] Address full PCI address of the register to save
152 * @param[in] Value Value to write to the register
153 * @param[in] ConfigPtr AMD standard header config parameter
156 typedef VOID (*PF_S3_SPECIAL_PCI_RESTORE) (
157 IN ACCESS_WIDTH AccessWidth,
158 IN PCI_ADDR PciAddress,
164 * MSR special case save handler
166 * @param[in] MsrAddress Address of model specific register to save
167 * @param[out] Value Value read from the register
168 * @param[in] ConfigPtr AMD standard header config parameter
171 typedef VOID (*PF_S3_SPECIAL_MSR_SAVE) (
172 IN UINT32 MsrAddress,
178 * MSR special case restore handler
180 * @param[in] MsrAddress Address of model specific register to restore
181 * @param[in] Value Value to write to the register
182 * @param[in] ConfigPtr AMD standard header config parameter
185 typedef VOID (*PF_S3_SPECIAL_MSR_RESTORE) (
186 IN UINT32 MsrAddress,
191 /// PCI special case save/restore structure.
193 PF_S3_SPECIAL_PCI_SAVE Save; ///< Save routine
194 PF_S3_SPECIAL_PCI_RESTORE Restore; ///< Restore routine
197 /// MSR special case save/restore structure.
199 PF_S3_SPECIAL_MSR_SAVE Save; ///< Save routine
200 PF_S3_SPECIAL_MSR_RESTORE Restore; ///< Restore routine
203 /* Register related definitions */
204 /// S3 register type bit fields
206 UINT8 SpecialCaseIndex:4; ///< Special Case array index
207 UINT8 RegisterSize:3; ///< For PCI, 1 = byte, 2 = word, else = dword.
208 ///< For MSR, don't care
209 UINT8 SpecialCaseFlag:1; ///< Indicates special case
212 /// S3 PCI register descriptor.
214 S3_REGISTER_TYPE Type; ///< Type[7] = special case flag,
215 ///< Type[6:3] = register size in bytes,
216 ///< Type[2:0] = special case index
217 UINT8 Function; ///< PCI function of the register
218 UINT16 Offset; ///< PCI offset of the register
219 UINT32 AndMask; ///< AND mask to be applied to the value before saving
220 } PCI_REG_DESCRIPTOR;
222 /// S3 'conditional' PCI register descriptor.
224 S3_REGISTER_TYPE Type; ///< Type[7] = special case flag,
225 ///< Type[6:3] = register size in bytes,
226 ///< Type[2:0] = special case index
227 UINT8 Function; ///< PCI function of the register
228 UINT16 Offset; ///< PCI offset of the register
229 UINT32 AndMask; ///< AND mask to be applied to the value before saving
230 UINT8 Mask1; ///< conditional mask 1
231 UINT8 Mask2; ///< conditional mask 2
232 } CONDITIONAL_PCI_REG_DESCRIPTOR;
234 /// S3 MSR register descriptor.
236 S3_REGISTER_TYPE Type; ///< Type[7] = special case flag,
237 ///< Type[6:3] = reserved,
238 ///< Type[2:0] = special case index
239 UINT32 Address; ///< MSR address
240 UINT64 AndMask; ///< AND mask to be applied to the value before saving
241 } MSR_REG_DESCRIPTOR;
243 /// S3 'conditional' MSR register descriptor.
245 S3_REGISTER_TYPE Type; ///< Type[7] = special case flag,
246 ///< Type[6:3] = reserved,
247 ///< Type[2:0] = special case index
248 UINT32 Address; ///< MSR address
249 UINT64 AndMask; ///< AND mask to be applied to the value before saving
250 UINT8 Mask1; ///< conditional mask 1
251 UINT8 Mask2; ///< conditional mask 2
252 } CONDITIONAL_MSR_REG_DESCRIPTOR;
254 /// Common header at the beginning of an S3 register list.
256 UINT16 Version; ///< Version of header
257 UINT16 NumRegisters; ///< Number of registers in the list
258 } REGISTER_BLOCK_HEADER;
260 /// S3 PCI register list header.
262 UINT16 Version; ///< Version of header
263 UINT16 NumRegisters; ///< Number of registers in the list
264 PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor
265 PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers
266 } PCI_REGISTER_BLOCK_HEADER;
268 /// S3 'conditional' PCI register list header.
270 UINT16 Version; ///< Version of header
271 UINT16 NumRegisters; ///< Number of registers in the list
272 CONDITIONAL_PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor
273 PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers
274 } CPCI_REGISTER_BLOCK_HEADER;
276 /// S3 MSR register list header.
278 UINT16 Version; ///< Version of header
279 UINT16 NumRegisters; ///< Number of registers in the list
280 MSR_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor
281 MSR_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers
282 } MSR_REGISTER_BLOCK_HEADER;
284 /// S3 'conditional' MSR register list header.
286 UINT16 Version; ///< Version of header
287 UINT16 NumRegisters; ///< Number of registers in the list
288 CONDITIONAL_MSR_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor
289 MSR_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers
290 } CMSR_REGISTER_BLOCK_HEADER;
292 /// S3 device descriptor pointers for ease of proper pointer advancement.
294 DEVICE_DESCRIPTOR *CommonDeviceHeader; ///< Common header
295 PCI_DEVICE_DESCRIPTOR *PciDevice; ///< PCI header
296 CONDITIONAL_PCI_DEVICE_DESCRIPTOR *CPciDevice; ///< 'conditional' PCI header
297 MSR_DEVICE_DESCRIPTOR *MsrDevice; ///< MSR header
298 CONDITIONAL_MSR_DEVICE_DESCRIPTOR *CMsrDevice; ///< 'conditional' MSR header
299 } DEVICE_DESCRIPTORS;
301 /// S3 register list header pointers for ease of proper pointer advancement.
303 DEVICE_DESCRIPTOR *CommonDeviceHeader; ///< Common header
304 PCI_REGISTER_BLOCK_HEADER *PciRegisters; ///< PCI header
305 CPCI_REGISTER_BLOCK_HEADER *CPciRegisters; ///< 'conditional' PCI header
306 MSR_REGISTER_BLOCK_HEADER *MsrRegisters; ///< MSR header
307 CMSR_REGISTER_BLOCK_HEADER *CMsrRegisters; ///< 'conditional' MSR header
308 } REGISTER_BLOCK_HEADERS;
310 /// S3 Volatile Storage Header
312 UINT32 HeapOffset; ///< Offset to beginning of heap data
313 UINT32 HeapSize; ///< Size of the heap data
314 UINT32 RegisterDataOffset; ///< Offset to beginning of raw save data
315 UINT32 RegisterDataSize; ///< Size of raw save data
316 } S3_VOLATILE_STORAGE_HEADER;
319 /*---------------------------------------------------------------------------------------
320 * F U N C T I O N P R O T O T Y P E
321 *---------------------------------------------------------------------------------------
324 GetWorstCaseContextSize (
325 IN DEVICE_BLOCK_HEADER *DeviceList,
326 IN CALL_POINTS CallPoint,
327 IN AMD_CONFIG_PARAMS *StdHeader
331 SaveDeviceListContext (
332 IN DEVICE_BLOCK_HEADER *DeviceList,
334 IN CALL_POINTS CallPoint,
335 OUT UINT32 *ActualBufferSize,
336 IN AMD_CONFIG_PARAMS *StdHeader
340 RestorePreESRContext (
341 OUT VOID **OrMaskPtr,
343 IN CALL_POINTS CallPoint,
344 IN AMD_CONFIG_PARAMS *StdHeader
348 RestorePostESRContext (
351 IN CALL_POINTS CallPoint,
352 IN AMD_CONFIG_PARAMS *StdHeader
356 AmdS3ParamsInitializer (
357 OUT AMD_S3_PARAMS *S3Params
361 GetNonMemoryRelatedDeviceList (
362 OUT DEVICE_BLOCK_HEADER **NonMemoryRelatedDeviceList,
363 IN AMD_CONFIG_PARAMS *StdHeader
367 S3GetPciDeviceRegisterList (
368 IN PCI_DEVICE_DESCRIPTOR *Device,
369 OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr,
370 IN AMD_CONFIG_PARAMS *StdHeader
374 S3GetCPciDeviceRegisterList (
375 IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
376 OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr,
377 IN AMD_CONFIG_PARAMS *StdHeader
381 S3GetMsrDeviceRegisterList (
382 IN MSR_DEVICE_DESCRIPTOR *Device,
383 OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr,
384 IN AMD_CONFIG_PARAMS *StdHeader
388 S3GetCMsrDeviceRegisterList (
389 IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
390 OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr,
391 IN AMD_CONFIG_PARAMS *StdHeader