src/vendorcode/amd/agesa/f14/AGESA.h

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * Agesa structures and definitions
   6  *
   7  * Contains AMD AGESA core interface
   8  *
   9  * @xrefitem bom "File Content Label" "Release Content"
  10  * @e project:      AGESA
  11  * @e sub-project:  Include
  12  * @e \$Revision: 47417 $   @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $
  13  */
  14 /*
  15  *****************************************************************************
  16  *
  17  * Copyright (c) 2011, Advanced Micro Devices, Inc.
  18  * All rights reserved.
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions are met:
  22  *     * Redistributions of source code must retain the above copyright
  23  *       notice, this list of conditions and the following disclaimer.
  24  *     * Redistributions in binary form must reproduce the above copyright
  25  *       notice, this list of conditions and the following disclaimer in the
  26  *       documentation and/or other materials provided with the distribution.
  27  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  28  *       its contributors may be used to endorse or promote products derived
  29  *       from this software without specific prior written permission.
  30  *
  31  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  32  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  33  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  34  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  35  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  36  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  37  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  38  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  39  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  40  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  41  *
  42  * ***************************************************************************
  43  *
  44  */
  45
  46
  47 #ifndef _AGESA_H_
  48 #define _AGESA_H_
  49
  50 #include  "Porting.h"
  51 #include  "AMD.h"
  52
  53 //
  54 //
  55 // AGESA Types and Definitions
  56 //
  57 //
  58
  59 // AGESA BASIC CALLOUTS
  60 #define AGESA_MEM_RELEASE              0x00028000
  61
  62 // AGESA ADVANCED CALLOUTS, Processor
  63 #define AGESA_CHECK_UMA                0x00028100
  64 #define AGESA_DO_RESET                 0x00028101
  65 #define AGESA_ALLOCATE_BUFFER          0x00028102
  66 #define AGESA_DEALLOCATE_BUFFER        0x00028103
  67 #define AGESA_LOCATE_BUFFER            0x00028104
  68 #define AGESA_RUNFUNC_ONAP             0x00028105
  69
  70 // AGESA ADVANCED CALLOUTS, HyperTransport
  71
  72 // AGESA ADVANCED CALLOUTS, Memory
  73 #define AGESA_READ_SPD                 0x00028140
  74 #define AGESA_HOOKBEFORE_DRAM_INIT     0x00028141
  75 #define AGESA_HOOKBEFORE_DQS_TRAINING  0x00028142
  76 #define AGESA_READ_SPD_RECOVERY        0x00028143
  77 #define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144
  78 #define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY     0x00028145
  79
  80 // AGESA IDS CALLOUTS
  81 #define AGESA_GET_IDS_INIT_DATA       0x00028200
  82
  83 // AGESA GNB CALLOUTS
  84 #define AGESA_GNB_PCIE_SLOT_RESET      0x00028301
  85
  86 //------------------------------------------------------------------------
  87 //
  88 // HyperTransport Interface
  89
  90
  91
  92 //-----------------------------------------------------------------------------
  93 //                         HT DEFINITIONS AND MACROS
  94 //
  95 //-----------------------------------------------------------------------------
  96
  97
  98 // Width equates for call backs
  99 #define HT_WIDTH_8_BITS              8                          ///< Specifies 8 bit, or up to 8 bit widths.
 100 #define HT_WIDTH_16_BITS             16                         ///< Specifies 16 bit, or up to 16 bit widths.
 101 #define HT_WIDTH_4_BITS              4
 102 #define HT_WIDTH_2_BITS              2
 103 #define HT_WIDTH_NO_LIMIT            HT_WIDTH_16_BITS
 104
 105 // Frequency Limit equates for call backs which take a frequency supported mask.
 106 #define HT_FREQUENCY_LIMIT_200M      1                           ///< Specifies a limit of no more than 200 MHz HT frequency.
 107 #define HT_FREQUENCY_LIMIT_400M      7                           ///< Specifies a limit of no more than 400 MHz HT frequency.
 108 #define HT_FREQUENCY_LIMIT_600M      0x1F                        ///< Specifies a limit of no more than 600 MHz HT frequency.
 109 #define HT_FREQUENCY_LIMIT_800M      0x3F                        ///< Specifies a limit of no more than 800 MHz HT frequency.
 110 #define HT_FREQUENCY_LIMIT_1000M     0x7F                        ///< Specifies a limit of no more than 1000 MHz HT frequency.
 111 #define HT_FREQUENCY_LIMIT_HT1_ONLY  0x7F                        ///< Specifies a limit of no more than 1000 MHz HT frequency.
 112 #define HT_FREQUENCY_LIMIT_1200M     0xFF                        ///< Specifies a limit of no more than 1200 MHz HT frequency.
 113 #define HT_FREQUENCY_LIMIT_1400M     0x1FF                       ///< Specifies a limit of no more than 1400 MHz HT frequency.
 114 #define HT_FREQUENCY_LIMIT_1600M     0x3FF                       ///< Specifies a limit of no more than 1600 MHz HT frequency.
 115 #define HT_FREQUENCY_LIMIT_1800M     0x7FF                       ///< Specifies a limit of no more than 1800 MHz HT frequency.
 116 #define HT_FREQUENCY_LIMIT_2000M     0xFFF                       ///< Specifies a limit of no more than 2000 MHz HT frequency.
 117 #define HT_FREQUENCY_LIMIT_2200M     0x1FFF                      ///< Specifies a limit of no more than 2200 MHz HT frequency.
 118 #define HT_FREQUENCY_LIMIT_2400M     0x3FFF                      ///< Specifies a limit of no more than 2400 MHz HT frequency.
 119 #define HT_FREQUENCY_LIMIT_2600M     0x7FFF                      ///< Specifies a limit of no more than 2600 MHz HT frequency.
 120 #define HT_FREQUENCY_LIMIT_2800M     0x27FFF                     ///< Specifies a limit of no more than 2800 MHz HT frequency.
 121 #define HT_FREQUENCY_LIMIT_3000M     0x67FFF                     ///< Specifies a limit of no more than 3000 MHz HT frequency.
 122 #define HT_FREQUENCY_LIMIT_3200M     0xE7FFF                     ///< Specifies a limit of no more than 3200 MHz HT frequency.
 123 #define HT_FREQUENCY_LIMIT_3600M     0x1E7FFF
 124 #define HT_FREQUENCY_LIMIT_MAX       HT_FREQUENCY_LIMIT_3600M
 125 #define HT_FREQUENCY_NO_LIMIT        0xFFFFFFFF                  ///< Specifies a no limit of HT frequency.
 126
 127 // Unit ID Clumping special values
 128 #define HT_CLUMPING_DISABLE          0x00000000
 129 #define HT_CLUMPING_NO_LIMIT         0xFFFFFFFF
 130
 131 #define HT_LIST_TERMINAL             0xFF             ///< End of list.
 132 #define HT_LIST_MATCH_ANY            0xFE             ///< Match Any value, used for Sockets, Links, IO Chain Depth.
 133 #define HT_LIST_MATCH_INTERNAL_LINK  0xFD             ///< Match all of the internal links.
 134
 135 // Event Notify definitions
 136
 137 // Event definitions.
 138
 139 // Coherent subfunction events
 140 #define HT_EVENT_COH_EVENTS             0x10001000
 141 #define HT_EVENT_COH_NO_TOPOLOGY        0x10011000    ///< See ::HT_EVENT_DATA_COH_NO_TOPOLOGY.
 142 #define HT_EVENT_COH_OBSOLETE000        0x10021000    //   No longer used.
 143 #define HT_EVENT_COH_PROCESSOR_TYPE_MIX 0x10031000    ///< See ::HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX.
 144 #define HT_EVENT_COH_NODE_DISCOVERED    0x10041000    ///< See ::HT_EVENT_COH_NODE_DISCOVERED.
 145 #define HT_EVENT_COH_MPCAP_MISMATCH     0x10051000    ///< See ::HT_EVENT_COH_MPCAP_MISMATCH.
 146
 147 // Non-coherent subfunction events
 148 #define HT_EVENT_NCOH_EVENTS         0x10002000
 149 #define HT_EVENT_NCOH_BUID_EXCEED    0x10012000       ///< See ::HT_EVENT_DATA_NCOH_BUID_EXCEED
 150 #define HT_EVENT_NCOH_OBSOLETE000    0x10022000       //   No longer used.
 151 #define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x10032000       ///< See ::HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED.
 152 #define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x10042000       ///< See ::HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED.
 153 #define HT_EVENT_NCOH_DEVICE_FAILED  0x10052000       ///< See ::HT_EVENT_DATA_NCOH_DEVICE_FAILED
 154 #define HT_EVENT_NCOH_AUTO_DEPTH     0x10062000       ///< See ::HT_EVENT_NCOH_AUTO_DEPTH
 155
 156 // Optimization subfunction events
 157 #define HT_EVENT_OPT_EVENTS               0x10003000
 158 #define HT_EVENT_OPT_REQUIRED_CAP_RETRY   0x10013000  ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
 159 #define HT_EVENT_OPT_REQUIRED_CAP_GEN3    0x10023000  ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
 160 #define HT_EVENT_OPT_UNUSED_LINKS         0x10033000  ///< See ::HT_EVENT_DATA_OPT_UNUSED_LINKS.
 161 #define HT_EVENT_OPT_LINK_PAIR_EXCEED     0x10043000  ///< See ::HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED.
 162
 163 // HW Fault events
 164 #define HT_EVENT_HW_EVENTS           0x10004000
 165 #define HT_EVENT_HW_SYNCFLOOD        0x10014000       ///< See ::HT_EVENT_DATA_HW_SYNCFLOOD.
 166 #define HT_EVENT_HW_HTCRC            0x10024000       ///< See ::HT_EVENT_DATA_HW_HT_CRC.
 167
 168 // The Recovery HT component uses 0x10005000 for events.
 169 // For consistency, we avoid that range here.
 170
 171 #define HT_MAX_NC_BUIDS 32
 172 //----------------------------------------------------------------------------
 173 //                         HT TYPEDEFS, STRUCTURES, ENUMS
 174 //
 175 //----------------------------------------------------------------------------
 176
 177 /// Specify the state redundant links are to be left in after match.
 178 ///
 179 /// After matching a link for IGNORE_LINK or SKIP_REGANG, the link may be left alone,
 180 /// or powered off.
 181
 182 typedef enum {
 183   MATCHED,                               ///< The link matches the requested customization.
 184                                          ///< When used with IGNORE_LINK,
 185                                          ///< this will generally require other software to initialize the link.
 186                                          ///< When used with SKIP_REGANG,
 187                                          ///< the two unganged links will be available for distribution.
 188
 189   POWERED_OFF,                           ///< Power the link off.  Support may vary based on processor model.
 190                                          ///< Power Off is only supported for coherent links.
 191                                          ///< Link power off may occur at a warm reset rather than immediately.
 192                                          ///< When used with SKIP_REGANG, the paired sublink is powered off, not the matching link.
 193
 194   UNMATCHED,                             ///< The link should be processed according to normal defaults.
 195                                          ///< Effectively, the link does not match the requested customization.
 196                                          ///< This can be used to exclude links from a following match any.
 197
 198   MaxFinalLinkState                      ///< Not a final link state, use for limit checking.
 199 } FINAL_LINK_STATE;
 200
 201 /// Swap a device from its current id to a new one.
 202
 203 typedef struct {
 204   IN       UINT8 FromId;                 ///< The device responding to FromId,
 205   IN       UINT8 ToId;                   ///< will be moved to ToId.
 206 } BUID_SWAP_ITEM;
 207
 208
 209 /// Each Non-coherent chain may have a list of device swaps.  After performing the swaps,
 210 /// the final in order list of device ids is provided. (There can be more swaps than devices.)
 211 /// The unused entries in both are filled with 0xFF.
 212
 213 typedef struct {
 214   IN       BUID_SWAP_ITEM Swaps[HT_MAX_NC_BUIDS]; ///< The BUID Swaps to perform
 215   IN       UINT8 FinalIds[HT_MAX_NC_BUIDS];       ///< The ordered final BUIDs, resulting from the swaps
 216 } BUID_SWAP_LIST;
 217
 218
 219 /// Control Manual Initialization of Non-Coherent Chains
 220 ///
 221 /// This interface is checked every time a non-coherent chain is
 222 /// processed.  BUID assignment may be controlled explicitly on a
 223 /// non-coherent chain. Provide a swap list.  Swaps controls the
 224 /// BUID assignment and FinalIds provides the device to device
 225 /// Linking.  Device orientation can be detected automatically, or
 226 /// explicitly.  See interface documentation for more details.
 227 ///
 228 /// If a manual swap list is not supplied,
 229 /// automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
 230 /// based on each device's unit count.
 231
 232 typedef struct {
 233   // Match fields
 234   IN       UINT8 Socket;                       ///< The Socket on which this chain is located
 235   IN       UINT8 Link;                         ///< The Link on the host for this chain
 236   // Override fields
 237   IN       BUID_SWAP_LIST SwapList;            ///< The swap list
 238 } MANUAL_BUID_SWAP_LIST;
 239
 240
 241 /// Override options for DEVICE_CAP_OVERRIDE.
 242 ///
 243 /// Specify which override actions should be performed.  For Checks, 1 means to check the item
 244 /// and 0 means to skip the check.  For the override options, 1 means to apply the override and
 245 /// 0 means to ignore the override.
 246
 247 typedef struct {
 248   IN       UINT32  IsCheckDevVenId:1;     ///< Check Match on Device/Vendor id
 249   IN       UINT32  IsCheckRevision:1;     ///< Check Match on device Revision
 250   IN       UINT32  IsOverrideWidthIn:1;   ///< Override Width In
 251   IN       UINT32  IsOverrideWidthOut:1;  ///< Override Width Out
 252   IN       UINT32  IsOverrideFreq:1;      ///< Override Frequency
 253   IN       UINT32  IsOverrideClumping:1;  ///< Override Clumping
 254   IN       UINT32  IsDoCallout:1;         ///< Make the optional callout
 255 } DEVICE_CAP_OVERRIDE_OPTIONS;
 256
 257 /// Override capabilities of a device.
 258 ///
 259 /// This interface is checked once for every Link on every IO device.
 260 /// Provide the width and frequency capability if needed for this device.
 261 /// This is used along with device capabilities, the limit interfaces, and northbridge
 262 /// limits to compute the default settings.  The components of the device's PCI config
 263 /// address are provided, so its settings can be consulted if need be.
 264 /// The optional callout is a catch all.
 265
 266 typedef struct {
 267   // Match fields
 268   IN       UINT8 HostSocket;           ///< The Socket on which this chain is located.
 269   IN       UINT8 HostLink;             ///< The Link on the host for this chain.
 270   IN       UINT8 Depth;                ///< The Depth in the I/O chain from the Host.
 271   IN       UINT32 DevVenId;            ///< The Device's PCI Vendor + Device ID (offset 0x00).
 272   IN       UINT8 Revision;             ///< The Device's PCI Revision field (offset 0x08).
 273   IN       UINT8 Link;                 ///< The Device's Link number (0 or 1).
 274   IN       DEVICE_CAP_OVERRIDE_OPTIONS Options; ///< The options for this device override.
 275   // Override fields
 276   IN       UINT8 LinkWidthIn;          ///< modify to change the Link Width In.
 277   IN       UINT8 LinkWidthOut;         ///< modify to change the Link Width Out.
 278   IN       UINT32 FreqCap;             ///< modify to change the Link's frequency capability.
 279   IN       UINT32 Clumping;            ///< modify to change Unit ID clumping support.
 280   IN       CALLOUT_ENTRY Callout;      ///< optional call for really complex cases, or NULL.
 281 } DEVICE_CAP_OVERRIDE;
 282
 283 /// Callout param struct for override capabilities of a device.
 284 ///
 285 /// If the optional callout is implemented this param struct is passed to it.
 286
 287 typedef struct {
 288   IN       AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
 289   // Match fields
 290   IN       UINT8 HostSocket;           ///< The Socket on which this chain is located.
 291   IN       UINT8 HostLink;             ///< The Link on the host for this chain.
 292   IN       UINT8 Depth;                ///< The Depth in the I/O chain from the Host.
 293   IN       UINT32 DevVenId;            ///< The Device's PCI Vendor + Device ID (offset 0x00).
 294   IN       UINT8 Revision;             ///< The Device's PCI Revision field (offset 0x08).
 295   IN       UINT8 Link;                 ///< The Device's Link number (0 or 1).
 296   IN       PCI_ADDR PciAddress;        ///< The Device's PCI Address.
 297   // Override fields
 298      OUT   UINT8 *LinkWidthIn;          ///< modify to change the Link Width In.
 299      OUT   UINT8 *LinkWidthOut;         ///< modify to change the Link Width Out.
 300      OUT   UINT32 *FreqCap;             ///< modify to change the Link's frequency capability.
 301      OUT   UINT32 *Clumping;            ///< modify to change Unit ID clumping support.
 302 } DEVICE_CAP_CALLOUT_PARAMS;
 303
 304 ///  Limits for CPU to CPU Links.
 305 ///
 306 ///  For each coherent connection this interface is checked once.
 307 ///  Provide the frequency and width if needed for this Link (usually based on board
 308 ///  restriction).  This is used with CPU device capabilities and northbridge limits
 309 ///  to compute the default settings.
 310
 311 typedef struct {
 312   // Match fields
 313   IN       UINT8 SocketA;                ///< One Socket on which this Link is located
 314   IN       UINT8 LinkA;                  ///< The Link on this Node
 315   IN       UINT8 SocketB;                ///< The other Socket on which this Link is located
 316   IN       UINT8 LinkB;                  ///< The Link on that Node
 317   // Limit fields
 318   IN       UINT8 ABLinkWidthLimit;       ///< modify to change the Link Width A->B
 319   IN       UINT8 BALinkWidthLimit;       ///< modify to change the Link Width B-<A
 320   IN       UINT32 PcbFreqCap;            ///< modify to change the Link's frequency capability
 321 } CPU_TO_CPU_PCB_LIMITS;
 322
 323 ///  Get limits for non-coherent Links.
 324 ///
 325 /// For each non-coherent connection this interface is checked once.
 326 /// Provide the frequency and width if needed for this Link (usually based on board
 327 /// restriction).  This is used with device capabilities, device overrides, and northbridge limits
 328 /// to compute the default settings.
 329 ///
 330 typedef struct {
 331   // Match fields
 332   IN       UINT8 HostSocket;               ///< The Socket on which this Link is located
 333   IN       UINT8 HostLink;                 ///< The Link about to be initialized
 334   IN       UINT8 Depth;                    ///< The Depth in the I/O chain from the Host
 335   // Limit fields
 336   IN       UINT8 DownstreamLinkWidthLimit; ///< modify to change the Link Width going away from processor
 337   IN       UINT8 UpstreamLinkWidthLimit;   ///< modify to change the Link Width moving toward processor
 338   IN       UINT32 PcbFreqCap;              ///< modify to change the Link's frequency capability
 339 } IO_PCB_LIMITS;
 340
 341 ///  Manually control bus number assignment.
 342 ///
 343 /// This interface is checked every time a non-coherent chain is processed.
 344 /// If a system can not use the auto Bus numbering feature for non-coherent chain bus
 345 /// assignments, this interface can provide explicit control.  For each chain, provide
 346 /// the bus number range to use.
 347
 348 typedef struct {
 349   // Match fields
 350   IN       UINT8 Socket;                 ///< The Socket on which this chain is located
 351   IN       UINT8 Link;                   ///< The Link on the host for this chain
 352   // Override fields
 353   IN       UINT8 SecBus;                 ///< Secondary Bus number for this non-coherent chain
 354   IN       UINT8 SubBus;                 ///< Subordinate Bus number
 355 } OVERRIDE_BUS_NUMBERS;
 356
 357
 358 ///  Ignore a Link.
 359 ///
 360 ///  This interface is checked every time a coherent Link is found and then every
 361 ///  time a non-coherent Link from a CPU is found.
 362 ///  Any coherent or non-coherent Link from a CPU can be ignored and not used
 363 ///  for discovery or initialization.  Useful for connection based systems.
 364 ///  (Note: not checked for IO device to IO Device Links.)
 365 ///  (Note: not usable for internal links (MCM processors).)
 366
 367 typedef struct {
 368   // Match fields
 369   IN       UINT8 Socket;                 ///< The Socket on which this Link is located
 370   IN       UINT8 Link;                   ///< The Link about to be initialized
 371   // Customization fields
 372   IN       FINAL_LINK_STATE LinkState;   ///< The link may be left unitialized, or powered off.
 373 } IGNORE_LINK;
 374
 375
 376 ///  Skip reganging of subLinks.
 377 ///
 378 ///  This interface is checked whenever two subLinks are both connected to the same CPUs.
 379 ///  Normally, unganged sublinks between the same two CPUs are reganged.
 380 ///  Provide a matching structure to leave the Links unganged.
 381
 382 typedef struct {
 383   // Match fields
 384   IN       UINT8 SocketA;                ///< One Socket on which this Link is located
 385   IN       UINT8 LinkA;                  ///< The Link on this Node
 386   IN       UINT8 SocketB;                ///< The other Socket on which this Link is located
 387   IN       UINT8 LinkB;                  ///< The Link on that Node
 388   // Customization fields
 389   IN       FINAL_LINK_STATE LinkState;   ///< The paired sublink may be active, or powered off.
 390 } SKIP_REGANG;
 391
 392 ///  The System Socket layout, which sockets are physically connected.
 393 ///
 394 ///  The hardware method for Socket naming is preferred.  Use this software method only
 395 ///  if required.
 396
 397 typedef struct {
 398   IN       UINT8 CurrentSocket;    ///< The socket from which this connection originates.
 399   IN       UINT8 CurrentLink;      ///< The Link from the source socket connects to another socket.
 400   IN       UINT8 TargetSocket;     ///< The target socket which is connected on that link.
 401 } SYSTEM_PHYSICAL_SOCKET_MAP;
 402
 403 //----------------------------------------------------------------------------
 404 ///
 405 /// This is the input structure for AmdHtInitialize.
 406 ///
 407 typedef struct {
 408   // Basic level customization
 409   IN       UINT8 AutoBusStart;           ///< For automatic bus number assignment, starting bus number - usually zero.
 410                                          ///< @BldCfgItem{BLDCFG_STARTING_BUSNUM}
 411   IN       UINT8 AutoBusMax;             ///< For automatic bus number assignment, do not assign above max.
 412                                          ///< @BldCfgItem{BLDCFG_MAXIMUM_BUSNUM}
 413   IN       UINT8 AutoBusIncrement;       ///< For automatic bus number assignment, each chain gets this many busses.
 414                                          ///< @BldCfgItem{BLDCFG_ALLOCATED_BUSNUMS}
 415
 416   // Advanced Level Customization
 417   IN       MANUAL_BUID_SWAP_LIST *ManualBuidSwapList;     ///< Provide Manual Swap List, if any.
 418                                                           ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
 419   IN       DEVICE_CAP_OVERRIDE *DeviceCapOverrideList;    ///< Provide Device Overrides, if any.
 420                                                           ///< @BldCfgItem{BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST}
 421   IN       CPU_TO_CPU_PCB_LIMITS *CpuToCpuPcbLimitsList;   ///< Provide CPU PCB Limits, if any.
 422                                                           ///< @BldCfgItem{BLDCFG_HTFABRIC_LIMITS_LIST}.
 423                                                           ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
 424   IN       IO_PCB_LIMITS *IoPcbLimitsList;                ///< Provide IO PCB Limits, if any.
 425                                                           ///< @BldCfgItem{BLDCFG_HTCHAIN_LIMITS_LIST}.
 426                                                           ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
 427   IN       OVERRIDE_BUS_NUMBERS *OverrideBusNumbersList;  ///< Provide manual Bus Number assignment, if any.
 428                                                           ///< Use either auto bus numbering or override bus
 429                                                           ///< numbers, not both.
 430                                                           ///< @BldCfgItem{BLDCFG_BUS_NUMBERS_LIST}
 431
 432   IN       IGNORE_LINK *IgnoreLinkList;                   ///< Provide links to ignore, if any.
 433                                                           ///< @BldCfgItem{BLDCFG_IGNORE_LINK_LIST}
 434   IN       SKIP_REGANG *SkipRegangList;                   ///< Provide links to remain unganged, if any.
 435                                                           ///< @BldCfgItem{BLDCFG_LINK_SKIP_REGANG_LIST}
 436                                                           ///< @n @e Examples: See @ref PerfPerWattHt "Performance-per-watt Optimization".
 437
 438   // Expert Level Customization
 439   IN       UINT8 **Topolist;                         ///< Use this topology list in addition to the built in, if not NULL.
 440                                                      ///< @BldCfgItem{BLDCFG_ADDITIONAL_TOPOLOGIES_LIST}
 441   IN       SYSTEM_PHYSICAL_SOCKET_MAP *SystemPhysicalSocketMap;
 442                                                      ///< The hardware socket naming method is preferred,
 443                                                      ///<  If it can't be used, this provides a software method.
 444                                                      ///< @BldCfgItem{BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP}
 445 } AMD_HT_INTERFACE;
 446
 447 //-----------------------------------------------------------------------------
 448 //
 449 // HT Recovery Interface
 450 //
 451
 452
 453 /*-----------------------------------------------------------------------------
 454  *              HT Recovery DEFINITIONS AND MACROS
 455  *
 456  *-----------------------------------------------------------------------------
 457  */
 458
 459 // BBHT subfunction events
 460 #define HT_EVENT_BB_EVENTS         0x10005000
 461 #define HT_EVENT_BB_BUID_EXCEED    0x10015000
 462 #define HT_EVENT_BB_DEVICE_FAILED  0x10055000
 463 #define HT_EVENT_BB_AUTO_DEPTH     0x10065000
 464
 465 /*----------------------------------------------------------------------------
 466  *                      HT Recovery   TYPEDEFS, STRUCTURES, ENUMS
 467  *
 468  *----------------------------------------------------------------------------
 469  */
 470
 471
 472 /// The Interface structure to Recovery HT.
 473
 474 typedef struct {
 475   IN       MANUAL_BUID_SWAP_LIST *ManualBuidSwapList;  ///< Option to manually control SB link init
 476                                                        ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
 477      OUT   UINT32 Depth;           ///< If auto init was used this is set to the depth of the chain,
 478                                    ///< else, for manual init unmodified.
 479 } AMD_HT_RESET_INTERFACE;
 480
 481 /*----------------------------------------------------------------------------
 482  *   CPU Feature related info
 483  *----------------------------------------------------------------------------
 484  */
 485
 486 /// Build Configuration values for BLDCFG_PLATFORM_C1E_MODE
 487 typedef enum {
 488   C1eModeDisabled                   = 0,   ///< Disabled
 489   C1eModeHardware                   = 1,   ///< Hardware method
 490   C1eModeMsgBased                   = 2,   ///< Message-based method
 491   C1eModeSoftwareDeprecated         = 3,   ///< Deprecated software SMI method.
 492                                            ///< Refer to "Addendum\Examples\C1eSMMHandler.asm" for
 493                                            ///< example host BIOS SMM Handler implementation
 494   C1eModeHardwareSoftwareDeprecated = 4,   ///< Hardware or deprecated software SMI method
 495   MaxC1eMode                        = 5    ///< Not a valid value, used for verifying input
 496 } PLATFORM_C1E_MODES;
 497
 498 /// Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
 499 typedef enum {
 500   CStateModeDisabled = 0,           ///< Disabled
 501   CStateModeC6       = 1,           ///< C6 State
 502   MaxCStateMode      = 2            ///< Not a valid value, used for verifying input
 503 } PLATFORM_CSTATE_MODES;
 504
 505 /// Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
 506 typedef enum {
 507   CpbModeAuto     = 0,           ///< Auto
 508   CpbModeDisabled = 1,           ///< Disabled
 509   MaxCpbMode      = 2            ///< Not a valid value, used for verifying input
 510 } PLATFORM_CPB_MODES;
 511
 512 /*----------------------------------------------------------------------------
 513  *   GNB PCIe configuration info
 514  *----------------------------------------------------------------------------
 515  */
 516
 517 // Event definitions
 518
 519
 520 #define GNB_EVENT_INVALID_CONFIGURATION               0x20010000   // User configuration invalid
 521 #define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001   // Requested lane allocation for PCIe port can not be supported
 522 #define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION     0x20010002   // Requested incorrect PCIe port device address
 523 #define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION      0x20010003   // Incorrect parameter in DDI link configuration
 524 #define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION    0x20010004   // Invalid with for PCIe port or DDI link
 525 #define GNB_EVENT_INVALID_LANES_CONFIGURATION         0x20010005   // Lane double subscribe lanes
 526 #define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION  0x20010006   // Requested lane allocation for DDI link(s) can not be supported
 527 #define GNB_EVENT_LINK_TRAINING_FAIL                  0x20020000   // PCIe Link training fail
 528 #define GNB_EVENT_BROKEN_LANE_RECOVERY                0x20030000   // Broken lane workaround applied to recover link training
 529 #define GNB_EVENT_GEN2_SUPPORT_RECOVERY               0x20040000   // Scale back to GEN1 to recover link training
 530
 531
 532 #define DESCRIPTOR_TERMINATE_LIST           0x80000000ull
 533
 534 /// PCIe port misc extended controls
 535 typedef struct  {
 536   IN      UINT8                     LinkComplianceMode :1;  ///< Force port into compliance mode (device will not be trained, port output compliance pattern)
 537   IN      UINT8                     LinkSafeMode       :2;  /**< Safe mode PCIe capability. (Parameter may limit PCIe speed requested through PCIe_PORT_DATA::LinkSpeedCapability)
 538                                                              *  @li @b 0 - port can advertize muximum supported capability
 539                                                              *  @li @b 1 - port limit advertized capability and speed to PCIe Gen1
 540                                                              */
 541 } PCIe_PORT_MISC_CONTROL;
 542
 543
 544 /// PCIe port configuration data
 545 typedef struct  {
 546   IN       UINT8                   PortPresent;              ///< Enable PCIe port for initialization.
 547   IN       UINT8                   ChannelType;              /**< Channel type.
 548                                                                *  @li @b 0 - "lowLoss",
 549                                                                *  @li @b 1 - "highLoss",
 550                                                                *  @li @b 2 - "mob0db",
 551                                                                *  @li @b 3 - "mob3db",
 552                                                                *  @li @b 4 - "extnd6db"
 553                                                                *  @li @b 5 - "extnd8db"
 554                                                                */
 555   IN       UINT8                   DeviceNumber;             /**< PCI Device number for port.
 556                                                                *   @li @b 0 - Native port device number
 557                                                                *   @li @b N - Port device number (See available configurations @ref F12LaneConfigurations "Family 0x12",  @ref F14LaneConfigurations "Family 0x14")
 558                                                                */
 559   IN       UINT8                   FunctionNumber;           ///< Reserved for future use
 560   IN       UINT8                   LinkSpeedCapability;      /**< PCIe link speed/
 561                                                                *  @li @b 0 - Maximum supported by silicon
 562                                                                *  @li @b 1 - Gen1
 563                                                                *  @li @b 2 - Gen2
 564                                                                *  @li @b 3 - Gen3
 565                                                                */
 566   IN       UINT8                   LinkAspm;                 /**< ASPM control. (see AgesaPcieLinkAspm for additional option to control ASPM)
 567                                                                *  @li @b 0 - Disabled
 568                                                                *  @li @b 1 - L0s only
 569                                                                *  @li @b 2 - L1 only
 570                                                                *  @li @b 3 - L0s and L1
 571                                                                */
 572   IN       UINT8                   LinkHotplug;              /**< Hotplug control.
 573                                                                *  @li @b 0 - Disabled
 574                                                                *  @li @b 1 - Basic
 575                                                                *  @li @b 2 - Server
 576                                                                *  @li @b 3 - Enhanced
 577                                                                */
 578   IN       UINT8                   ResetId;                  /**< Arbitrary number greater than 0 assigned by platform firmware for GPIO
 579                                                                *   identification which control reset for given port.
 580                                                                *   Each port with unique GPIO should have unique ResetId assigned.
 581                                                                *   All ports use same GPIO to control reset should have same ResetId assigned.
 582                                                                *   see AgesaPcieSlotResetContol.
 583                                                                */
 584   IN       PCIe_PORT_MISC_CONTROL  MiscControls;             ///< Misc extended controls
 585 } PCIe_PORT_DATA;
 586
 587 /// DDI channel lane mapping
 588 typedef struct {                                          ///< Structure that discribe lane mapping
 589   IN      UINT8              Lane0   :2;                  /**< Lane 0 mapping
 590                                                            *  @li @b 0 - Map to lane 0
 591                                                            *  @li @b 1 - Map to lane 1
 592                                                            *  @li @b 2 - Map to lane 2
 593                                                            *  @li @b 2 - Map to lane 3
 594                                                            */
 595   IN      UINT8              Lane1   :2;                  ///< Lane 1 mapping (see "Lane 0 mapping")
 596   IN      UINT8              Lane2   :2;                  ///< Lane 2 mapping (see "Lane 0 mapping")
 597   IN      UINT8              Lane3   :2;                  ///< Lane 3 mapping (see "Lane 0 mapping")
 598 } CHANNEL_MAPPING;                                        ///< Lane mapping
 599
 600 /// Common Channel Mapping
 601 typedef union {
 602   IN      UINT8                ChannelMappingValue;       ///< Raw lane mapping
 603   IN      CHANNEL_MAPPING      ChannelMapping;            ///< Channel mapping
 604 } CONN_CHANNEL_MAPPING;
 605
 606 /// DDI Configuration data
 607 typedef struct  {
 608   IN       UINT8                ConnectorType;            /**< Display Connector Type
 609                                                             *  @li @b 0 - DP
 610                                                             *  @li @b 1 - eDP
 611                                                             *  @li @b 2 - Single Link DVI-D
 612                                                             *  @li @b 3 - Dual  Link DVI-D (see @ref F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description")
 613                                                             *  @li @b 4 - HDMI
 614                                                             *  @li @b 5 - Travis DP-to-VGA
 615                                                             *  @li @b 6 - Travis DP-to-LVDS
 616                                                             *  @li @b 7 - Hudson-2 NutMeg DP-to-VGA
 617                                                             *  @li @b 8 - Single Link DVI-I
 618                                                             *  @li @b 9 - Native CRT (Family 0x14)
 619                                                             *  @li @b 10 - Native LVDS (Family 0x14)
 620                                                             *  @li @b 11 - Auto detect LCD panel connector type. VBIOS is able to auto detect the LVDS connector type: native LVDS, eDP or Travis-LVDS
 621                                                             *              The auto detection method only support panel with EDID.
 622                                                             */
 623   IN       UINT8                AuxIndex;                 /**< Indicates which AUX or DDC Line is used
 624                                                             *  @li @b 0 - AUX1
 625                                                             *  @li @b 1 - AUX2
 626                                                             *  @li @b 2 - AUX3
 627                                                             *  @li @b 3 - AUX4
 628                                                             *  @li @b 4 - AUX5
 629                                                             *  @li @b 5 - AUX6
 630                                                             */
 631   IN       UINT8                HdpIndex;                 /**< Indicates which HDP pin is used
 632                                                             *  @li @b 0 - HDP1
 633                                                             *  @li @b 1 - HDP2
 634                                                             *  @li @b 2 - HDP3
 635                                                             *  @li @b 3 - HDP4
 636                                                             *  @li @b 4 - HDP5
 637                                                             *  @li @b 5 - HDP6
 638                                                             */
 639   IN       CONN_CHANNEL_MAPPING Mapping[2];               /**< Set specific mapping of lanes to connector pins
 640                                                             *  @li Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
 641                                                             *  @li Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only applicable for Dual DDI link)
 642                                                             *  if Mapping[x] set to 0 than default mapping assumed
 643                                                             */
 644 } PCIe_DDI_DATA;
 645
 646 /// Engine Configuration
 647 typedef struct {
 648   IN       UINT8                EngineType;               /**< Engine type
 649                                                            *  @li @b 0 -  Ignore engine configuration
 650                                                            *  @li @b 1 -  PCIe port
 651                                                            *  @li @b 2 -  DDI
 652                                                            */
 653   IN       UINT16               StartLane;                /**< Start Lane ID (in reversed configuration StartLane > EndLane)
 654                                                            * See lane description for @ref F12PcieLaneDescription "Family 0x12"
 655                                                            * @ref F14PcieLaneDescription "Family 0x14".
 656                                                            * See lane configurations for @ref F12LaneConfigurations "Family 0x12"
 657                                                            * @ref F14LaneConfigurations "Family 0x14".
 658                                                            */
 659   IN       UINT16               EndLane;                  /**< End lane ID (in reversed configuration StartLane > EndLane)
 660                                                            * See lane description for @ref F12PcieLaneDescription "Family 0x12",
 661                                                            * @ref F14PcieLaneDescription "Family 0x14".
 662                                                            * See lane configurations for @ref F12LaneConfigurations "Family 0x12"
 663                                                            * @ref F14LaneConfigurations "Family 0x14".
 664                                                            */
 665
 666 } PCIe_ENGINE_DATA;
 667
 668 /// PCIe port descriptor
 669 typedef struct {
 670   IN       UINT32               Flags;                    /**< Descriptor flags
 671                                                            * @li @b Bit31 - last descriptor in complex
 672                                                            */
 673   IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
 674   IN       PCIe_PORT_DATA       Port;                     ///< PCIe port specific configuration info
 675 } PCIe_PORT_DESCRIPTOR;
 676
 677 /// DDI descriptor
 678 typedef struct {
 679   IN       UINT32               Flags;                    /**< Descriptor flags
 680                                                            * @li @b Bit31 - last descriptor in complex
 681                                                            */
 682   IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
 683   IN       PCIe_DDI_DATA        Ddi;                      ///< DDI port specific configuration info
 684 } PCIe_DDI_DESCRIPTOR;
 685
 686 /// PCIe Complex descriptor
 687 typedef struct {
 688   IN       UINT32               Flags;                    /**< Descriptor flags
 689                                                            * @li @b Bit31 - last descriptor in topology
 690                                                            */
 691   IN       UINT32               SocketId;                 ///< Socket Id
 692   IN       PCIe_PORT_DESCRIPTOR *PciePortList;            ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
 693   IN       PCIe_DDI_DESCRIPTOR  *DdiLinkList;             ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
 694   IN       VOID                 *Reserved;                ///< Reserved for future use
 695 } PCIe_COMPLEX_DESCRIPTOR;
 696
 697 /// Action to control PCIe slot reset
 698 typedef enum {
 699   AssertSlotReset,                                        ///< Assert slot reset
 700   DeassertSlotReset                                       ///< Deassert slot reset
 701 } PCIE_RESET_CONTROL;
 702
 703 ///Slot Reset Info
 704 typedef struct {
 705   IN      AMD_CONFIG_PARAMS     StdHeader;                ///< Standard configuration header
 706   IN      UINT8                 ResetId;                  ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
 707   IN      UINT8                 ResetControl;             ///< Reset control as in PCIE_RESET_CONTROL
 708 } PCIe_SLOT_RESET_INFO;
 709
 710 /// Engine descriptor type
 711 typedef enum {
 712   PcieUnusedEngine = 0,                                   ///< Unused descriptor
 713   PciePortEngine = 1,                                     ///< PCIe port
 714   PcieDdiEngine = 2,                                      ///< DDI
 715   MaxPcieEngine                                           ///< Max engine type for boundary check.
 716 } PCIE_ENGINE_TYPE;
 717
 718 /// PCIe link capability/speed
 719 typedef enum  {
 720   PcieGenMaxSupported,                                    ///< Maximum supported
 721   PcieGen1 = 1,                                           ///< Gen1
 722   PcieGen2,                                               ///< Gen2
 723   MaxPcieGen                                              ///< Max Gen for boundary check
 724 } PCIE_LINK_SPEED_CAP;
 725
 726 /// PCIe PSPP Power policy
 727 typedef enum  {
 728   PsppDisabled,                                           ///< PSPP disabled
 729   PsppPerformance = 1,                                    ///< Performance
 730   PsppBalanceHigh,                                        ///< Balance-High
 731   PsppBalanceLow,                                         ///< Balance-Low
 732   PsppPowerSaving,                                        ///< Power Saving
 733   MaxPspp                                                 ///< Max Pspp for boundary check
 734 } PCIE_PSPP_POLICY;
 735
 736 /// DDI display connector type
 737 typedef enum {
 738   ConnectorTypeDP,                                        ///< DP
 739   ConnectorTypeEDP,                                       ///< eDP
 740   ConnectorTypeSingleLinkDVI,                             ///< Single Link DVI-D
 741   ConnectorTypeDualLinkDVI,                               ///< Dual  Link DVI-D
 742   ConnectorTypeHDMI,                                      ///< HDMI
 743   ConnectorTypeTravisDpToVga,                             ///< Travis DP-to-VGA
 744   ConnectorTypeTravisDpToLvds,                            ///< Travis DP-to-LVDS
 745   ConnectorTypeNutmegDpToVga,                             ///< Hudson-2 NutMeg DP-to-VGA
 746   ConnectorTypeSingleLinkDviI,                            ///< Single Link DVI-I
 747   ConnectorTypeCrt,                                       ///< CRT (VGA)
 748   ConnectorTypeLvds,                                      ///< LVDS
 749   ConnectorTypeAutoDetect,                                ///< VBIOS auto detect connector type (native LVDS, eDP or Travis-LVDS)
 750   MaxConnectorType                                        ///< Not valid value, used to verify input
 751 } PCIE_CONNECTOR_TYPE;
 752
 753 /// PCIe link channel type
 754 typedef enum {
 755   ChannelTypeLowLoss,                                     ///< Low Loss
 756   ChannelTypeHighLoss,                                    ///< High Loss
 757   ChannelTypeMob0db,                                      ///< Mobile 0dB
 758   ChannelTypeMob3db,                                      ///< Mobile 3dB
 759   ChannelTypeExt6db,                                      ///< Extended 6dB
 760   ChannelTypeExt8db,                                      ///< Extended 8dB
 761   MaxChannelType                                          ///< Not valid value, used to verify input
 762 } PCIE_CHANNEL_TYPE;
 763
 764 /// PCIe link ASPM
 765 typedef enum {
 766   AspmDisabled,                                           ///< Disabled
 767   AspmL0s,                                                ///< PCIe L0s link state
 768   AspmL1,                                                 ///< PCIe L1 link state
 769   AspmL0sL1,                                              ///< PCIe L0s & L1 link state
 770   MaxAspm                                                 ///< Not valid value, used to verify input
 771 } PCIE_ASPM_TYPE;
 772
 773 /// PCIe link hotplug support
 774 typedef enum {
 775   HotplugDisabled,                                        ///< Hotplug disable
 776   HotplugBasic,                                           ///< Basic Hotplug
 777   HotplugServer,                                          ///< Server Hotplug
 778   HotplugEnhanced,                                        ///< Enhanced
 779   HotplugInboard,                                         ///< Inboard
 780   MaxHotplug                                              ///< Not valid value, used to verify input
 781 } PCIE_HOTPLUG_TYPE;
 782
 783 /// PCIe link initialization
 784 typedef enum {
 785   PortDisabled,                                           ///< Disable
 786   PortEnabled                                             ///< Enable
 787 } PCIE_PORT_ENABLE;
 788
 789 /// DDI Aux channel
 790 typedef enum {
 791   Aux1,                                                   ///< Aux1
 792   Aux2,                                                   ///< Aux2
 793   Aux3,                                                   ///< Aux3
 794   Aux4,                                                   ///< Aux4
 795   Aux5,                                                   ///< Aux5
 796   Aux6,                                                   ///< Aux6
 797   MaxAux                                                  ///< Not valid value, used to verify input
 798 } PCIE_AUX_TYPE;
 799
 800 /// DDI Hdp Index
 801 typedef enum {
 802   Hdp1,                                                   ///< Hdp1
 803   Hdp2,                                                   ///< Hdp2
 804   Hdp3,                                                   ///< Hdp3
 805   Hdp4,                                                   ///< Hdp4
 806   Hdp5,                                                   ///< Hdp5
 807   Hdp6,                                                   ///< Hdp6
 808   MaxHdp                                                  ///< Not valid value, used to verify input
 809 } PCIE_HDP_TYPE;
 810
 811 // Macro for statically initialization of various structures
 812 #define  PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane}
 813 #define  PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \
 814 {mPortPresent, mChannelType, mDevAddress, 0, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap} }
 815 #define  PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \
 816 {mConnectorType, mAuxIndex, mHpdIndex, {0, 0}}
 817 #define  PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1) \
 818 {mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}}
 819
 820
 821 /*----------------------------------------------------------------------------
 822  *   GNB configuration info
 823  *----------------------------------------------------------------------------
 824  */
 825
 826 /// LVDS Misc Control Field
 827 typedef struct {
 828   IN  UINT8     FpdiMode:1;          ///< This item configures LVDS 888bit panel mode
 829                                      ///< @li FALSE = LVDS 888 panel in LDI mode
 830                                      ///< @li TRUE =  LVDS 888 panel in FPDI mode
 831                                      ///< @BldCfgItem{BLDCFG_LVDS_MISC_888_FPDI_MODE}
 832   IN  UINT8     DlChSwap:1;          ///< This item configures LVDS panel lower and upper link mapping
 833                                      ///< @li FALSE = Lower link and upper link not swap
 834                                      ///< @li TRUE = Lower link and upper link are swapped
 835                                      ///< @BldCfgItem{BLDCFG_LVDS_MISC_DL_CH_SWAP}
 836   IN  UINT8     VsyncActiveLow:1;    ///< This item configures polarity of frame pulse encoded in lvds data stream
 837                                      ///< @li FALSE = Active high Frame Pulse/Vsync
 838                                      ///< @li TRUE = Active low Frame Pulse/Vsync
 839                                      ///< @BldCfgItem{BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW}
 840   IN  UINT8     HsyncActiveLow:1;    ///< This item configures polarity of line pulse encoded in lvds data
 841                                      ///< @li FALSE = Active high Line Pulse
 842                                      ///< @li TRUE = Active low Line Pulse / Hsync
 843                                      ///< @BldCfgItem{BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW}
 844   IN  UINT8     BLONActiveLow:1;     ///< This item configures polarity of signal sent to digital BLON output pin
 845                                      ///< @li FALSE = Not inverted(active high)
 846                                      ///< @li TRUE = Inverted (active low)
 847                                      ///< @BldCfgItem{BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW}
 848   IN  UINT8     Reserved:3;          ///< Reserved
 849 } LVDS_MISC_CONTROL_FIELD;
 850
 851 /// LVDS Misc Control
 852 typedef union _LVDS_MISC_CONTROL {
 853   IN LVDS_MISC_CONTROL_FIELD Field;  ///< LVDS_MISC_CONTROL_FIELD
 854   IN UINT8   Value;                  ///< LVDS Misc Control Value
 855 } LVDS_MISC_CONTROL;
 856
 857 /// Configuration settings for GNB.
 858 typedef struct {
 859   IN  UINT8     Gnb3dStereoPinIndex;      ///< 3D Stereo Pin ID.
 860                                           ///< @li 0 = Stereo 3D is disabled (default).
 861                                           ///< @li 1 = Use processor pin HPD1.
 862                                           ///< @li 2 = Use processor pin HPD2
 863                                           ///< @li 3 = Use processor pin HPD3
 864                                           ///< @li 4 = Use processor pin HPD4
 865                                           ///< @li 5 = Use processor pin HPD5
 866                                           ///< @li 6 = Use processor pin HPD6
 867                                           ///< @BldCfgItem{BLDCFG_STEREO_3D_PINOUT}
 868   IN  UINT16     LvdsSpreadSpectrum;      ///< Spread spectrum value in 0.01 %
 869                                           ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
 870   IN  UINT16     LvdsSpreadSpectrumRate;  ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
 871                                           ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
 872   IN  LVDS_MISC_CONTROL      LvdsMiscControl;///< This item configures LVDS swap/Hsync/Vsync/BLON
 873   IN  UINT16     PcieRefClkSpreadSpectrum;   ///< Spread spectrum value in 0.01 %
 874                                              ///< @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
 875 } GNB_ENV_CONFIGURATION;
 876
 877 /// GNB configuration info
 878 typedef struct {
 879   IN       PCIe_COMPLEX_DESCRIPTOR  *PcieComplexList;  /**< Pointer to array of structures describe PCIe topology on each processor package or NULL.
 880                                                         * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST
 881                                                         * Example of topology definition for single socket system:
 882                                                         * @code
 883                                                         *  PCIe_PORT_DESCRIPTOR PortList [] = {
 884                                                         *    // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
 885                                                         *    {
 886                                                         *      0,   //Descriptor flags
 887                                                         *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
 888                                                         *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
 889                                                         *    },
 890                                                         *    // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
 891                                                         *    {
 892                                                         *      0,   //Descriptor flags
 893                                                         *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
 894                                                         *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
 895                                                         *    },
 896                                                         *    // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
 897                                                         *    {
 898                                                         *      DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
 899                                                         *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
 900                                                         *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
 901                                                         *    }
 902                                                         *  };
 903                                                         *  PCIe_PORT_DESCRIPTOR DdiList [] = {
 904                                                         *    // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...)
 905                                                         *    {
 906                                                         *      0,   //Descriptor flags
 907                                                         *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
 908                                                         *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0)
 909                                                         *    },
 910                                                         *    // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
 911                                                         *    {
 912                                                         *      DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
 913                                                         *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
 914                                                         *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0)
 915                                                         *    }
 916                                                         *  };
 917                                                         * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {
 918                                                         *   DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate complexes list
 919                                                         *   0,  //Socket ID
 920                                                         *   &PortList[0],
 921                                                         *   &DdiList[0],
 922                                                         * }
 923                                                         * @endcode
 924                                                         */
 925   IN       UINT8                    PsppPolicy;         /**< PSPP (PCIe Speed Power Policy)
 926                                                          *  @li @b 0 - Disabled
 927                                                          *  @li @b 1 - Performance
 928                                                          *  @li @b 2 - Balance-High
 929                                                          *  @li @b 3 - Balance-Low
 930                                                          *  @li @b 4 - Power Saving
 931                                                          */
 932
 933 } GNB_CONFIGURATION;
 934 //
 935 //  MEMORY-SPECIFIC DATA STRUCTURES
 936 //
 937 //
 938 //
 939 //
 940 // AGESA MAXIMIUM VALUES
 941 //
 942 //   These Max values are used to define array sizes and associated loop
 943 //   counts in the code.  They reflect the maximum values that AGESA
 944 //   currently supports and does not necessarily reflect the hardware
 945 //   capabilities of configuration.
 946 //
 947
 948 #define MAX_SOCKETS_SUPPORTED   8   ///< Max number of sockets in system
 949 #define MAX_CHANNELS_PER_SOCKET 4   ///< Max Channels per sockets
 950 #define MAX_DIMMS_PER_CHANNEL   4   ///< Max DIMMs on a memory channel (independent of platform)
 951 #define NUMBER_OF_DELAY_TABLES  9   ///< Number of tables defined in CH_DEF_STRUCT.
 952                                     ///< Eg: UINT16  *RcvEnDlys;
 953                                     ///<     UINT8   *WrDqsDlys;
 954                                     ///<     UINT8   *RdDqsDlys;
 955                                     ///<     UINT8   *WrDatDlys;
 956                                     ///<     UINT8   *RdDqsMinDlys;
 957                                     ///<     UINT8   *RdDqsMaxDlys;
 958                                     ///<     UINT8   *WrDatMinDlys;
 959                                     ///<     UINT8   *WrDatMaxDlys;
 960 #define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables
 961
 962 #define MAX_PLATFORM_TYPES     16   ///< Platform types per system
 963
 964 #define MCT_TRNG_KEEPOUT_START  0x00004000    ///< base [39:8]
 965 #define MCT_TRNG_KEEPOUT_END    0x00007FFF    ///< base [39:8]
 966
 967 #define UMA_ATTRIBUTE_INTERLEAVE 0x80000000   ///< Uma Region is interleaved
 968 #define UMA_ATTRIBUTE_ON_DCT0    0x40000000   ///< UMA resides on memory that belongs to DCT0
 969 #define UMA_ATTRIBUTE_ON_DCT1    0x20000000   ///< UMA resides on memory that belongs to DCT1
 970
 971 typedef UINT8 PSO_TABLE;            ///< Platform Configuration Table
 972
 973 //        AGESA DEFINITIONS
 974 //
 975 //        Many of these are derived from the platform and hardware specific definitions
 976
 977 /// EccSymbolSize override value
 978 #define ECCSYMBOLSIZE_USE_BKDG      0   ///< Use BKDG Recommended Value
 979 #define ECCSYMBOLSIZE_FORCE_X4      4   ///< Force to x4
 980 #define ECCSYMBOLSIZE_FORCE_X8      8   ///< Force to x8
 981 /// CPU Package Type
 982 #define PT_L1       0                 ///< L1 Package type
 983 #define PT_M2       1                 ///< AM Package type
 984 #define PT_S1       2                 ///< S1 Package type
 985
 986 /// Structures use to pass system Logical CPU-ID
 987 typedef struct {
 988   IN OUT   UINT64 Family;             ///< Indicates logical ID Family
 989   IN OUT   UINT64 Revision;           ///< Indicates logical ID Family
 990 } CPU_LOGICAL_ID;
 991
 992 /// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
 993 typedef enum {
 994   AMD_PLATFORM_SERVER = 0x8000,     ///< Server
 995   AMD_PLATFORM_DESKTOP = 0x10000,   ///< Desktop
 996   AMD_PLATFORM_MOBILE = 0x20000,    ///< Mobile
 997 } AMD_PLATFORM_TYPE;
 998
 999 /// Dram technology type
1000 typedef enum {
1001   DDR2_TECHNOLOGY,      ///< DDR2 technology
1002   DDR3_TECHNOLOGY       ///< DDR3 technology
1003 } TECHNOLOGY_TYPE;
1004
1005 /// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
1006 typedef enum {
1007   DDR400_FREQUENCY = 200,     ///< DDR 400
1008   DDR533_FREQUENCY = 266,     ///< DDR 533
1009   DDR667_FREQUENCY = 333,     ///< DDR 667
1010   DDR800_FREQUENCY = 400,     ///< DDR 800
1011   DDR1066_FREQUENCY = 533,    ///< DDR 1066
1012   DDR1333_FREQUENCY = 667,    ///< DDR 1333
1013   DDR1600_FREQUENCY = 800,    ///< DDR 1600
1014   DDR1866_FREQUENCY = 933,    ///< DDR 1866
1015   UNSUPPORTED_DDR_FREQUENCY   ///< Highest limit of DDR frequency
1016 } MEMORY_BUS_SPEED;
1017
1018 /// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
1019 typedef enum {
1020   QUADRANK_REGISTERED,        ///< Quadrank registered DIMM
1021   QUADRANK_UNBUFFERED         ///< Quadrank unbuffered DIMM
1022 } QUANDRANK_TYPE;
1023
1024 /// Build Configuration values for BLDCFG_TIMING_MODE_SELECT
1025 typedef enum {
1026   TIMING_MODE_AUTO,           ///< Use best rate possible
1027   TIMING_MODE_LIMITED,        ///< Set user top limit
1028   TIMING_MODE_SPECIFIC        ///< Set user specified speed
1029 } USER_MEMORY_TIMING_MODE;
1030
1031 /// Build Configuration values for BLDCFG_POWER_DOWN_MODE
1032 typedef enum {
1033   POWER_DOWN_BY_CHANNEL,      ///< Channel power down mode
1034   POWER_DOWN_BY_CHIP_SELECT,  ///< Chip select power down mode
1035   POWER_DOWN_MODE_AUTO        ///< AGESA to select power down mode
1036 } POWER_DOWN_MODE;
1037
1038 /// Low voltage support
1039 typedef enum {
1040   VOLT1_5,                   ///< 1.5 Volt
1041   VOLT1_35,                  ///< 1.35 Volt
1042   VOLT1_25,                  ///< 1.25 Volt
1043   VOLT_UNSUPPORTED = 0xFF    ///< No common voltage found
1044 } DIMM_VOLTAGE;
1045
1046 /// UMA Mode
1047 typedef enum {
1048   UMA_NONE = 0,              ///< UMA None
1049   UMA_SPECIFIED = 1,         ///< UMA Specified
1050   UMA_AUTO = 2               ///< UMA Auto
1051 } UMA_MODE;
1052
1053 /// Build Configuration values for BLDCFG_UMA_ALIGNMENT
1054 typedef enum {
1055   NO_UMA_ALIGNED = 0x00FFFFFF,           ///< NO UMA aligned
1056   UMA_128MB_ALIGNED = 0x00FFF800,        ///< UMA 128MB aligned
1057   UMA_256MB_ALIGNED = 0x00FFF000,        ///< UMA 256MB aligned
1058   UMA_512MB_ALIGNED = 0x00FFE000,        ///< UMA 512MB aligned
1059 } UMA_ALIGNMENT;
1060
1061 ///
1062 ///   Global MCT Configuration Status Word (GStatus)
1063 ///
1064 typedef enum {
1065   GsbMTRRshort,              ///< Ran out of MTRRs while mapping memory
1066   GsbAllECCDimms,            ///< All banks of all Nodes are ECC capable
1067   GsbDramECCDis,             ///< Dram ECC requested but not enabled.
1068   GsbSoftHole,               ///< A Node Base gap was created
1069   GsbHWHole,                 ///< A HW dram remap was created
1070   GsbNodeIntlv,              ///< Node Memory interleaving was enabled
1071   GsbSpIntRemapHole,         ///< Special condition for Node Interleave and HW remapping
1072   GsbEnDIMMSpareNW,          ///< Indicates that DIMM Spare can be used without a warm reset
1073
1074   GsbEOL                     ///< End of list
1075 } GLOBAL_STATUS_FIELD;
1076
1077 ///
1078 ///   Local Error Status (DIE_STRUCT.ErrStatus[31:0])
1079 ///
1080 typedef enum {
1081   EsbNoDimms,                  ///< No DIMMs
1082   EsbSpdChkSum,                ///< SPD Checksum fail
1083   EsbDimmMismatchM,            ///< dimm module type(buffer) mismatch
1084   EsbDimmMismatchT,            ///< dimm CL/T mismatch
1085   EsbDimmMismatchO,            ///< dimm organization mismatch (128-bit)
1086   EsbNoTrcTrfc,                ///< SPD missing Trc or Trfc info
1087   EsbNoCycTime,                ///< SPD missing byte 23 or 25
1088   EsbBkIntDis,                 ///< Bank interleave requested but not enabled
1089   EsbDramECCDis,               ///< Dram ECC requested but not enabled
1090   EsbSpareDis,                 ///< Online spare requested but not enabled
1091   EsbMinimumMode,              ///< Running in Minimum Mode
1092   EsbNoRcvrEn,                 ///< No DQS Receiver Enable pass window found
1093   EsbSmallRcvr,                ///< DQS Rcvr En pass window too small (far right of dynamic range)
1094   EsbNoDqsPos,                 ///< No DQS-DQ passing positions
1095   EsbSmallDqs,                 ///< DQS-DQ passing window too small
1096   EsbDCBKScrubDis,             ///< DCache scrub requested but not enabled
1097
1098   EsbEMPNotSupported,          ///< Processor is not capable for EMP.
1099   EsbEMPConflict,               ///< EMP requested but cannot be enabled since
1100                                ///< channel interleaving, bank interleaving, or bank swizzle is enabled.
1101   EsbEMPDis,                   ///< EMP requested but cannot be enabled since
1102                                ///< memory size of each DCT is not a power of two.
1103
1104   EsbEOL                       ///< End of list
1105 } ERROR_STATUS_FIELD;
1106
1107 ///
1108 ///  Local Configuration Status (DIE_STRUCT.Status[31:0])
1109 ///
1110 typedef enum {
1111   SbRegistered,                ///< All DIMMs are Registered
1112   SbEccDimms,                  ///< All banks ECC capable
1113   SbParDimms,                  ///< All banks Addr/CMD Parity capable
1114   SbDiagClks,                  ///< Jedec ALL slots clock enable diag mode
1115   Sb128bitmode,                ///< DCT in 128-bit mode operation
1116   Sb64MuxedMode,               ///< DCT in 64-bit mux'ed mode.
1117   Sb2TMode,                    ///< 2T CMD timing mode is enabled.
1118   SbSWNodeHole,                ///< Remapping of Node Base on this Node to create a gap.
1119   SbHWHole,                    ///< Memory Hole created on this Node using HW remapping.
1120   SbOver400Mhz,                ///< DCT freq greater than or equal to 400MHz flag
1121   SbDQSPosPass2,               ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
1122   SbDQSRcvLimit,               ///< Used for DQSRcvEnTrain to know we have reached the upper bound.
1123   SbExtConfig,                 ///< Indicate the default setting for extended PCI configuration support
1124   SbLrdimms,                   ///< All DIMMs are LRDIMMs
1125
1126   SbEOL                        ///< End of list
1127 } LOCAL_STATUS_FIELD;
1128
1129
1130 ///< CPU MSR Register definitions ------------------------------------------
1131 #define SYS_CFG     0xC0010010
1132 #define TOP_MEM     0xC001001A
1133 #define TOP_MEM2    0xC001001D
1134 #define HWCR        0xC0010015
1135 #define NB_CFG      0xC001001F
1136
1137 #define FS_BASE     0xC0000100
1138 #define IORR0_BASE  0xC0010016
1139 #define IORR0_MASK  0xC0010017
1140 #define BU_CFG      0xC0011023
1141 #define BU_CFG2     0xC001102A
1142 #define COFVID_STAT 0xC0010071
1143 #define TSC         0x10
1144
1145 //-----------------------------------------------------------------------------
1146 ///
1147 /// SPD Data for each DIMM.
1148 ///
1149 typedef struct _SPD_DEF_STRUCT {
1150   IN BOOLEAN DimmPresent;       ///< Indicates that the DIMM is present and Data is valid
1151   IN UINT8 Data[256];           ///< Buffer for 256 Bytes of SPD data from DIMM
1152 } SPD_DEF_STRUCT;
1153
1154 ///
1155 /// Channel Definition Structure.
1156 /// This data structure defines entries that are specific to the channel initialization
1157 ///
1158 typedef struct _CH_DEF_STRUCT {
1159   OUT UINT8   ChannelID;         ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
1160   OUT TECHNOLOGY_TYPE TechType;  ///< Technology type of this channel
1161   OUT UINT8   ChDimmPresent;     ///< For each bit n 0..7, 1 = DIMM n is present.
1162                                  ///<  DIMM#  Select Signal
1163                                  ///<  0      MA0_CS_L[0, 1]
1164                                  ///<  1      MB0_CS_L[0, 1]
1165                                  ///<  2      MA1_CS_L[0, 1]
1166                                  ///<  3      MB1_CS_L[0, 1]
1167                                  ///<  4      MA2_CS_L[0, 1]
1168                                  ///<  5      MB2_CS_L[0, 1]
1169                                  ///<  6      MA3_CS_L[0, 1]
1170                                  ///<  7      MB3_CS_L[0, 1]
1171
1172   OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel.
1173   OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel.
1174   OUT SPD_DEF_STRUCT *SpdPtr;    ///< Pointer to the SPD data for this channel. (Setup by NB Constructor)
1175   OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to
1176                                  ///<   SPD Data for each Dimm. (Setup by Tech Block Constructor)
1177   OUT UINT8   ChDimmValid;       ///< For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
1178                                  ///<
1179   OUT UINT8   RegDimmPresent;    ///< For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
1180   OUT UINT8   LrDimmPresent;     ///< For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
1181   OUT UINT8   SODimmPresent;     ///< For each bit n 0..3, 1 = DIMM n is a SO-DIMM, where 4..7 are reserved.
1182   OUT UINT8   Loads;             ///< Number of devices loading bus
1183   OUT UINT8   Dimms;             ///< Number of DIMMs loading Channel
1184   OUT UINT8   Ranks;             ///< Number of ranks loading Channel DATA
1185   OUT BOOLEAN SlowMode;          ///< 1T or 2T CMD mode (slow access mode)
1186                                  ///< FALSE = 1T
1187                                  ///< TRUE = 2T
1188   ///< The following pointers will be pointed to dynamically allocated buffers.
1189   ///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
1190   ///< Example: If DIMM and Byte based training, then
1191   ///< XX is a value in Hex
1192   ///<                        BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
1193   ///<  Row1 -  Logical DIMM0    XX      XX      XX      XX      XX      XX      XX      XX      XX
1194   ///<  Row2 -  Logical DIMM1    XX      XX      XX      XX      XX      XX      XX      XX      XX
1195   OUT UINT16  *RcvEnDlys;       ///< DQS Receiver Enable Delays
1196   OUT UINT8   *WrDqsDlys;       ///< Write DQS delays (only valid for DDR3)
1197   OUT UINT8   *RdDqsDlys;       ///< Read Dqs delays
1198   OUT UINT8   *WrDatDlys;       ///< Write Data delays
1199   OUT UINT8   *RdDqsMinDlys;    ///< Minimum Window for Read DQS
1200   OUT UINT8   *RdDqsMaxDlys;    ///< Maximum Window for Read DQS
1201   OUT UINT8   *WrDatMinDlys;    ///< Minimum Window for Write data
1202   OUT UINT8   *WrDatMaxDlys;    ///< Maximum Window for Write data
1203   OUT UINT8   RowCount;         ///< Number of rows of the allocated buffer.
1204   OUT UINT8   ColumnCount;      ///< Number of columns of the allocated buffer.
1205   OUT UINT8   *FailingBitMask;    ///< Table of masks to Track Failing bits
1206   OUT UINT32  DctOdcCtl;          ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
1207   OUT UINT32  DctAddrTmg;         ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
1208   OUT UINT32  PhyRODTCSLow;       ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
1209   OUT UINT32  PhyRODTCSHigh;      ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
1210   OUT UINT32  PhyWODTCSLow;       ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
1211   OUT UINT32  PhyWODTCSHigh;      ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
1212   OUT UINT8   PhyWLODT[4];        ///< Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8])
1213   OUT UINT16  DctEccDqsLike;      ///< DCT DQS ECC UINT8 like...
1214   OUT UINT8   DctEccDqsScale;     ///< DCT DQS ECC UINT8 scale
1215   OUT UINT16  PtrPatternBufA;     ///< Ptr on stack to aligned DQS testing pattern
1216   OUT UINT16  PtrPatternBufB;     ///< Ptr on stack to aligned DQS testing pattern
1217   OUT UINT8   ByteLane;           ///< Current UINT8 Lane (0..7)
1218   OUT UINT8   Direction;          ///< Current DQS-DQ training write direction (0=read, 1=write)
1219   OUT UINT8   Pattern;            ///< Current pattern
1220   OUT UINT8   DqsDelay;           ///< Current DQS delay value
1221   OUT UINT16  HostBiosSrvc1;      ///< UINT16 sized general purpose field for use by host BIOS.  Scratch space.
1222   OUT UINT32  HostBiosSrvc2;      ///< UINT32 sized general purpose field for use by host BIOS.  Scratch space.
1223   OUT UINT16  DctMaxRdLat;        ///< Max Read Latency (ns) for the DCT
1224   OUT UINT8   DIMMValidCh;        ///< DIMM# in CH
1225   OUT UINT8   MaxCh;              ///< Max number of CH in system
1226   OUT UINT8   Dct;                ///< Dct pointer
1227   OUT UINT8   WrDatGrossH;        ///< Write Data Gross delay high value
1228   OUT UINT8   DqsRcvEnGrossL;     ///< DQS Receive Enable Gross Delay low
1229
1230   OUT UINT8   TrwtWB;             ///<  Non-SPD timing value for TrwtWB
1231   OUT UINT8   CurrRcvrDctADelay;  ///< for keep current RcvrEnDly
1232   OUT UINT16  T1000;              ///< get the T1000 figure (cycle time (ns) * 1K)
1233   OUT UINT8   DqsRcvEnPass;       ///< for TrainRcvrEn UINT8 lane pass flag
1234   OUT UINT8   DqsRcvEnSaved;      ///< for TrainRcvrEn UINT8 lane saved flag
1235   OUT UINT8   SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training
1236
1237   OUT UINT8   ClToNbFlag;         ///< is used to restore ClLinesToNbDis bit after memory
1238   OUT UINT32  NodeSysBase;        ///< for channel interleave usage
1239   OUT UINT8   RefRawCard[MAX_DIMMS_PER_CHANNEL];   ///< Array of rawcards detected
1240   OUT UINT8   CtrlWrd02[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 2 values per DIMM
1241   OUT UINT8   CtrlWrd03[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 3 values per DIMM
1242   OUT UINT8   CtrlWrd04[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 4 values per DIMM
1243   OUT UINT8   CtrlWrd05[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 5 values per DIMM
1244   OUT UINT8   CtrlWrd08[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 8 values per DIMM
1245
1246   OUT UINT16  CsPresentDCT;       ///< For each bit n 0..7, 1 = Chip-select n is present
1247   OUT UINT8   DimmMirrorPresent;  ///< For each bit n 0..3, 1 = DIMM n is OnDimmMirror capable where 4..7 are reserved.
1248   OUT UINT8   DimmSpdCse;         ///< For each bit n 0..3, 1 = DIMM n SPD checksum error where 4..7 are reserved.
1249   OUT UINT8   DimmExclude;        ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
1250   OUT UINT8   DimmYr06;           ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006
1251   OUT UINT8   DimmWk2406;         ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
1252   OUT UINT8   DimmPlPresent;      ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
1253   OUT UINT8   DimmQrPresent;      ///< QuadRank DIMM present?
1254   OUT UINT8   DimmDrPresent;      ///< Bitmap indicating that Dual Rank Dimms are present
1255   OUT UINT8   DimmSRPresent;      ///< Bitmap indicating that Single Rank Dimms are present
1256   OUT UINT8   Dimmx4Present;      ///< For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
1257   OUT UINT8   Dimmx8Present;      ///< For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
1258   OUT UINT8   Dimmx16Present;     ///< For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
1259   OUT UINT8   LrdimmPhysicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of Physical Ranks for LRDIMMs
1260   OUT UINT8   LrDimmLogicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of LRDIMM Logical ranks in this configuration
1261   OUT UINT8   LrDimmRankMult[MAX_DIMMS_PER_CHANNEL];///< Rank Multipication factor per dimm.
1262
1263   OUT UINT8   *MemClkDisMap;      ///<  This pointer will be set to point to an array that describes
1264                                   ///<  the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
1265                                   ///<  base on this array to disable unused MemClk to save power.
1266                                   ///<
1267                                   ///<  The array must have 8 entries. Each entry, which associates with
1268                                   ///<  one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
1269                                   ///<    Example:
1270                                   ///<    BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
1271                                   ///<    is like below:
1272                                   ///<         Bit AM3/S1g3 pin name
1273                                   ///<         0   M[B,A]_CLK_H/L[0]
1274                                   ///<         1   M[B,A]_CLK_H/L[1]
1275                                   ///<         2   M[B,A]_CLK_H/L[2]
1276                                   ///<         3   M[B,A]_CLK_H/L[3]
1277                                   ///<         4   M[B,A]_CLK_H/L[4]
1278                                   ///<         5   M[B,A]_CLK_H/L[5]
1279                                   ///<         6   M[B,A]_CLK_H/L[6]
1280                                   ///<         7   M[B,A]_CLK_H/L[7]
1281                                   ///<    And platform has the following routing:
1282                                   ///<         CS0   M[B,A]_CLK_H/L[4]
1283                                   ///<         CS1   M[B,A]_CLK_H/L[2]
1284                                   ///<         CS2   M[B,A]_CLK_H/L[3]
1285                                   ///<         CS3   M[B,A]_CLK_H/L[5]
1286                                   ///<    Then MemClkDisMap should be pointed to the following array:
1287                                   ///<               CLK_2 CLK_3 CLK_4 CLK_5
1288                                   ///<    0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
1289                                   ///<  Each entry of the array is the bitmask of 8 chip selects.
1290
1291   OUT UINT8   *CKETriMap;         ///<  This pointer will be set to point to an array that describes
1292                                   ///<  the routing of CKE pins to the DIMMs' ranks.
1293                                   ///<  The array must have 2 entries. Each entry, which associates with
1294                                   ///<  one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
1295                                   ///<  AGESA will base on this array to disable unused CKE pins to save power.
1296
1297   OUT UINT8   *ODTTriMap;         ///<  This pointer will be set to point to an array that describes
1298                                   ///<  the routing of ODT pins to the DIMMs' ranks.
1299                                   ///<  The array must have 4 entries. Each entry, which associates with
1300                                   ///<  one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
1301                                   ///<  AGESA will base on this array to disable unused ODT pins to save power.
1302
1303   OUT UINT8   *ChipSelTriMap;     ///<  This pointer will be set to point to an array that describes
1304                                   ///<  the routing of chip select pins to the DIMMs' ranks.
1305                                   ///<  The array must have 8 entries. Each entry is a bitmap of 8 CS.
1306                                   ///<  AGESA will base on this array to disable unused Chip select pins to save power.
1307
1308   OUT BOOLEAN   ExtendTmp;        ///<  If extended temperature is supported on all dimms on a channel.
1309
1310   OUT UINT8   Reserved[100];      ///< Reserved
1311 } CH_DEF_STRUCT;
1312
1313 ///
1314 /// DCT Channel Timing Parameters.
1315 /// This data structure sets timings that are specific to the channel.
1316 ///
1317 typedef struct _CH_TIMING_STRUCT {
1318   OUT UINT16  DctDimmValid;       ///< For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
1319   OUT UINT16  DimmMirrorPresent;  ///< For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
1320   OUT UINT16  DimmSpdCse;         ///< For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
1321   OUT UINT16  DimmExclude;        ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
1322   OUT UINT16  CsPresent;          ///< For each bit n 0..7, 1=Chip-select n is present
1323   OUT UINT16  CsEnabled;          ///< For each bit n 0..7, 1=Chip-select n is enabled
1324   OUT UINT16  CsTestFail;         ///< For each bit n 0..7, 1=Chip-select n is present but disabled
1325   OUT UINT16  CsTrainFail;        ///< Bitmap showing which chipselects failed training
1326   OUT UINT16  DIMM1KPage;         ///< For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved
1327   OUT UINT16  DimmQrPresent;      ///< QuadRank DIMM present?
1328   OUT UINT16  DimmDrPresent;      ///< Bitmap indicating that Dual Rank Dimms are present , where 4..7 are reserved
1329   OUT UINT8   DimmSRPresent;      ///< Bitmap indicating that Single Rank Dimms are present, where 4..7 are reserved
1330   OUT UINT16  Dimmx4Present;      ///< For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved
1331   OUT UINT16  Dimmx8Present;      ///< For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved
1332   OUT UINT16  Dimmx16Present;     ///< For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved
1333
1334   OUT UINT16  DIMMTrcd;           ///< Minimax Trcd*40 (ns) of DIMMs
1335   OUT UINT16  DIMMTrp;            ///< Minimax Trp*40 (ns) of DIMMs
1336   OUT UINT16  DIMMTrtp;           ///< Minimax Trtp*40 (ns) of DIMMs
1337   OUT UINT16  DIMMTras;           ///< Minimax Tras*40 (ns) of DIMMs
1338   OUT UINT16  DIMMTrc;            ///< Minimax Trc*40 (ns) of DIMMs
1339   OUT UINT16  DIMMTwr;            ///< Minimax Twr*40 (ns) of DIMMs
1340   OUT UINT16  DIMMTrrd;           ///< Minimax Trrd*40 (ns) of DIMMs
1341   OUT UINT16  DIMMTwtr;           ///< Minimax Twtr*40 (ns) of DIMMs
1342   OUT UINT16  DIMMTfaw;           ///< Minimax Tfaw*40 (ns) of DIMMs
1343   OUT UINT16  TargetSpeed;        ///< Target DRAM bus speed in MHz
1344   OUT UINT16  Speed;              ///< DRAM bus speed in MHz
1345                                   ///<  400 (MHz)
1346                                   ///<  533 (MHz)
1347                                   ///<  667 (MHz)
1348                                   ///<  800 (MHz)
1349                                   ///<  and so on...
1350   OUT UINT8   CasL;               ///< CAS latency DCT setting (busclocks)
1351   OUT UINT8   Trcd;               ///< DCT Trcd (busclocks)
1352   OUT UINT8   Trp;                ///< DCT Trp (busclocks)
1353   OUT UINT8   Trtp;               ///< DCT Trtp (busclocks)
1354   OUT UINT8   Tras;               ///< DCT Tras (busclocks)
1355   OUT UINT8   Trc;                ///< DCT Trc (busclocks)
1356   OUT UINT8   Twr;                ///< DCT Twr (busclocks)
1357   OUT UINT8   Trrd;               ///< DCT Trrd (busclocks)
1358   OUT UINT8   Twtr;               ///< DCT Twtr (busclocks)
1359   OUT UINT8   Tfaw;               ///< DCT Tfaw (busclocks)
1360   OUT UINT8   Trfc0;              ///< DCT Logical DIMM0 Trfc
1361                                   ///<  0 = 75ns (for 256Mb devs)
1362                                   ///<  1 = 105ns (for 512Mb devs)
1363                                   ///<  2 = 127.5ns (for 1Gb devs)
1364                                   ///<  3 = 195ns (for 2Gb devs)
1365                                   ///<  4 = 327.5ns (for 4Gb devs)
1366   OUT UINT8   Trfc1;              ///< DCT Logical DIMM1 Trfc (see Trfc0 for format)
1367   OUT UINT8   Trfc2;              ///< DCT Logical DIMM2 Trfc (see Trfc0 for format)
1368   OUT UINT8   Trfc3;              ///< DCT Logical DIMM3 Trfc (see Trfc0 for format)
1369   OUT UINT32  DctMemSize;         ///< Base[47:16], total DRAM size controlled by this DCT.
1370                                   ///<
1371   OUT BOOLEAN SlowMode;           ///< 1T or 2T CMD mode (slow access mode)
1372                                   ///< FALSE = 1T
1373                                   ///< TRUE = 2T
1374   OUT UINT8   TrwtTO;             ///< DCT TrwtTO (busclocks)
1375   OUT UINT8   Twrrd;              ///< DCT Twrrd (busclocks)
1376   OUT UINT8   Twrwr;              ///< DCT Twrwr (busclocks)
1377   OUT UINT8   Trdrd;              ///< DCT Trdrd (busclocks)
1378   OUT UINT8   TrwtWB;             ///< DCT TrwtWB (busclocks)
1379   OUT UINT8   TrdrdSD;            ///< DCT TrdrdSD (busclocks)
1380   OUT UINT8   TwrwrSD;            ///< DCT TwrwrSD (busclocks)
1381   OUT UINT8   TwrrdSD;            ///< DCT TwrrdSD (busclocks)
1382   OUT UINT16  MaxRdLat;           ///< Max Read Latency
1383   OUT UINT8   WrDatGrossH;        ///< Temporary variables must be removed
1384   OUT UINT8   DqsRcvEnGrossL;     ///< Temporary variables must be removed
1385 } CH_TIMING_STRUCT;
1386
1387 ///
1388 /// Data for each DCT.
1389 /// This data structure defines data used to configure each DRAM controller.
1390 ///
1391 typedef struct _DCT_STRUCT {
1392   OUT UINT8   Dct;                ///< Current Dct
1393   OUT CH_TIMING_STRUCT Timings;   ///< Channel Timing structure
1394   OUT CH_DEF_STRUCT    *ChData;   ///< Pointed to a dynamically allocated array of Channel structures
1395   OUT UINT8   ChannelCount;       ///< Number of channel per this DCT
1396 } DCT_STRUCT;
1397
1398
1399 ///
1400 /// Data Structure defining each Die.
1401 /// This data structure contains information that is used to configure each Die.
1402 ///
1403 typedef struct _DIE_STRUCT {
1404
1405   /// Advanced:
1406
1407   OUT UINT8   NodeId;              ///< Node ID of current controller
1408   OUT UINT8   SocketId;            ///< Socket ID of this Die
1409   OUT UINT8   DieId;               ///< ID of this die relative to the socket
1410   OUT PCI_ADDR      PciAddr;       ///< Pci bus and device number of this controller.
1411   OUT AGESA_STATUS  ErrCode;       ///< Current error condition of Node
1412                                    ///<  0x0 = AGESA_SUCCESS
1413                                    ///<  0x1 = AGESA_UNSUPPORTED
1414                                    ///<  0x2 = AGESA_BOUNDS_CHK
1415                                    ///<  0x3 = AGESA_ALERT
1416                                    ///<  0x4 = AGESA_WARNING
1417                                    ///<  0x5 = AGESA_ERROR
1418                                    ///<  0x6 = AGESA_CRITICAL
1419                                    ///<  0x7 = AGESA_FATAL
1420                                    ///<
1421   OUT BOOLEAN ErrStatus[EsbEOL];   ///< Error Status bit Field
1422                                    ///<
1423   OUT BOOLEAN Status[SbEOL];       ///< Status bit Field
1424                                    ///<
1425   OUT UINT32  NodeMemSize;         ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
1426                                    ///<
1427   OUT UINT32  NodeSysBase;         ///< Base[47:16] (system address) DRAM base address of this Node.
1428                                    ///<
1429   OUT UINT32  NodeHoleBase;        ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping.  Dram hole exists on this Node
1430                                    ///<
1431   OUT UINT32  NodeSysLimit;        ///< Base[47:16] (system address) DRAM limit address of this Node.
1432                                    ///<
1433   OUT UINT32  DimmPresent;         ///< For each bit n 0..7, 1 = DIMM n is present.
1434                                    ///<   DIMM#  Select Signal
1435                                    ///<   0      MA0_CS_L[0, 1]
1436                                    ///<   1      MB0_CS_L[0, 1]
1437                                    ///<   2      MA1_CS_L[0, 1]
1438                                    ///<   3      MB1_CS_L[0, 1]
1439                                    ///<   4      MA2_CS_L[0, 1]
1440                                    ///<   5      MB2_CS_L[0, 1]
1441                                    ///<   6      MA3_CS_L[0, 1]
1442                                    ///<   7      MB3_CS_L[0, 1]
1443                                    ///<
1444   OUT UINT32  DimmValid;           ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
1445   OUT UINT32  RegDimmPresent;      ///< For each bit n 0..7, 1 = DIMM n is registered DIMM
1446   OUT UINT32  LrDimmPresent;       ///< For each bit n 0..7, 1 = DIMM n is Load Reduced DIMM
1447   OUT UINT32  DimmEccPresent;      ///< For each bit n 0..7, 1 = DIMM n is ECC capable.
1448   OUT UINT32  DimmParPresent;      ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
1449                                    ///<
1450   OUT UINT16  DimmTrainFail;       ///< Bitmap showing which dimms failed training
1451   OUT UINT16  ChannelTrainFail;    ///< Bitmap showing the channel information about failed Chip Selects
1452                                    ///<  0 in any bit field indicates Channel 0
1453                                    ///<  1 in any bit field indicates Channel 1
1454   OUT UINT8   Dct;                 ///<  Need to be removed
1455                                    ///<  DCT pointer
1456   OUT BOOLEAN GangedMode;          ///< Ganged mode
1457                                    ///<  0 = disabled
1458                                    ///<  1 = enabled
1459   OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node
1460                                    ///<
1461   OUT UINT16  HostBiosSrvc1;       ///< UINT16 sized general purpose field for use by host BIOS.  Scratch space.
1462                                    ///<
1463   OUT UINT32  HostBiosSrvc2;       ///< UINT32 sized general purpose field for use by host BIOS.  Scratch space.
1464                                    ///<
1465   OUT UINT8   MLoad;               ///< Need to be removed
1466                                    ///< Number of devices loading MAA bus
1467                                    ///<
1468   OUT UINT8   MaxAsyncLat;         ///< Legacy wrapper
1469                                    ///<
1470   OUT UINT8   ChbD3Rcvrdly;        ///< Legacy wrapper
1471                                    ///<
1472   OUT UINT16  ChaMaxRdLat;         ///< Max Read Latency (ns) for DCT 0
1473                                    ///<
1474   OUT UINT8   ChbD3BcRcvrdly;      ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay
1475
1476   OUT DCT_STRUCT *DctData;         ///< Pointed to a dynamically allocated array of DCT_STRUCTs
1477   OUT UINT8   DctCount;            ///< Number of DCTs per this Die
1478   OUT UINT8   Reserved[16];        ///< Reserved
1479 } DIE_STRUCT;
1480
1481 /**********************************************************************
1482  * S3 Support structure
1483  **********************************************************************/
1484 /// AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
1485 typedef struct {
1486      OUT   UINT32 Signature;           ///< "ASTR" for AMD Suspend-To-RAM
1487      OUT   UINT16 Version;             ///< S3 Params version number
1488   IN OUT   UINT32 Flags;               ///< Indicates operation
1489   IN OUT   VOID   *NvStorage;          ///< Pointer to memory critical save state data
1490   IN OUT   UINT32 NvStorageSize;       ///< Size in bytes of the NvStorage region
1491   IN OUT   VOID   *VolatileStorage;    ///< Pointer to remaining AMD save state data
1492   IN OUT   UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region
1493 } AMD_S3_PARAMS;
1494
1495 ///===============================================================================
1496 /// MEM_PARAMETER_STRUCT
1497 /// This data structure is used to pass wrapper parameters to the memory configuration code
1498 ///
1499 typedef struct _MEM_PARAMETER_STRUCT {
1500
1501   // Basic (Return parameters)
1502   // (This section contains the outbound parameters from the memory init code)
1503
1504   OUT BOOLEAN GStatus[GsbEOL];    ///< Global Status bitfield.
1505                                   ///<
1506   OUT UINT32 HoleBase;            ///< If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
1507                                   ///<
1508   OUT UINT32 Sub4GCacheTop;       ///< If not zero, the 32-bit top of cacheable memory.
1509                                   ///<
1510   OUT UINT32 SysLimit;            ///< Limit[47:16] (system address).
1511                                   ///<
1512
1513   OUT DIMM_VOLTAGE DDR3Voltage;   ///< Find support voltage and send back to platform BIOS.
1514                                   ///< 0 = 1.5v
1515                                   ///< 1 = 1.35v
1516                                   ///< 2 = 1.2v
1517                                   ///< 0xFF = Mixed 1.5V and 1.2V in the system. 1.5V dimms get excluded
1518                                   ///<        from the system.
1519                                   ///<
1520
1521   OUT struct _MEM_DATA_STRUCT *MemData;   ///< Access to global memory init data.
1522
1523   //  Advanced (Optional parameters)
1524   //  Optional (all defaults values will be initialized by the
1525   //  'AmdMemInitDataStructDef' based on AMD defaults. It is up
1526   //  to the IBV/OEM to change the defaults after initialization
1527   //  but prior to the main entry to the memory code):
1528
1529   // Memory Map/Mgt.
1530
1531   IN UINT16  BottomIo;             ///< Bottom of 32-bit IO space (8-bits).
1532                                    ///<   NV_BOTTOM_IO[7:0]=Addr[31:24]
1533                                    ///<
1534   IN BOOLEAN MemHoleRemapping;     ///< Memory Hole Remapping (1-bit).
1535                                    ///<  FALSE = disable
1536                                    ///<  TRUE  = enable
1537
1538
1539   // Dram Timing
1540
1541   IN USER_MEMORY_TIMING_MODE   UserTimingMode;  ///< User Memclock Mode.
1542                                                 ///< @BldCfgItem{BLDCFG_TIMING_MODE_SELECT}
1543
1544   IN MEMORY_BUS_SPEED          MemClockValue;   ///< Memory Clock Value.
1545                                                 ///< @BldCfgItem{BLDCFG_MEMORY_CLOCK_SELECT}
1546
1547
1548   // Dram Configuration
1549
1550   IN BOOLEAN EnableBankIntlv;      ///< Dram Bank (chip-select) Interleaving (1-bit).
1551                                    ///<  - FALSE =disable (default)
1552                                    ///<  - TRUE = enable
1553                                    ///<
1554                                    ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING}
1555
1556   IN BOOLEAN EnableNodeIntlv;      ///< Node Memory Interleaving (1-bit).
1557                                    ///<   - FALSE = disable (default)
1558                                    ///<   - TRUE = enable
1559                                    ///<
1560                                    ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING}
1561
1562   IN BOOLEAN EnableChannelIntlv;   ///< Channel Interleaving (1-bit).
1563                                    ///<   - FALSE = disable (default)
1564                                    ///<   - TRUE = enable
1565                                    ///<
1566                                    ///< @BldCfgItem{BLDCFG_MEMORY_CHANNEL_INTERLEAVING}
1567   // ECC
1568
1569   IN BOOLEAN EnableEccFeature;     ///< enable ECC error to go into MCE.
1570                                    ///<   - FALSE = disable (default)
1571                                    ///<   - TRUE = enable
1572                                    ///<
1573                                    ///< @BldCfgItem{BLDCFG_ENABLE_ECC_FEATURE}
1574   // Dram Power
1575
1576   IN BOOLEAN EnablePowerDown;      ///< CKE based power down mode (1-bit).
1577                                    ///<   - FALSE =disable (default)
1578                                    ///<   - TRUE =enable
1579                                    ///<
1580                                    ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN}
1581
1582   // Online Spare
1583
1584   IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0.
1585                                    ///<  - FALSE = disable Spare (default)
1586                                    ///<  - TRUE = enable Spare
1587                                    ///<
1588                                    ///< @BldCfgItem{BLDCFG_ONLINE_SPARE}
1589
1590   IN UINT8 *TableBasedAlterations; ///< Desired modifications to register settings.
1591
1592   IN PSO_TABLE *PlatformMemoryConfiguration;
1593                                    ///< A table that contains platform specific settings.
1594                                    ///< For example, MemClk routing, the number of DIMM slots per channel, ....
1595                                    ///< AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
1596                                    ///< contains default conservative settings. Platform BIOS can either tweak
1597                                    ///< DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
1598                                    ///<
1599   IN BOOLEAN EnableParity;         ///< Parity control.
1600                                    ///<  - TRUE = enable
1601                                    ///<  - FALSE = disable (default)
1602                                    ///<
1603                                    ///< @BldCfgItem{BLDCFG_MEMORY_PARITY_ENABLE}
1604
1605   IN BOOLEAN EnableBankSwizzle;    ///< BankSwizzle control.
1606                                    ///<  - FALSE = disable
1607                                    ///<  - TRUE = enable  (default)
1608                                    ///<
1609                                    ///< @BldCfgItem{BLDCFG_BANK_SWIZZLE}
1610
1611                                    ///<
1612
1613   IN BOOLEAN EnableMemClr;         ///< Memory Clear functionality control.
1614                                    ///<  - FALSE = disable
1615                                    ///<  - TRUE = enable  (default)
1616                                    ///<
1617
1618   // Uma Configuration
1619
1620   IN UMA_MODE UmaMode;             ///<  Uma Mode
1621                                    ///<  0 = None
1622                                    ///<  1 = Specified
1623                                    ///<  2 = Auto
1624   IN OUT UINT32 UmaSize;           ///<  The size of shared graphics dram (16-bits)
1625                                    ///<  NV_UMA_Size[31:0]=Addr[47:16]
1626                                    ///<
1627   OUT UINT32 UmaBase;              ///<  The allocated Uma base address (32-bits)
1628                                    ///<  NV_UMA_Base[31:0]=Addr[47:16]
1629                                    ///<
1630
1631   /// Memory Restore Feature
1632
1633   IN BOOLEAN MemRestoreCtl;        ///< Memory context restore control
1634                                    ///<   FALSE = perform memory init as normal (AMD default)
1635                                    ///<   TRUE = restore memory context and skip training. This requires
1636                                    ///<          MemContext is valid before AmdInitPost
1637                                    ///<
1638   IN BOOLEAN SaveMemContextCtl;    ///< Control switch to save memory context at the end of MemAuto
1639                                    ///<   TRUE = AGESA will setup MemContext block before exit AmdInitPost
1640                                    ///<   FALSE = AGESA will not setup MemContext block. Platform is
1641                                    ///<           expected to call S3Save later in POST if it wants to
1642                                    ///<           use memory context restore feature.
1643                                    ///<
1644   IN OUT AMD_S3_PARAMS MemContext; ///< Memory context block describes the data that platform needs to
1645                                    ///< save and restore for memory context restore feature to work.
1646                                    ///< It uses the subset of S3Save block to save/restore. Hence platform
1647                                    ///< may save only S3 block and uses it for both S3 resume and
1648                                    ///< memory context restore.
1649                                    ///<  - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
1650                                    ///<    before AmdInitPost.
1651                                    ///<  - If SaveMemContextCtl is TRUE, platform needs to save MemContext
1652                                    ///<    right after AmdInitPost.
1653                                    ///<
1654 } MEM_PARAMETER_STRUCT;
1655
1656
1657 ///
1658 /// Function definition.
1659 /// This data structure passes function pointers to the memory configuration code.
1660 /// The wrapper can use this structure with customized versions.
1661 ///
1662 typedef struct _MEM_FUNCTION_STRUCT {
1663
1664   // PUBLIC required Internal functions
1665
1666   IN OUT BOOLEAN (*amdMemGetPsCfgU) ( VOID *pMemData);  ///< Proc for Unbuffered DIMMs, platform specific
1667   IN OUT BOOLEAN (*amdMemGetPsCfgR) (VOID *pMemData);   ///< Proc for Registered DIMMs, platform specific
1668
1669   // PUBLIC optional functions
1670
1671   IN OUT VOID (*amdMemEccInit) (VOID *pMemData);                  ///< NB proc for ECC feature
1672   IN OUT VOID (*amdMemChipSelectInterleaveInit) (VOID *pMemData); ///< NB proc for CS interleave feature
1673   IN OUT VOID (*amdMemDctInterleavingInit) (VOID *pMemData);      ///< NB proc for Channel interleave feature
1674   IN OUT VOID (*amdMemMctInterleavingInit) (VOID *pMemData);      ///< NB proc for Node interleave feature
1675   IN OUT VOID (*amdMemParallelTraining) (VOID *pMemData);         ///< NB proc for parallel training feature
1676   IN OUT VOID (*amdMemEarlySampleSupport) (VOID *pMemData);       ///< NB code for early sample support feature
1677   IN OUT VOID (*amdMemMultiPartInitSupport) (VOID *pMemData);     ///< NB code for 'multi-part'
1678   IN OUT VOID (*amdMemOnlineSpareSupport) (VOID *pMemData);       ///< NB code for On-Line Spare feature
1679   IN OUT VOID (*amdMemUDimmInit) (VOID *pMemData);                ///< NB code for UDIMMs
1680   IN OUT VOID (*amdMemRDimmInit) (VOID *pMemData);                ///< NB code for RDIMMs
1681   IN OUT VOID (*amdMemLrDimmInit) (VOID *pMemData);                ///< NB code for LRDIMMs
1682
1683   IN OUT UINT32   Reserved[100]; ///< Reserved for later function definition
1684 } MEM_FUNCTION_STRUCT;
1685
1686 ///
1687 /// Socket Structure
1688 ///
1689 ///
1690 typedef struct _MEM_SOCKET_STRUCT {
1691   OUT VOID *ChannelPtr[MAX_CHANNELS_PER_SOCKET];  ///< Pointers to each channels training data
1692
1693   OUT VOID *TimingsPtr[MAX_CHANNELS_PER_SOCKET];  ///< Pointers to each channels timing data
1694 } MEM_SOCKET_STRUCT;
1695
1696 ///
1697 /// Contains all data relevant to Memory Initialization.
1698 ///
1699 typedef struct _MEM_DATA_STRUCT {
1700   IN AMD_CONFIG_PARAMS StdHeader;             ///< Standard configuration header
1701
1702   IN MEM_PARAMETER_STRUCT *ParameterListPtr;  ///< List of input Parameters
1703
1704   OUT MEM_FUNCTION_STRUCT FunctionList;       ///< List of function Pointers
1705
1706   IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info
1707
1708   IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling
1709
1710
1711   OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED];  ///< Socket list for memory code.
1712                                    ///< SocketList is a shortcut for IBVs to retrieve training
1713                                    ///< and timing data for each channel indexed by socket/channel,
1714                                    ///< eliminating their need to parse die/dct/channel etc.
1715                                    ///< It contains pointers to the populated data structures for
1716                                    ///< each channel and skips the channel structures that are
1717                                    ///< unpopulated. In the case of channels sharing the same DCT,
1718                                    ///< the pTimings pointers will point to the same DCT Timing data.
1719
1720   OUT DIE_STRUCT *DiesPerSystem;  ///< Pointed to an array of DIE_STRUCTs
1721   OUT UINT8      DieCount;        ///< Number of MCTs in the system.
1722
1723   IN SPD_DEF_STRUCT *SpdDataStructure;              ///< Pointer to SPD Data structure
1724
1725   IN OUT  struct _PLATFORM_CONFIGURATION   *PlatFormConfig;    ///< Platform profile/build option config structure
1726
1727   IN OUT BOOLEAN IsFlowControlSupported;    ///< Indicates if flow control is supported
1728
1729   OUT UINT32 TscRate;             ///< The rate at which the TSC increments in megahertz.
1730
1731 } MEM_DATA_STRUCT;
1732
1733 ///
1734 /// Uma Structure
1735 ///
1736 ///
1737 typedef struct _UMA_INFO {
1738   OUT UINT64 UmaBase;          ///< UmaBase[63:0] = Addr[63:0]
1739   OUT UINT32 UmaSize;          ///< UmaSize[31:0] = Addr[31:0]
1740   OUT UINT32 UmaAttributes;    ///< Indicate the attribute of Uma
1741   OUT UINT8 UmaMode;           ///< Indicate the mode of Uma
1742   OUT UINT16 MemClock;         ///< Indicate memory running speed in MHz
1743   OUT UINT8 Reserved[3];       ///< Reserved for future usage
1744 } UMA_INFO;
1745
1746 //  AGESA MEMORY ERRORS
1747
1748 // AGESA_ALERT Memory Errors
1749 #define MEM_ALERT_USER_TMG_MODE_OVERRULED   0x04010000 ///< TIMING_MODE_SPECIFIC is requested but
1750                                                        ///< cannot be applied to current configurations.
1751 #define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100          ///< DIMM organization miss-match
1752 #define MEM_ALERT_BK_INT_DIS 0x04010200                 ///< Bank interleaving disable for internal issue
1753
1754 // AGESA_ERROR Memory Errors
1755 #define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300     ///< No DQS Position window for RD DQS
1756 #define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300  ///< Small DQS Position window for RD DQS
1757 #define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300     ///< No DQS Position window for WR DQS
1758 #define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300  ///< Small DQS Position window for WR DQS
1759 #define MEM_ERROR_ECC_DIS 0x04010400                  ///< ECC has been disabled as a result of an internal issue
1760 #define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500 ///< DIMM sparing has not been enabled for an internal issues
1761 #define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300 ///< Receive Enable value is too large
1762 #define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300 ///< There is no DQS receiver enable window
1763 #define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600 ///< Time out when polling DramEnabled bit
1764 #define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700 ///< Time out when polling DctAccessDone bit
1765 #define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800 ///< Time out when polling SendCtrlWord bit
1766 #define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900 ///< Time out when polling PrefDramTrainMode bit
1767 #define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00 ///< Time out when polling EnterSelfRef bit
1768 #define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00 ///< Time out when polling FreqChgInProg bit
1769 #define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00 ///< Time out when polling ExitSelfRef bit
1770 #define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00 ///< Time out when polling SendMrsCmd bit
1771 #define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00 ///< Time out when polling SendZQCmd bit
1772 #define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00 ///< Time out when polling DctExtraAccessDone bit
1773 #define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00 ///< Time out when polling MemClrBusy bit
1774 #define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00 ///< Time out when polling MemCleared bit
1775 #define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000 ///< Time out when polling FlushWr bit
1776 #define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300 ///< Fail to find pass during Max Rd Latency training
1777 #define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300 ///< Fail to launch training code on an AP
1778 #define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300 ///< Fail to finish parallel training
1779 #define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100 ///< No address mapping found for a dimm
1780 #define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT  0x040A0300 ///< There is no DQS receiver enable window and the value is equal to the largest value
1781 #define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300 ///< Receive Enable value is too large and is 1 less than limit
1782 #define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR  0x04011200    ///< SPD Checksum error for NV_SPDCHK_RESTRT
1783 #define MEM_ERROR_NO_CHIPSELECT 0x04011300              ///< No chipselects found
1784 #define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500   ///< Unbuffered dimm is not supported at 333MHz
1785 #define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x040C0300   ///< Returned PRE value during write levelizzation was out of range
1786
1787 // AGESA_WARNING Memory Errors
1788 #define MEM_WARNING_UNSUPPORTED_QRDIMM      0x04011600 ///< QR DIMMs detected but not supported
1789 #define MEM_WARNING_UNSUPPORTED_UDIMM       0x04021600 ///< U DIMMs detected but not supported
1790 #define MEM_WARNING_UNSUPPORTED_SODIMM      0x04031600 ///< SO-DIMMs detected but not supported
1791 #define MEM_WARNING_UNSUPPORTED_X4DIMM      0x04041600 ///< x4 DIMMs detected but not supported
1792 #define MEM_WARNING_UNSUPPORTED_RDIMM       0x04051600 ///< R DIMMs detected but not supported
1793 #define MEM_WARNING_UNSUPPORTED_LRDIMM      0x04061600 ///< LR DIMMs detected but not supported
1794 #define MEM_WARNING_EMP_NOT_SUPPORTED       0x04011700 ///< Processor is not capable for EMP
1795 #define MEM_WARNING_EMP_CONFLICT            0x04021700  ///< EMP cannot be enabled if channel interleaving,
1796 #define MEM_WARNING_EMP_NOT_ENABLED         0x04031700  ///< Memory size is not power of two.
1797 #define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800  ///< Performance has been enabled, but battery life is preferred.
1798                                                         ///< bank interleaving, or bank swizzle is enabled.
1799 #define MEM_WARNING_NO_SPDTRC_FOUND         0x04011900  ///< No Trc timing value found in SPD of a dimm.
1800 #define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000    ///< Node Interleaveing Requested, but could not be enabled
1801 #define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100 ///< Channel Interleaveing Requested, but could not be enabled
1802 #define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200 ///< Bank Interleaveing Requested, but could not be enabled
1803 #define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300 ///< Voltage 1.35 determined, but could not be supported
1804
1805 // AGESA_FATAL Memory Errors
1806 #define MEM_ERROR_MINIMUM_MODE 0x04011A00               ///< Running in minimum mode
1807 #define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00  ///< DIMM modules are miss-matched
1808 #define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00    ///< No DIMMs have been found
1809 #define MEM_ERROR_MISMATCH_DIMM_CLOCKS  0x04011D00      ///< DIMM clocks miss-matched
1810 #define MEM_ERROR_NO_CYC_TIME 0x04011E00                ///< No cycle time found
1811 #define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS   0x04011F00 ///< Heap allocation error with dynamic storing of trained timings
1812 #define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs   0x04021F00 ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
1813 #define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV   0x04031F00 ///< Heap allocation error with REMOTE_TRAINING_ENV
1814 #define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD     0x04041F00    ///< Heap allocation error for SPD data
1815 #define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA     0x04051F00    ///< Heap allocation error for RECEIVED_DATA during parallel training
1816 #define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS     0x04061F00    ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
1817 #define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA     0x04071F00   ///< Heap allocation error for Training Data
1818 #define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK     0x04081F00    ///< Heap allocation error for  DIMM Identify "MEM_NB_BLOCK
1819 #define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM     0x04022300   ///< No Constructor for DIMM Identify
1820
1821 // AGESA_CRITICAL Memory Errors
1822 #define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3     0x04091F00    ///< Heap allocation error for DMI table for DDR3
1823 #define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2     0x040A1F00    ///< Heap allocation error for DMI table for DDR2
1824 #define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG              0x04011400    ///< Dimm population is not supported
1825
1826
1827
1828 /*----------------------------------------------------------------------------
1829  *
1830  *                END OF MEMORY-SPECIFIC DATA STRUCTURES
1831  *
1832  *----------------------------------------------------------------------------
1833  */
1834
1835
1836
1837
1838 /*----------------------------------------------------------------------------
1839  *
1840  *                    CPU RELATED DEFINITIONS
1841  *
1842  *----------------------------------------------------------------------------
1843  */
1844
1845 // CPU Event definitions.
1846
1847 // Defines used to filter CPU events based on functional blocks
1848 #define CPU_EVENT_PM_EVENT_MASK                         0xFF00FF00
1849 #define CPU_EVENT_PM_EVENT_CLASS                        0x08000400
1850
1851 //================================================================
1852 // CPU General events
1853 //    Heap allocation                     (AppFunction =      01h)
1854 #define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT            0x08000100
1855 #define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED           0x08010100
1856 #define CPU_ERROR_HEAP_IS_FULL                          0x08020100
1857 #define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED    0x08030100
1858 #define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT     0x08040100
1859 //    BrandId                             (AppFunction =      02h)
1860 #define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE            0x08000200
1861 //    Micro code patch                    (AppFunction =      03h)
1862 #define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED        0x08000300
1863 //    Power management                    (AppFunction =      04h)
1864 #define CPU_EVENT_PM_PSTATE_OVERCURRENT                 0x08000400
1865 #define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT             0x08010400
1866 #define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE             0x08020400
1867 #define CPU_ERROR_PM_NB_PSTATE_MISMATCH                 0x08030400
1868 //    BIST                                (AppFunction =      05h)
1869 #define CPU_EVENT_BIST_ERROR                            0x08000500
1870
1871 //=================================================================
1872 // CPU Feature events
1873 //    Execution cache                     (AppFunction =      21h)
1874 //        AGESA_CACHE_SIZE_REDUCED                            2101
1875 //        AGESA_CACHE_REGIONS_ACROSS_1MB                      2102
1876 //        AGESA_CACHE_REGIONS_ACROSS_4GB                      2103
1877 //        AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY                2104
1878 //        AGESA_CACHE_START_ADDRESS_LESS_D0000                2105
1879 //        AGESA_THREE_CACHE_REGIONS_ABOVE_1MB                 2106
1880 //        AGESA_DEALLOCATE_CACHE_REGIONS                      2107
1881 #define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR      0x08002100
1882 //    Core Leveling                       (AppFunction =      22h)
1883 #define CPU_WARNING_ADJUSTED_LEVELING_MODE              0x08002200
1884 //    HT Assist                           (AppFunction =      23h)
1885 #define CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG            0x08002300
1886
1887 // CPU Build Configuration structures and definitions
1888
1889 /// Build Configuration structure for BLDCFG_AP_MTRR_SETTINGS
1890 typedef struct {
1891   IN  UINT32 MsrAddr;     ///< Fixed-Sized MTRR address
1892   IN  UINT64 MsrData;     ///< MTRR Settings
1893 } AP_MTRR_SETTINGS;
1894
1895 #define AMD_AP_MTRR_FIX64k_00000    0x00000250
1896 #define AMD_AP_MTRR_FIX16k_80000    0x00000258
1897 #define AMD_AP_MTRR_FIX16k_A0000    0x00000259
1898 #define AMD_AP_MTRR_FIX4k_C0000     0x00000268
1899 #define AMD_AP_MTRR_FIX4k_C8000     0x00000269
1900 #define AMD_AP_MTRR_FIX4k_D0000     0x0000026A
1901 #define AMD_AP_MTRR_FIX4k_D8000     0x0000026B
1902 #define AMD_AP_MTRR_FIX4k_E0000     0x0000026C
1903 #define AMD_AP_MTRR_FIX4k_E8000     0x0000026D
1904 #define AMD_AP_MTRR_FIX4k_F0000     0x0000026E
1905 #define AMD_AP_MTRR_FIX4k_F8000     0x0000026F
1906 #define CPU_LIST_TERMINAL           0xFFFFFFFF
1907
1908 /************************************************************************
1909  *
1910  *  AGESA interface Call-Out function parameter structures
1911  *
1912  ***********************************************************************/
1913
1914 /// Parameters structure for interface call-out AgesaAllocateBuffer
1915 typedef struct {
1916   IN OUT    AMD_CONFIG_PARAMS   StdHeader;      ///< Standard configuration header
1917   IN OUT    UINT32              BufferLength;   ///< Size of buffer to allocate
1918   IN        UINT32              BufferHandle;   ///< Identifier or name for the buffer
1919   OUT       VOID                *BufferPointer; ///< location of the created buffer
1920 } AGESA_BUFFER_PARAMS;
1921
1922 /// Parameters structure for interface call-out AgesaRunCodeOnAp
1923 typedef struct {
1924   IN OUT    AMD_CONFIG_PARAMS   StdHeader;            ///< Standard configuration header
1925   IN        UINT32              FunctionNumber;       ///< Index of the procedure to execute
1926   IN        VOID                *RelatedDataBlock;    ///< Location of data structure the procedure will use
1927   IN        UINT32              RelatedBlockLength;   ///< Size of the related data block
1928 } AP_EXE_PARAMS;
1929
1930 /// Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
1931 typedef struct {
1932   IN OUT    AMD_CONFIG_PARAMS   StdHeader;      ///< Standard configuration header
1933   IN        UINT8               SocketId;       ///< Address of SPD - socket ID
1934   IN        UINT8               MemChannelId;   ///< Address of SPD - memory channel ID
1935   IN        UINT8               DimmId;         ///< Address of SPD - DIMM ID
1936   IN OUT    UINT8               *Buffer;        ///< Location where to place the SPD content
1937   IN OUT    MEM_DATA_STRUCT     *MemData;       ///< Location of the MemData structure, for reference
1938 } AGESA_READ_SPD_PARAMS;
1939
1940 /// Buffer Handles
1941 typedef enum {
1942   AMD_DMI_INFO_BUFFER_HANDLE = 0x000D000,       ///< Assign 0x000D000 buffer handle to DMI function
1943   AMD_PSTATE_DATA_BUFFER_HANDLE,                ///< Assign 0x000D001 buffer handle to Pstate data
1944   AMD_PSTATE_ACPI_BUFFER_HANDLE,                ///< Assign 0x000D002 buffer handle to Pstate table
1945   AMD_BRAND_ID_BUFFER_HANDLE,                   ///< Assign 0x000D003 buffer handle to Brand ID
1946   AMD_ACPI_SLIT_BUFFER_HANDLE,                  ///< Assign 0x000D004 buffer handle to SLIT function
1947   AMD_SRAT_INFO_BUFFER_HANDLE,                  ///< Assign 0x000D005 buffer handle to SRAT function
1948   AMD_WHEA_BUFFER_HANDLE,                       ///< Assign 0x000D006 buffer handle to WHEA function
1949   AMD_S3_INFO_BUFFER_HANDLE,                    ///< Assign 0x000D007 buffer handle to S3 function
1950   AMD_S3_NB_INFO_BUFFER_HANDLE,                 ///< Assign 0x000D008 buffer handle to S3 NB device info
1951   AMD_ACPI_ALIB_BUFFER_HANDLE                   ///< Assign 0x000D009 buffer handle to ALIB SSDT table
1952 } AMD_BUFFER_HANDLE;
1953 /************************************************************************
1954  *
1955  *  AGESA interface Call-Out function prototypes
1956  *
1957  ***********************************************************************/
1958
1959 VOID
1960 AgesaDoReset (
1961   IN        UINTN               ResetType,
1962   IN OUT    AMD_CONFIG_PARAMS   *StdHeader
1963   );
1964
1965 AGESA_STATUS
1966 AgesaAllocateBuffer (
1967   IN      UINTN                 FcnData,
1968   IN OUT  AGESA_BUFFER_PARAMS   *AllocParams
1969   );
1970
1971 AGESA_STATUS
1972 AgesaDeallocateBuffer (
1973   IN      UINTN                 FcnData,
1974   IN OUT  AGESA_BUFFER_PARAMS   *DeallocParams
1975   );
1976
1977 AGESA_STATUS
1978 AgesaLocateBuffer (
1979   IN      UINTN                 FcnData,
1980   IN OUT  AGESA_BUFFER_PARAMS   *LocateParams
1981   );
1982
1983 AGESA_STATUS
1984 AgesaReadSpd (
1985   IN        UINTN                 FcnData,
1986   IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
1987   );
1988
1989 AGESA_STATUS
1990 AgesaReadSpdRecovery (
1991   IN        UINTN                 FcnData,
1992   IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
1993   );
1994
1995 AGESA_STATUS
1996 AgesaHookBeforeDramInitRecovery (
1997   IN       UINTN           FcnData,
1998   IN OUT   MEM_DATA_STRUCT *MemData
1999   );
2000
2001 AGESA_STATUS
2002 AgesaRunFcnOnAp (
2003   IN        UINTN               ApicIdOfCore,
2004   IN        AP_EXE_PARAMS       *LaunchApParams
2005   );
2006
2007 AGESA_STATUS
2008 AgesaHookBeforeDramInit (
2009   IN        UINTN               FcnData,
2010   IN OUT    MEM_DATA_STRUCT     *MemData
2011   );
2012
2013 AGESA_STATUS
2014 AgesaHookBeforeDQSTraining (
2015   IN        UINTN               FcnData,
2016   IN OUT    MEM_DATA_STRUCT     *MemData
2017   );
2018
2019 AGESA_STATUS
2020 AgesaHookBeforeExitSelfRefresh (
2021   IN        UINTN               FcnData,
2022   IN OUT    MEM_DATA_STRUCT     *MemData
2023   );
2024
2025 AGESA_STATUS
2026 AgesaPcieSlotResetControl (
2027   IN      UINTN                 FcnData,
2028   IN      PCIe_SLOT_RESET_INFO  *ResetInfo
2029  );
2030
2031 /************************************************************************
2032  *
2033  *  AGESA interface structure definition and function prototypes
2034  *
2035  ***********************************************************************/
2036
2037 /**********************************************************************
2038  * Platform Configuration:  The parameters in boot branch function
2039  **********************************************************************/
2040
2041 ///  The possible platform control flow settings.
2042 typedef enum  {
2043   Nfcm,                                          ///< Normal Flow Control Mode.
2044   UmaDr,                                         ///< UMA using Display Refresh flow control.
2045   UmaIfcm,                                       ///< UMA using Isochronous Flow Control.
2046   Ifcm,                                          ///< Isochronous Flow Control Mode (other than for UMA).
2047   Iommu,                                         ///< An IOMMU is in use in the system.
2048   MaxControlFlow                                 ///< Not a control flow mode, use for limit checking.
2049 } PLATFORM_CONTROL_FLOW;
2050
2051 ///  Platform Deemphasis Levels.
2052 ///
2053 /// The deemphasis level is set for the receiver, based on link characterization.  The DCV level is
2054 /// set based on the level of the far transmitter.
2055 typedef enum {
2056   DeemphasisLevelNone,                           ///< No Deemphasis.
2057   DeemphasisLevelMinus3,                         ///< Minus 3 db deemphasis.
2058   DeemphasisLevelMinus6,                         ///< Minus 6 db deemphasis.
2059   DeemphasisLevelMinus8,                         ///< Minus 8 db deemphasis.
2060   DeemphasisLevelMinus11,                        ///< Minus 11 db deemphasis.
2061   DeemphasisLevelMinus11pre8,                    ///< Minus 11, Minus 8 precursor db deemphasis.
2062   DcvLevelNone = 16,                             ///< No DCV Deemphasis.
2063   DcvLevelMinus2,                                ///< Minus 2 db DCV deemphasis.
2064   DcvLevelMinus3,                                ///< Minus 3 db DCV deemphasis.
2065   DcvLevelMinus5,                                ///< Minus 5 db DCV deemphasis.
2066   DcvLevelMinus6,                                ///< Minus 6 db DCV deemphasis.
2067   DcvLevelMinus7,                                ///< Minus 7 db DCV deemphasis.
2068   DcvLevelMinus8,                                ///< Minus 8 db DCV deemphasis.
2069   DcvLevelMinus9,                                ///< Minus 9 db DCV deemphasis.
2070   DcvLevelMinus11,                               ///< Minus 11 db DCV deemphasis.
2071   MaxPlatformDeemphasisLevel                     ///< Not a deemphasis level, use for limit checking.
2072 } PLATFORM_DEEMPHASIS_LEVEL;
2073
2074 ///  Provide Deemphasis Levels for HT Links.
2075 ///
2076 ///  For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will
2077 ///  be checked for a match.  The item matches for a Socket, Link if the link frequency is
2078 ///  is in the inclusive range HighFreq:LoFreq.
2079 ///  AGESA does not set deemphasis in IO devices, only in processors.
2080
2081 typedef struct {
2082   // Match fields
2083   IN       UINT8 Socket;                                        ///< One Socket on which this Link is located
2084   IN       UINT8 Link;                                          ///< The Link on this Processor.
2085   IN       UINT8 LoFreq;                                        ///< If the link is set to this frequency or greater, apply these levels, and
2086   IN       UINT8 HighFreq;                                      ///< If the link is set to this frequency or less, apply these levels.
2087   // Value fields
2088   IN       PLATFORM_DEEMPHASIS_LEVEL     ReceiverDeemphasis;    ///< The deemphasis level for this link
2089   IN       PLATFORM_DEEMPHASIS_LEVEL     DcvDeemphasis;         ///< The DCV, or far transmitter deemphasis level.
2090 } CPU_HT_DEEMPHASIS_LEVEL;
2091
2092 ///  The possible platform power policy settings.
2093 typedef enum  {
2094   Performance,                                   ///< Optimize for performance.
2095   BatteryLife,                                   ///< Optimize for battery life.
2096   MaxPowerPolicy                                 ///< Not a power policy mode, use for limit checking.
2097 } PLATFORM_POWER_POLICY;
2098
2099 ///  Platform performance settings for optimized settings.
2100 ///  Several configuration settings for the processor depend upon other parts and
2101 ///  general designer choices for the system. The determination of these data points
2102 ///  is not standard for all platforms, so the host environment needs to provide these
2103 ///  to specify how the system is to be configured.
2104 typedef struct {
2105   IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode;    ///< The platform's control flow mode for optimum platform performance.
2106                                                        ///< @BldCfgItem{BLDCFG_PLATFORM_CONTROL_FLOW_MODE}
2107   IN BOOLEAN               UseHtAssist;                ///< HyperTransport link traffic optimization.
2108                                                        ///< @BldCfgItem{BLDCFG_USE_HT_ASSIST}
2109   IN BOOLEAN               UseAtmMode;                 ///< HyperTransport link traffic optimization.
2110                                                        ///< @BldCfgItem{BLDCFG_USE_ATM_MODE}
2111   IN BOOLEAN               Use32ByteRefresh;           ///< Display Refresh traffic generates 32 byte requests.
2112                                                        ///< @BldCfgItem{BLDCFG_USE_32_BYTE_REFRESH}
2113   IN BOOLEAN               UseVariableMctIsocPriority; ///< The Memory controller will be set to Variable Isoc Priority.
2114                                                        ///< @BldCfgItem{BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY}
2115   IN PLATFORM_POWER_POLICY PlatformPowerPolicy;        ///< The platform's desired power policy
2116                                                        ///< @BldCfgItem{BLDCFG_PLATFORM_POWER_POLICY_MODE}
2117 } PERFORMANCE_PROFILE;
2118
2119 ///  Platform settings that describe the voltage regulator modules of the system.
2120 ///  Many power management settings are dependent upon the characteristics of the
2121 ///  on-board voltage regulator module (VRM).  The host environment needs to provide
2122 ///  these to specify how the system is to be configured.
2123 typedef struct {
2124   IN UINT32  CurrentLimit;                         ///< Vrm Current Limit.
2125                                                    ///< @BldCfgItem{BLDCFG_VRM_CURRENT_LIMIT}
2126                                                    ///< @BldCfgItem{BLDCFG_VRM_NB_CURRENT_LIMIT}
2127   IN UINT32  LowPowerThreshold;                    ///< Vrm Low Power Threshold.
2128                                                    ///< @BldCfgItem{BLDCFG_VRM_LOW_POWER_THRESHOLD}
2129                                                    ///< @BldCfgItem{BLDCFG_VRM_NB_LOW_POWER_THRESHOLD}
2130   IN UINT32  SlewRate;                             ///< Vrm Slew Rate.
2131                                                    ///< @BldCfgItem{BLDCFG_VRM_SLEW_RATE}
2132                                                    ///< @BldCfgItem{BLDCFG_VRM_NB_SLEW_RATE}
2133   IN UINT32  AdditionalDelay;                      ///< Vrm Additional Delay.
2134                                                    ///< @BldCfgItem{BLDCFG_VRM_ADDITIONAL_DELAY}
2135                                                    ///< @BldCfgItem{BLDCFG_VRM_NB_ADDITIONAL_DELAY}
2136   IN BOOLEAN HiSpeedEnable;                        ///< Select high speed VRM.
2137                                                    ///< @BldCfgItem{BLDCFG_VRM_HIGH_SPEED_ENABLE}
2138                                                    ///< @BldCfgItem{BLDCFG_VRM_NB_HIGH_SPEED_ENABLE}
2139   IN UINT32  InrushCurrentLimit;                   ///< Vrm Inrush Current Limit.
2140                                                    ///< @BldCfgItem{BLDCFG_VRM_INRUSH_CURRENT_LIMIT}
2141                                                    ///< @BldCfgItem{BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT}
2142 } PLATFORM_VRM_CONFIGURATION;
2143
2144 ///  The VRM types to characterize.
2145 typedef enum  {
2146   CoreVrm,                                       ///< VDD plane.
2147   NbVrm,                                         ///< VDDNB plane.
2148   MaxVrmType                                     ///< Not a valid VRM type, use for limit checking.
2149 } PLATFORM_VRM_TYPE;
2150
2151
2152 /// Build Option/Configuration Boolean Structure.
2153 typedef struct {
2154   IN  AMD_CODE_HEADER VersionString;              ///< AMD embedded code version string
2155
2156   //Build Option Area
2157   IN BOOLEAN OptionUDimms;                        ///< @ref BLDOPT_REMOVE_UDIMMS_SUPPORT "BLDOPT_REMOVE_UDIMMS_SUPPORT"
2158   IN BOOLEAN OptionRDimms;                        ///< @ref BLDOPT_REMOVE_RDIMMS_SUPPORT "BLDOPT_REMOVE_RDIMMS_SUPPORT"
2159   IN BOOLEAN OptionLrDimms;                      ///< @ref BLDOPT_REMOVE_LRDIMMS_SUPPORT "BLDOPT_REMOVE_LRDIMMS_SUPPORT"
2160   IN BOOLEAN OptionEcc;                           ///< @ref BLDOPT_REMOVE_ECC_SUPPORT "BLDOPT_REMOVE_ECC_SUPPORT"
2161   IN BOOLEAN OptionBankInterleave;                ///< @ref BLDOPT_REMOVE_BANK_INTERLEAVE "BLDOPT_REMOVE_BANK_INTERLEAVE"
2162   IN BOOLEAN OptionDctInterleave;                 ///< @ref BLDOPT_REMOVE_DCT_INTERLEAVE "BLDOPT_REMOVE_DCT_INTERLEAVE"
2163   IN BOOLEAN OptionNodeInterleave;                ///< @ref BLDOPT_REMOVE_NODE_INTERLEAVE "BLDOPT_REMOVE_NODE_INTERLEAVE"
2164   IN BOOLEAN OptionParallelTraining;              ///< @ref BLDOPT_REMOVE_PARALLEL_TRAINING "BLDOPT_REMOVE_PARALLEL_TRAINING"
2165   IN BOOLEAN OptionOnlineSpare;                   ///< @ref BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT "BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT"
2166   IN BOOLEAN OptionMemRestore;                    ///< @ref BLDOPT_REMOVE_MEM_RESTORE_SUPPORT "BLDOPT_REMOVE_MEM_RESTORE_SUPPORT"
2167   IN BOOLEAN OptionMultisocket;                   ///< @ref BLDOPT_REMOVE_MULTISOCKET_SUPPORT "BLDOPT_REMOVE_MULTISOCKET_SUPPORT"
2168   IN BOOLEAN OptionAcpiPstates;                   ///< @ref BLDOPT_REMOVE_ACPI_PSTATES "BLDOPT_REMOVE_ACPI_PSTATES"
2169   IN BOOLEAN OptionSrat;                          ///< @ref BLDOPT_REMOVE_SRAT "BLDOPT_REMOVE_SRAT"
2170   IN BOOLEAN OptionSlit;                          ///< @ref BLDOPT_REMOVE_SLIT "BLDOPT_REMOVE_SLIT"
2171   IN BOOLEAN OptionWhea;                          ///< @ref BLDOPT_REMOVE_WHEA "BLDOPT_REMOVE_WHEA"
2172   IN BOOLEAN OptionDmi;                           ///< @ref BLDOPT_REMOVE_DMI "BLDOPT_REMOVE_DMI"
2173   IN BOOLEAN OptionEarlySamples;                  ///< @ref BLDOPT_REMOVE_EARLY_SAMPLES "BLDOPT_REMOVE_EARLY_SAMPLES"
2174   IN BOOLEAN OptionAddrToCsTranslator;            ///< ADDR_TO_CS_TRANSLATOR
2175
2176   //Build Configuration Area
2177   IN UINT64 CfgPciMmioAddress;                    ///< Pci Mmio Base Address to use for PCI Config accesses.
2178                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_BASE}
2179   IN UINT32 CfgPciMmioSize;                       ///< Pci Mmio region Size.
2180                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_SIZE}
2181   IN PLATFORM_VRM_CONFIGURATION CfgPlatVrmCfg[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
2182   IN UINT32 CfgPlatNumIoApics;                    ///< The number of IO APICS for the platform.
2183   IN UINT32 CfgMemInitPstate;                     ///< Memory Init Pstate.
2184   IN PLATFORM_C1E_MODES CfgPlatformC1eMode;       ///< Select the C1e Mode that will used.
2185   IN UINT32 CfgPlatformC1eOpData;                 ///< An IO port or additional C1e setup data, depends on C1e mode.
2186   IN UINT32 CfgPlatformC1eOpData1;                ///< An IO port or additional C1e setup data, depends on C1e mode.
2187   IN UINT32 CfgPlatformC1eOpData2;                ///< An IO port or additional C1e setup data, depends on C1e mode.
2188   IN PLATFORM_CSTATE_MODES CfgPlatformCStateMode; ///< Select the C-State Mode that will used.
2189   IN UINT32 CfgPlatformCStateOpData;              ///< An IO port or additional C-State setup data, depends on C-State mode.
2190   IN UINT16 CfgPlatformCStateIoBaseAddress;       ///< Specifies I/O ports that can be used to allow CPU to enter CStates
2191   IN PLATFORM_CPB_MODES CfgPlatformCpbMode;       ///< Enable or disable core performance boost
2192   IN UINT32 CfgCoreLevelingMode;                  ///< Apply any downcoring or core count leveling as specified.
2193   IN PERFORMANCE_PROFILE CfgPerformanceProfile;   ///< The platform's control flow mode and platform performance settings.
2194   IN CPU_HT_DEEMPHASIS_LEVEL *CfgPlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
2195
2196   IN UINT32 CfgAmdPlatformType;                   ///< Designate the platform as a Server, Desktop, or Mobile.
2197   IN UINT32 CfgAmdPstateCapValue;                 ///< Amd pstate ceiling enabling deck
2198
2199   IN MEMORY_BUS_SPEED CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit.
2200                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT}
2201   IN BOOLEAN CfgMemoryModeUnganged;               ///< Memory Mode Unganged.
2202                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED}
2203   IN BOOLEAN CfgMemoryQuadRankCapable;            ///< Memory Quad Rank Capable.
2204                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE}
2205   IN QUANDRANK_TYPE CfgMemoryQuadrankType;        ///< Memory Quadrank Type.
2206                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUADRANK_TYPE}
2207   IN BOOLEAN CfgMemoryRDimmCapable;               ///< Memory RDIMM Capable.
2208   IN BOOLEAN CfgMemoryLRDimmCapable;              ///< Memory LRDIMM Capable.
2209   IN BOOLEAN CfgMemoryUDimmCapable;               ///< Memory UDIMM Capable.
2210   IN BOOLEAN CfgMemorySODimmCapable;              ///< Memory SODimm Capable.
2211                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE}
2212   IN BOOLEAN CfgMemoryEnableBankInterleaving;     ///< Memory Enable Bank Interleaving.
2213   IN BOOLEAN CfgMemoryEnableNodeInterleaving;     ///< Memory Enable Node Interleaving.
2214   IN BOOLEAN CfgMemoryChannelInterleaving;        ///< Memory Channel Interleaving.
2215   IN BOOLEAN CfgMemoryPowerDown;                  ///< Memory Power Down.
2216   IN POWER_DOWN_MODE CfgPowerDownMode;            ///< Power Down Mode.
2217   IN BOOLEAN CfgOnlineSpare;                      ///< Online Spare.
2218   IN BOOLEAN CfgMemoryParityEnable;               ///< Memory Parity Enable.
2219   IN BOOLEAN CfgBankSwizzle;                      ///< Bank Swizzle.
2220   IN USER_MEMORY_TIMING_MODE CfgTimingModeSelect; ///< Timing Mode Select.
2221   IN MEMORY_BUS_SPEED CfgMemoryClockSelect;       ///< Memory Clock Select.
2222   IN BOOLEAN CfgDqsTrainingControl;               ///< Dqs Training Control.
2223                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL}
2224   IN BOOLEAN CfgIgnoreSpdChecksum;                ///< Ignore Spd Checksum.
2225                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM}
2226   IN BOOLEAN CfgUseBurstMode;                     ///< Use Burst Mode.
2227                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_USE_BURST_MODE}
2228   IN BOOLEAN CfgMemoryAllClocksOn;                ///< Memory All Clocks On.
2229                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON}
2230   IN BOOLEAN CfgEnableEccFeature;                 ///< Enable ECC Feature.
2231   IN BOOLEAN CfgEccRedirection;                   ///< ECC Redirection.
2232                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION}
2233   IN UINT16  CfgScrubDramRate;                    ///< Scrub Dram Rate.
2234                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE}
2235   IN UINT16  CfgScrubL2Rate;                      ///< Scrub L2Rate.
2236                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE}
2237   IN UINT16  CfgScrubL3Rate;                      ///< Scrub L3Rate.
2238                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE}
2239   IN UINT16  CfgScrubIcRate;                      ///< Scrub Ic Rate.
2240                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE}
2241   IN UINT16  CfgScrubDcRate;                      ///< Scrub Dc Rate.
2242                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE}
2243   IN BOOLEAN CfgEccSyncFlood;                     ///< ECC Sync Flood.
2244                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD}
2245   IN UINT16  CfgEccSymbolSize;                    ///< ECC Symbol Size.
2246                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE}
2247   IN UINT64  CfgHeapDramAddress;                  ///< Heap contents will be temporarily stored in this address during the transition.
2248                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_HEAP_DRAM_ADDRESS}
2249   IN BOOLEAN CfgNodeMem1GBAlign;                  ///< Node Mem 1GB boundary Alignment
2250   IN BOOLEAN CfgS3LateRestore;                    ///< S3 Late Restore
2251   IN BOOLEAN CfgAcpiPstateIndependent;            ///< PSD method dependent/Independent
2252   IN AP_MTRR_SETTINGS *CfgApMtrrSettingsList;     ///< The AP's MTRR settings before final halt
2253                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_AP_MTRR_SETTINGS_LIST}
2254   IN UMA_MODE CfgUmaMode;                         ///< Uma Mode
2255   IN UINT32 CfgUmaSize;                           ///< Uma Size [31:0]=Addr[47:16]
2256   IN BOOLEAN CfgUmaAbove4G;                       ///< Uma Above 4G Support
2257   IN UMA_ALIGNMENT CfgUmaAlignment;               ///< Uma alignment
2258   IN BOOLEAN CfgProcessorScopeInSb;               ///< ACPI Processor Object in \\_SB scope
2259   IN CHAR8   CfgProcessorScopeName0;              ///< OEM specific 1st character of processor scope name.
2260   IN CHAR8   CfgProcessorScopeName1;              ///< OEM specific 2nd character of processor scope name.
2261   IN UINT8   CfgGnbHdAudio;                       ///< GNB HD Audio
2262   IN UINT8   CfgAbmSupport;                       ///< Abm Support
2263   IN UINT8   CfgDynamicRefreshRate;               ///< DRR Dynamic Refresh Rate
2264   IN UINT16  CfgLcdBackLightControl;              ///< LCD Backlight Control
2265   IN UINT8   CfgGnb3dStereoPinIndex;                ///< 3D Stereo Pin ID.
2266   IN UINT32  CfgTempPcieMmioBaseAddress;          ///< Temp pcie MMIO base Address
2267                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS}
2268   IN UINT32  CfgGnbIGPUSSID;                      ///< Gnb internal GPU SSID
2269                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_SUBSYSTEM_ID}
2270   IN UINT32  CfgGnbHDAudioSSID;                   ///< Gnb HD Audio SSID
2271                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID}
2272   IN UINT32  CfgGnbPcieSSID;                      ///< Gnb PCIe SSID
2273                                                   ///< Build-time customizable only - @BldCfgItem{BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID}
2274   IN UINT16  CfgLvdsSpreadSpectrum;               ///< Lvds Spread Spectrum
2275                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
2276   IN UINT16  CfgLvdsSpreadSpectrumRate;           ///< Lvds Spread Spectrum Rate
2277                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
2278   IN LVDS_MISC_CONTROL CfgLvdsMiscControl;        ///< The LVDS Misc control
2279   IN UINT16     CfgPcieRefClkSpreadSpectrum;      ///< PCIe Reference Clock Spread Spectrum
2280                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
2281   IN BOOLEAN Reserved;                            ///< reserved...
2282 } BUILD_OPT_CFG;
2283
2284 ///  A structure containing platform specific operational characteristics. This
2285 ///  structure is initially populated by the initializer with a copy of the same
2286 ///  structure that was created at build time using the build configuration controls.
2287 typedef struct _PLATFORM_CONFIGURATION {
2288   IN PERFORMANCE_PROFILE PlatformProfile;             ///< Several configuration settings for the processor.
2289   IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
2290                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_DEEMPHASIS_LIST}.
2291                                                       ///< @n @e Examples: See @ref DeemphasisExamples "Deemphasis List Examples".
2292   IN UINT8               CoreLevelingMode;            ///< Indicates how to balance the number of cores per processor.
2293                                                       ///< @BldCfgItem{BLDCFG_CORE_LEVELING_MODE}
2294   IN PLATFORM_C1E_MODES  C1eMode;                     ///< Specifies the method of C1e enablement - Disabled, HW, or message based.
2295                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_MODE}
2296   IN UINT32              C1ePlatformData;             ///< If C1eMode is HW, specifies the P_LVL3 I/O port of the platform.
2297                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA}
2298   IN UINT32              C1ePlatformData1;            ///< If C1eMode is SW, specifies the address of chipset's SMI command port.
2299                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA1}
2300   IN UINT32              C1ePlatformData2;            ///< If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source.
2301                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA2}
2302   IN PLATFORM_CSTATE_MODES  CStateMode;               ///< Specifies the method of C-State enablement - Disabled, or C6.
2303                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_MODE}
2304   IN UINT32              CStatePlatformData;          ///< This element specifies some pertinent data needed for the operation of the Cstate feature
2305                                                       ///< If CStateMode is CStateModeC6, this item is reserved
2306                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_OPDATA}
2307   IN UINT16              CStateIoBaseAddress;         ///< This item specifies a free block of 8 consecutive bytes of I/O ports that
2308                                                       ///< can be used to allow the CPU to enter Cstates.
2309                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS}
2310   IN PLATFORM_CPB_MODES  CpbMode;                     ///< Specifies the method of core performance boost enablement - Disabled, or Auto.
2311                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_CPB_MODE}
2312   IN BOOLEAN             UserOptionDmi;               ///< When set to TRUE, the DMI data table is generated.
2313   IN BOOLEAN             UserOptionPState;            ///< When set to TRUE, the PState data tables are generated.
2314   IN BOOLEAN             UserOptionSrat;              ///< When set to TRUE, the SRAT data table is generated.
2315   IN BOOLEAN             UserOptionSlit;              ///< When set to TRUE, the SLIT data table is generated.
2316   IN BOOLEAN             UserOptionWhea;              ///< When set to TRUE, the WHEA data table is generated.
2317   IN UINT32              PowerCeiling;                ///< P-State Ceiling Enabling Deck - Max power milli-watts.
2318   IN BOOLEAN             ForcePstateIndependent;      ///< P-State _PSD independence or dependence.
2319                                                       ///< @BldCfgItem{BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT}
2320   IN UINT32              NumberOfIoApics;             ///< Number of I/O APICs in the system
2321                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_NUM_IO_APICS}
2322   IN PLATFORM_VRM_CONFIGURATION VrmProperties[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
2323   IN BOOLEAN             ProcessorScopeInSb;          ///< ACPI Processor Object in \\_SB scope
2324                                                       ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_IN_SB}
2325   IN CHAR8               ProcessorScopeName0;         ///< OEM specific 1st character of processor scope name.
2326                                                       ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME0}
2327   IN CHAR8               ProcessorScopeName1;         ///< OEM specific 2nd character of processor scope name.
2328                                                       ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME1}
2329   IN UINT8               GnbHdAudio;                  ///< Control GFX HD Audio controller(Used for HDMI and DP display output),
2330                                                       ///< essentially it enables function 1 of graphics device.
2331                                                       ///< @li 0 = HD Audio disable
2332                                                       ///< @li 1 = HD Audio enable
2333                                                       ///< @BldCfgItem{BLDCFG_CFG_GNB_HD_AUDIO}
2334   IN UINT8               AbmSupport;                  ///< Automatic adjust LVDS/eDP Back light level support.It is
2335                                                       ///< characteristic specific to display panel which used by platform design.
2336                                                       ///< @li 0 = ABM support disabled
2337                                                       ///< @li 1 = ABM support enabled
2338                                                       ///< @BldCfgItem{BLDCFG_CFG_ABM_SUPPORT}
2339   IN UINT8               DynamicRefreshRate;          ///< Adjust refresh rate on LVDS/eDP.
2340                                                       ///< @BldCfgItem{BLDCFG_CFG_DYNAMIC_REFRESH_RATE}
2341   IN UINT16              LcdBackLightControl;         ///< The PWM frequency to LCD backlight control.
2342                                                       ///< If equal to 0 backlight not controlled by iGPU
2343                                                       ///< @BldCfgItem{BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL}
2344 } PLATFORM_CONFIGURATION;
2345
2346
2347 /**********************************************************************
2348  * Structures for: AmdInitLate
2349  **********************************************************************/
2350 #define PROC_VERSION_LENGTH 48
2351 #define MAX_DIMMS_PER_SOCKET 16
2352
2353 /*  Interface Parameter Structures  */
2354 /// DMI Type4 - Processor ID
2355 typedef struct {
2356   OUT UINT32                    ProcIdLsd;              ///< Lower half of 64b ID
2357   OUT UINT32                    ProcIdMsd;              ///< Upper half of 64b ID
2358 } TYPE4_PROC_ID;
2359
2360 /// DMI Type 4 - Processor information
2361 typedef struct {
2362   OUT UINT8                     T4ProcType;             ///< CPU Type
2363   OUT UINT8                     T4ProcFamily;           ///< Family 1
2364   OUT TYPE4_PROC_ID             T4ProcId;               ///< Id
2365   OUT UINT8                     T4Voltage;              ///< Voltage
2366   OUT UINT16                    T4ExternalClock;        ///< External clock
2367   OUT UINT16                    T4MaxSpeed;             ///< Max speed
2368   OUT UINT16                    T4CurrentSpeed;         ///< Current speed
2369   OUT UINT8                     T4Status;               ///< Status
2370   OUT UINT8                     T4ProcUpgrade;          ///< Up grade
2371   OUT UINT8                     T4CoreCount;            ///< Core count
2372   OUT UINT8                     T4CoreEnabled;          ///< Core Enable
2373   OUT UINT8                     T4ThreadCount;          ///< Thread count
2374   OUT UINT16                    T4ProcCharacteristics;  ///< Characteristics
2375   OUT UINT16                    T4ProcFamily2;          ///< Family 2
2376   OUT CHAR8                     T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version
2377 } TYPE4_DMI_INFO;
2378
2379 /// DMI Type 7 - Cache information
2380 typedef struct _TYPE7_DMI_INFO {
2381   OUT UINT16                    T7CacheCfg;             ///< Cache cfg
2382   OUT UINT16                    T7MaxCacheSize;         ///< Max size
2383   OUT UINT16                    T7InstallSize;          ///< Install size
2384   OUT UINT16                    T7SupportedSramType;    ///< Supported Sram Type
2385   OUT UINT16                    T7CurrentSramType;      ///< Current type
2386   OUT UINT8                     T7CacheSpeed;           ///< Speed
2387   OUT UINT8                     T7ErrorCorrectionType;  ///< ECC type
2388   OUT UINT8                     T7SystemCacheType;      ///< Cache type
2389   OUT UINT8                     T7Associativity;        ///< Associativity
2390 } TYPE7_DMI_INFO;
2391
2392 /// DMI Type 16 offset 04h - Location
2393 typedef enum {
2394   OtherLocation = 0x01,                                 ///< Assign 01 to Other
2395   UnknownLocation,                                      ///< Assign 02 to Unknown
2396   SystemboardOrMotherboard,                             ///< Assign 03 to systemboard or motherboard
2397   IsaAddonCard,                                         ///< Assign 04 to ISA add-on card
2398   EisaAddonCard,                                        ///< Assign 05 to EISA add-on card
2399   PciAddonCard,                                         ///< Assign 06 to PCI add-on card
2400   McaAddonCard,                                         ///< Assign 07 to MCA add-on card
2401   PcmciaAddonCard,                                      ///< Assign 08 to PCMCIA add-on card
2402   ProprietaryAddonCard,                                 ///< Assign 09 to proprietary add-on card
2403   NuBus,                                                ///< Assign 0A to NuBus
2404   Pc98C20AddonCard,                                     ///< Assign 0A0 to PC-98/C20 add-on card
2405   Pc98C24AddonCard,                                     ///< Assign 0A1 to PC-98/C24 add-on card
2406   Pc98EAddoncard,                                       ///< Assign 0A2 to PC-98/E add-on card
2407   Pc98LocalBusAddonCard                                 ///< Assign 0A3 to PC-98/Local bus add-on card
2408 } DMI_T16_LOCATION;
2409
2410 /// DMI Type 16 offset 05h - Memory Error Correction
2411 typedef enum {
2412   OtherUse = 0x01,                                      ///< Assign 01 to Other
2413   UnknownUse,                                           ///< Assign 02 to Unknown
2414   SystemMemory,                                         ///< Assign 03 to system memory
2415   VideoMemory,                                          ///< Assign 04 to video memory
2416   FlashMemory,                                          ///< Assign 05 to flash memory
2417   NonvolatileRam,                                       ///< Assign 06 to non-volatile RAM
2418   CacheMemory                                           ///< Assign 07 to cache memory
2419 } DMI_T16_USE;
2420
2421 /// DMI Type 16 offset 07h - Maximum Capacity
2422 typedef enum {
2423   Dmi16OtherErrCorrection = 0x01,                       ///< Assign 01 to Other
2424   Dmi16UnknownErrCorrection,                            ///< Assign 02 to Unknown
2425   Dmi16NoneErrCorrection,                               ///< Assign 03 to None
2426   Dmi16Parity,                                          ///< Assign 04 to parity
2427   Dmi16SingleBitEcc,                                    ///< Assign 05 to Single-bit ECC
2428   Dmi16MultiBitEcc,                                     ///< Assign 06 to Multi-bit ECC
2429   Dmi16Crc                                              ///< Assign 07 to CRC
2430 } DMI_T16_ERROR_CORRECTION;
2431
2432 /// DMI Type 16 - Physical Memory Array
2433 typedef struct {
2434   OUT DMI_T16_LOCATION          Location;               ///< The physical location of the Memory Array,
2435                                                         ///< whether on the system board or an add-in board.
2436   OUT DMI_T16_USE               Use;                    ///< Identifies the function for which the array
2437                                                         ///< is used.
2438   OUT DMI_T16_ERROR_CORRECTION  MemoryErrorCorrection;  ///< The primary hardware error correction or
2439                                                         ///< detection method supported by this memory array.
2440   OUT UINT32                    MaximumCapacity;        ///< The maximum memory capacity, in kilobytes,
2441                                                         ///< for the array.
2442   OUT UINT16                    NumberOfMemoryDevices;  ///< The number of slots or sockets available
2443                                                         ///< for memory devices in this array.
2444 } TYPE16_DMI_INFO;
2445
2446 /// DMI Type 17 offset 0Eh - Form Factor
2447 typedef enum {
2448   OtherFormFactor = 0x01,                               ///< Assign 01 to Other
2449   UnknowFormFactor,                                     ///< Assign 02 to Unknown
2450   SimmFormFactor,                                       ///< Assign 03 to SIMM
2451   SipFormFactor,                                        ///< Assign 04 to SIP
2452   ChipFormFactor,                                       ///< Assign 05 to Chip
2453   DipFormFactor,                                        ///< Assign 06 to DIP
2454   ZipFormFactor,                                        ///< Assign 07 to ZIP
2455   ProprietaryCardFormFactor,                            ///< Assign 08 to Proprietary Card
2456   DimmFormFactorFormFactor,                             ///< Assign 09 to DIMM
2457   TsopFormFactor,                                       ///< Assign 10 to TSOP
2458   RowOfChipsFormFactor,                                 ///< Assign 11 to Row of chips
2459   RimmFormFactor,                                       ///< Assign 12 to RIMM
2460   SodimmFormFactor,                                     ///< Assign 13 to SODIMM
2461   SrimmFormFactor,                                      ///< Assign 14 to SRIMM
2462   FbDimmFormFactor                                      ///< Assign 15 to FB-DIMM
2463 } DMI_T17_FORM_FACTOR;
2464
2465 /// DMI Type 17 offset 12h - Memory Type
2466 typedef enum {
2467   OtherMemType = 0x01,                                  ///< Assign 01 to Other
2468   UnknownMemType,                                       ///< Assign 02 to Unknown
2469   DramMemType,                                          ///< Assign 03 to DRAM
2470   EdramMemType,                                         ///< Assign 04 to EDRAM
2471   VramMemType,                                          ///< Assign 05 to VRAM
2472   SramMemType,                                          ///< Assign 06 to SRAM
2473   RamMemType,                                           ///< Assign 07 to RAM
2474   RomMemType,                                           ///< Assign 08 to ROM
2475   FlashMemType,                                         ///< Assign 09 to Flash
2476   EepromMemType,                                        ///< Assign 10 to EEPROM
2477   FepromMemType,                                        ///< Assign 11 to FEPROM
2478   EpromMemType,                                         ///< Assign 12 to EPROM
2479   CdramMemType,                                         ///< Assign 13 to CDRAM
2480   ThreeDramMemType,                                     ///< Assign 14 to 3DRAM
2481   SdramMemType,                                         ///< Assign 15 to SDRAM
2482   SgramMemType,                                         ///< Assign 16 to SGRAM
2483   RdramMemType,                                         ///< Assign 17 to RDRAM
2484   DdrMemType,                                           ///< Assign 18 to DDR
2485   Ddr2MemType,                                          ///< Assign 19 to DDR2
2486   Ddr2FbdimmMemType,                                    ///< Assign 20 to DDR2 FB-DIMM
2487   Ddr3MemType = 0x18,                                   ///< Assign 24 to DDR3
2488   Fbd2MemType                                           ///< Assign 25 to FBD2
2489 } DMI_T17_MEMORY_TYPE;
2490
2491 /// DMI Type 17 offset 13h - Type Detail
2492 typedef struct {
2493   OUT UINT16                    Reserved1:1;            ///< Reserved
2494   OUT UINT16                    Other:1;                ///< Other
2495   OUT UINT16                    Unknown:1;              ///< Unknown
2496   OUT UINT16                    FastPaged:1;            ///< Fast-Paged
2497   OUT UINT16                    StaticColumn:1;         ///< Static column
2498   OUT UINT16                    PseudoStatic:1;         ///< Pseudo-static
2499   OUT UINT16                    Rambus:1;               ///< RAMBUS
2500   OUT UINT16                    Synchronous:1;          ///< Synchronous
2501   OUT UINT16                    Cmos:1;                 ///< CMOS
2502   OUT UINT16                    Edo:1;                  ///< EDO
2503   OUT UINT16                    WindowDram:1;           ///< Window DRAM
2504   OUT UINT16                    CacheDram:1;            ///< Cache Dram
2505   OUT UINT16                    NonVolatile:1;          ///< Non-volatile
2506   OUT UINT16                    Reserved2:3;            ///< Reserved
2507 } DMI_T17_TYPE_DETAIL;
2508
2509 /// DMI Type 17 - Memory Device
2510 typedef struct {
2511   OUT UINT16                    TotalWidth;             ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
2512   OUT UINT16                    DataWidth;              ///< Data Width, in bits, of this memory device.
2513   OUT UINT16                    MemorySize;             ///< The size of the memory device.
2514   OUT DMI_T17_FORM_FACTOR       FormFactor;             ///< The implementation form factor for this memory device.
2515   OUT UINT8                     DeviceSet;              ///< Identifies when the Memory Device is one of a set of
2516                                                         ///< Memory Devices that must be populated with all devices of
2517                                                         ///< the same type and size, and the set to which this device belongs.
2518   OUT CHAR8                     DeviceLocator[8];       ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
2519   OUT CHAR8                     BankLocator[10];        ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
2520   OUT DMI_T17_MEMORY_TYPE       MemoryType;             ///< The type of memory used in this device.
2521   OUT DMI_T17_TYPE_DETAIL       TypeDetail;             ///< Additional detail on the memory device type
2522   OUT UINT16                    Speed;                  ///< Identifies the speed of the device, in megahertz (MHz).
2523   OUT UINT64                    ManufacturerIdCode;     ///< Manufacturer ID code.
2524   OUT CHAR8                     SerialNumber[9];        ///< Serial Number.
2525   OUT CHAR8                     PartNumber[19];         ///< Part Number.
2526   OUT UINT8                     Attributes;             ///< Bits 7-4: Reserved, Bits 3-0: rank.
2527   OUT UINT32                    ExtSize;                ///< Extended Size.
2528   OUT UINT16                    ConfigSpeed;            ///< Configured memory clock speed
2529 } TYPE17_DMI_INFO;
2530
2531 /// Memory DMI Type 17 and 20 - for memory use
2532 typedef struct {
2533   OUT UINT16                    TotalWidth;             ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
2534   OUT UINT16                    DataWidth;              ///< Data Width, in bits, of this memory device.
2535   OUT UINT16                    MemorySize;             ///< The size of the memory device.
2536   OUT DMI_T17_FORM_FACTOR       FormFactor;             ///< The implementation form factor for this memory device.
2537   OUT UINT8                     DeviceLocator;          ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
2538   OUT UINT8                     BankLocator;            ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
2539   OUT UINT16                    Speed;                  ///< Identifies the speed of the device, in megahertz (MHz).
2540   OUT UINT64                    ManufacturerIdCode;     ///< Manufacturer ID code.
2541   OUT UINT8                     SerialNumber[4];        ///< Serial Number.
2542   OUT UINT8                     PartNumber[18];         ///< Part Number.
2543   OUT UINT8                     Attributes;             ///< Bits 7-4: Reserved, Bits 3-0: rank.
2544   OUT UINT32                    ExtSize;                ///< Extended Size.
2545   OUT UINT8                     Socket:3;               ///< Socket ID
2546   OUT UINT8                     Channel:2;              ///< Channel ID
2547   OUT UINT8                     Dimm:2;                 ///< DIMM ID
2548   OUT UINT8                     DimmPresent:1;          ///< Dimm Present
2549   OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes, of a range
2550                                                         ///< of memory mapped to the referenced Memory Device.
2551   OUT UINT32                    EndingAddr;             ///< The handle, or instance number, associated with
2552                                                         ///< the Memory Device structure to which this address
2553                                                         ///< range is mapped.
2554   OUT UINT16                    ConfigSpeed;            ///< Configured memory clock speed
2555 } MEM_DMI_INFO;
2556
2557 /// DMI Type 19 - Memory Array Mapped Address
2558 typedef struct {
2559   OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes,
2560                                                         ///< of a range of memory mapped to the
2561                                                         ///< specified physical memory array.
2562   OUT UINT32                    EndingAddr;             ///< The physical ending address of the
2563                                                         ///< last kilobyte of a range of addresses
2564                                                         ///< mapped to the specified physical memory array.
2565   OUT UINT16                    MemoryArrayHandle;      ///< The handle, or instance number, associated
2566                                                         ///< with the physical memory array to which this
2567                                                         ///< address range is mapped.
2568   OUT UINT8                     PartitionWidth;         ///< Identifies the number of memory devices that
2569                                                         ///< form a single row of memory for the address
2570                                                         ///< partition defined by this structure.
2571 } TYPE19_DMI_INFO;
2572
2573 ///DMI Type 20 - Memory Device Mapped Address
2574 typedef struct {
2575   OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes, of a range
2576                                                         ///< of memory mapped to the referenced Memory Device.
2577   OUT UINT32                    EndingAddr;             ///< The handle, or instance number, associated with
2578                                                         ///< the Memory Device structure to which this address
2579                                                         ///< range is mapped.
2580   OUT UINT16                    MemoryDeviceHandle;     ///< The handle, or instance number, associated with
2581                                                         ///< the Memory Device structure to which this address
2582                                                         ///< range is mapped.
2583   OUT UINT16                    MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated
2584                                                         ///< with the Memory Array Mapped Address structure to
2585                                                         ///< which this device address range is mapped.
2586   OUT UINT8                     PartitionRowPosition;   ///< Identifies the position of the referenced Memory
2587                                                         ///< Device in a row of the address partition.
2588   OUT UINT8                     InterleavePosition;     ///< The position of the referenced Memory Device in
2589                                                         ///< an interleave.
2590   OUT UINT8                     InterleavedDataDepth;   ///< The maximum number of consecutive rows from the
2591                                                         ///< referenced Memory Device that are accessed in a
2592                                                         ///< single interleaved transfer.
2593 } TYPE20_DMI_INFO;
2594
2595 /// Collection of pointers to the DMI records
2596 typedef struct {
2597   OUT TYPE4_DMI_INFO            T4[MAX_SOCKETS_SUPPORTED];    ///< Type 4 struc
2598   OUT TYPE7_DMI_INFO            T7L1[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 1
2599   OUT TYPE7_DMI_INFO            T7L2[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 2
2600   OUT TYPE7_DMI_INFO            T7L3[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 3
2601   OUT TYPE16_DMI_INFO           T16;                          ///< Type 16 struc
2602   OUT TYPE17_DMI_INFO           T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc
2603   OUT TYPE19_DMI_INFO           T19;                          ///< Type 19 struc
2604   OUT TYPE20_DMI_INFO           T20[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 20 struc
2605 } DMI_INFO;
2606
2607 /**********************************************************************
2608  * Interface call:  AllocateExecutionCache
2609  **********************************************************************/
2610 #define MAX_CACHE_REGIONS    3
2611
2612 /// AllocateExecutionCache sub param structure for cached memory region
2613 typedef struct {
2614   IN OUT   UINT32               ExeCacheStartAddr;      ///< Start address
2615   IN OUT   UINT32               ExeCacheSize;           ///< Size
2616 } EXECUTION_CACHE_REGION;
2617
2618 /**********************************************************************
2619  * Interface call:  AmdGetAvailableExeCacheSize
2620  **********************************************************************/
2621 /// Get available Cache remain
2622 typedef struct {
2623   IN OUT   AMD_CONFIG_PARAMS    StdHeader;              ///< Standard configuration header
2624      OUT   UINT32               AvailableExeCacheSize;  ///< Remain size
2625 } AMD_GET_EXE_SIZE_PARAMS;
2626
2627 AGESA_STATUS
2628 AmdGetAvailableExeCacheSize (
2629   IN OUT   AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams
2630   );
2631
2632 /// Selection type for core leveling
2633 typedef enum {
2634   CORE_LEVEL_LOWEST,            ///< Level to lowest common denominator
2635   CORE_LEVEL_TWO,               ///< Level to 2 cores
2636   CORE_LEVEL_POWER_OF_TWO,      ///< Level to 1,2,4 or 8
2637   CORE_LEVEL_NONE,              ///< Do no leveling
2638   CORE_LEVEL_COMPUTE_UNIT,      ///< Level cores to one core per compute unit
2639   CORE_LEVEL_ONE,               ///< Level to 1 core
2640   CORE_LEVEL_THREE,             ///< Level to 3 cores
2641   CORE_LEVEL_FOUR,              ///< Level to 4 cores
2642   CORE_LEVEL_FIVE,              ///< Level to 5 cores
2643   CORE_LEVEL_SIX,               ///< Level to 6 cores
2644   CORE_LEVEL_SEVEN,             ///< Level to 7 cores
2645   CORE_LEVEL_EIGHT,             ///< Level to 8 cores
2646   CORE_LEVEL_NINE,              ///< Level to 9 cores
2647   CORE_LEVEL_TEN,               ///< Level to 10 cores
2648   CORE_LEVEL_ELEVEN,            ///< Level to 11 cores
2649   CORE_LEVEL_TWELVE,            ///< Level to 12 cores
2650   CORE_LEVEL_THIRTEEN,          ///< Level to 13 cores
2651   CORE_LEVEL_FOURTEEN,          ///< Level to 14 cores
2652   CORE_LEVEL_FIFTEEN,           ///< Level to 15 cores
2653   CoreLevelModeMax              ///< Used for bounds checking
2654 } CORE_LEVELING_TYPE;
2655
2656
2657
2658
2659
2660 /************************************************************************
2661  *
2662  *  AGESA Basic Level interface structure definition and function prototypes
2663  *
2664  ***********************************************************************/
2665
2666 /**********************************************************************
2667  * Interface call:  AmdCreateStruct
2668  **********************************************************************/
2669 AGESA_STATUS
2670 AmdCreateStruct (
2671   IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
2672   );
2673
2674 /**********************************************************************
2675  * Interface call:  AmdReleaseStruct
2676  **********************************************************************/
2677 AGESA_STATUS
2678 AmdReleaseStruct (
2679   IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
2680   );
2681
2682 /**********************************************************************
2683  * Interface call:  AmdInitReset
2684  **********************************************************************/
2685 /// AmdInitReset param structure
2686 typedef struct {
2687   IN       AMD_CONFIG_PARAMS         StdHeader;        ///< Standard configuration header
2688   IN       EXECUTION_CACHE_REGION    CacheRegion[3];   ///< The cached memory region
2689   IN       AMD_HT_RESET_INTERFACE    HtConfig;         ///< The interface for Ht Recovery
2690 } AMD_RESET_PARAMS;
2691
2692 AGESA_STATUS
2693 AmdInitReset (
2694   IN OUT   AMD_RESET_PARAMS     *ResetParams
2695   );
2696
2697
2698 /**********************************************************************
2699  * Interface call:  AmdInitEarly
2700  **********************************************************************/
2701 /// InitEarly param structure
2702 ///
2703 /// Provide defaults or customizations to each service performed in AmdInitEarly.
2704 ///
2705 typedef struct {
2706   IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
2707   IN       EXECUTION_CACHE_REGION CacheRegion[3];   ///< Execution Map Interface
2708   IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
2709   IN       AMD_HT_INTERFACE       HtConfig;         ///< HyperTransport Interface
2710   IN       GNB_CONFIGURATION      GnbConfig;        ///< GNB configuration
2711 } AMD_EARLY_PARAMS;
2712
2713 AGESA_STATUS
2714 AmdInitEarly (
2715   IN OUT   AMD_EARLY_PARAMS     *EarlyParams
2716   );
2717
2718
2719 /**********************************************************************
2720  * Interface call:  AmdInitPost
2721  **********************************************************************/
2722 /// AmdInitPost param structure
2723 typedef struct {
2724   IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
2725   IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
2726   IN       MEM_PARAMETER_STRUCT   MemConfig;        ///< Memory post param
2727 } AMD_POST_PARAMS;
2728
2729 AGESA_STATUS
2730 AmdInitPost (
2731   IN OUT   AMD_POST_PARAMS      *PostParams         ///< Amd Cpu init param
2732   );
2733
2734
2735 /**********************************************************************
2736  * Interface call:  AmdInitEnv
2737  **********************************************************************/
2738 /// AmdInitEnv param structure
2739 typedef struct {
2740   IN OUT   AMD_CONFIG_PARAMS      StdHeader;            ///< Standard configuration header
2741   IN       PLATFORM_CONFIGURATION PlatformConfig;       ///< platform operational characteristics.
2742   IN       GNB_ENV_CONFIGURATION  GnbEnvConfiguration;  ///< platform operational characteristics.
2743 } AMD_ENV_PARAMS;
2744
2745 AGESA_STATUS
2746 AmdInitEnv (
2747   IN OUT   AMD_ENV_PARAMS       *EnvParams
2748   );
2749
2750
2751 /**********************************************************************
2752  * Interface call:  AmdInitMid
2753  **********************************************************************/
2754 /// AmdInitMid param structure
2755 typedef struct {
2756   IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
2757   IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
2758 } AMD_MID_PARAMS;
2759
2760 AGESA_STATUS
2761 AmdInitMid (
2762   IN OUT   AMD_MID_PARAMS       *MidParams
2763   );
2764
2765
2766 /**********************************************************************
2767  * Interface call:  AmdInitLate
2768  **********************************************************************/
2769 /// AmdInitLate param structure
2770 typedef struct {
2771   IN OUT   AMD_CONFIG_PARAMS      StdHeader;              ///< Standard configuration header
2772   IN       PLATFORM_CONFIGURATION PlatformConfig;         ///< platform operational characteristics.
2773      OUT   DMI_INFO               *DmiTable;              ///< DMI Interface
2774      OUT   VOID                   *AcpiPState;            ///< Acpi Pstate SSDT Table
2775      OUT   VOID                   *AcpiSrat;              ///< SRAT Table
2776      OUT   VOID                   *AcpiSlit;              ///< SLIT Table
2777      OUT   VOID                   *AcpiWheaMce;           ///< WHEA MCE Table
2778      OUT   VOID                   *AcpiWheaCmc;           ///< WHEA CMC Table
2779      OUT   VOID                   *AcpiAlib;              ///< ACPI SSDT table with ALIB implementation
2780 } AMD_LATE_PARAMS;
2781
2782 AGESA_STATUS
2783 AmdInitLate (
2784   IN OUT   AMD_LATE_PARAMS      *LateParams
2785   );
2786
2787 /**********************************************************************
2788  * Interface call:  AmdInitRecovery
2789  **********************************************************************/
2790 /// CPU Recovery Parameters
2791 typedef struct {
2792   IN OUT   AMD_CONFIG_PARAMS StdHeader;             ///< Standard configuration header
2793   IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
2794 } AMD_CPU_RECOVERY_PARAMS;
2795
2796 /// AmdInitRecovery param structure
2797 typedef struct {
2798   IN OUT   AMD_CONFIG_PARAMS        StdHeader;            ///< Standard configuration header
2799   IN       MEM_PARAMETER_STRUCT     MemConfig;            ///< Memory post param
2800   IN       EXECUTION_CACHE_REGION   CacheRegion[3];       ///< The cached memory region. And the max cache region is 3
2801   IN       AMD_CPU_RECOVERY_PARAMS  CpuRecoveryParams;    ///< Params for CPU related recovery init.
2802 } AMD_RECOVERY_PARAMS;
2803
2804 AGESA_STATUS
2805 AmdInitRecovery (
2806   IN OUT   AMD_RECOVERY_PARAMS    *RecoveryParams
2807   );
2808
2809 /**********************************************************************
2810  * Interface call:  AmdInitResume
2811  **********************************************************************/
2812 /// AmdInitResume param structure
2813 typedef struct {
2814   IN OUT   AMD_CONFIG_PARAMS      StdHeader;      ///< Standard configuration header
2815   IN       PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics
2816   IN       AMD_S3_PARAMS          S3DataBlock;    ///< Save state data
2817 } AMD_RESUME_PARAMS;
2818
2819 AGESA_STATUS
2820 AmdInitResume (
2821   IN       AMD_RESUME_PARAMS    *ResumeParams
2822   );
2823
2824
2825 /**********************************************************************
2826  * Interface call:  AmdS3LateRestore
2827  **********************************************************************/
2828 /// AmdS3LateRestore param structure
2829 typedef struct {
2830   IN OUT   AMD_CONFIG_PARAMS    StdHeader;          ///< Standard configuration header
2831   IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
2832   IN       AMD_S3_PARAMS          S3DataBlock;      ///< Save state data
2833 } AMD_S3LATE_PARAMS;
2834
2835 AGESA_STATUS
2836 AmdS3LateRestore (
2837   IN OUT   AMD_S3LATE_PARAMS    *S3LateParams
2838   );
2839
2840
2841 /**********************************************************************
2842  * Interface call:  AmdS3Save
2843  **********************************************************************/
2844 /// AmdS3Save param structure
2845 typedef struct {
2846   IN OUT   AMD_CONFIG_PARAMS    StdHeader;          ///< Standard configuration header
2847   IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
2848      OUT   AMD_S3_PARAMS          S3DataBlock;      ///< Standard header
2849 } AMD_S3SAVE_PARAMS;
2850
2851 AGESA_STATUS
2852 AmdS3Save (
2853   IN OUT   AMD_S3SAVE_PARAMS    *AmdS3SaveParams
2854   );
2855
2856
2857 /**********************************************************************
2858  * Interface call:  AmdLateRunApTask
2859  **********************************************************************/
2860 /**
2861  * Entry point for AP tasking.
2862  */
2863 AGESA_STATUS
2864 AmdLateRunApTask (
2865   IN       AP_EXE_PARAMS  *AmdApExeParams
2866 );
2867
2868 //
2869 // General Services API
2870 //
2871
2872 /**********************************************************************
2873  * Interface service call:  AmdGetApicId
2874  **********************************************************************/
2875 /// Request the APIC ID of a particular core.
2876
2877 typedef struct {
2878   IN       AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
2879   IN       UINT8             Socket;           ///< The Core's Socket.
2880   IN       UINT8             Core;             ///< The Core id.
2881      OUT   BOOLEAN           IsPresent;        ///< The Core is present, and  ApicAddress is valid.
2882      OUT   UINT8             ApicAddress;      ///< The Core's APIC ID.
2883 } AMD_APIC_PARAMS;
2884
2885 /**
2886  * Get a specified Core's APIC ID.
2887  */
2888 AGESA_STATUS
2889 AmdGetApicId (
2890   IN OUT AMD_APIC_PARAMS *AmdParamApic
2891 );
2892
2893 /**********************************************************************
2894  * Interface service call:  AmdGetPciAddress
2895  **********************************************************************/
2896 /// Request the PCI Address of a Processor Module (that is, its Northbridge)
2897
2898 typedef struct {
2899   IN       AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
2900   IN       UINT8             Socket;           ///< The Processor's socket
2901   IN       UINT8             Module;           ///< The Module in that Processor
2902      OUT   BOOLEAN           IsPresent;        ///< The Core is present, and  PciAddress is valid.
2903      OUT   PCI_ADDR          PciAddress;       ///< The Processor's PCI Config Space address (Function 0, Register 0)
2904 } AMD_GET_PCI_PARAMS;
2905
2906 /**
2907  * Get Processor Module's PCI Config Space address.
2908  */
2909 AGESA_STATUS
2910 AmdGetPciAddress (
2911   IN OUT   AMD_GET_PCI_PARAMS *AmdParamGetPci
2912 );
2913
2914 /**********************************************************************
2915  * Interface service call:  AmdIdentifyCore
2916  **********************************************************************/
2917 /// Request the identity (Socket, Module, Core) of the current Processor Core
2918
2919 typedef struct {
2920   IN       AMD_CONFIG_PARAMS StdHeader;         ///< Standard configuration header
2921      OUT   UINT8             Socket;            ///< The current Core's Socket
2922      OUT   UINT8             Module;            ///< The current Core's Processor Module
2923      OUT   UINT8             Core;              ///< The current Core's core id.
2924 } AMD_IDENTIFY_PARAMS;
2925
2926 /**
2927  * "Who am I" for the current running core.
2928  */
2929 AGESA_STATUS
2930 AmdIdentifyCore (
2931   IN OUT  AMD_IDENTIFY_PARAMS *AmdParamIdentify
2932 );
2933
2934 /**********************************************************************
2935  * Interface service call:  AmdReadEventLog
2936  **********************************************************************/
2937 /// An Event Log Entry.
2938 typedef struct {
2939   IN       AMD_CONFIG_PARAMS StdHeader;         ///< Standard configuration header
2940      OUT   UINT32            EventClass;        ///< The severity of this event, matches AGESA_STATUS.
2941      OUT   UINT32            EventInfo;         ///< The unique event identifier, zero means "no event".
2942      OUT   UINT32            DataParam1;        ///< Data specific to the Event.
2943      OUT   UINT32            DataParam2;        ///< Data specific to the Event.
2944      OUT   UINT32            DataParam3;        ///< Data specific to the Event.
2945      OUT   UINT32            DataParam4;        ///< Data specific to the Event.
2946 } EVENT_PARAMS;
2947
2948 /**
2949  * Read an Event from the Event Log.
2950  */
2951 AGESA_STATUS
2952 AmdReadEventLog (
2953   IN       EVENT_PARAMS *Event
2954 );
2955
2956 /**********************************************************************
2957  * Interface service call:  AmdIdentifyDimm
2958  **********************************************************************/
2959 /// Request the identity of dimm from system address
2960
2961 typedef struct {
2962   IN OUT   AMD_CONFIG_PARAMS StdHeader;            ///< Standard configuration header
2963   IN       UINT64            MemoryAddress;        ///< System Address that needs to be translated to dimm identification.
2964   OUT      UINT8             SocketId;             ///< The socket on which the targeted address locates.
2965   OUT      UINT8             MemChannelId;         ///< The channel on which the targeted address locates.
2966   OUT      UINT8             DimmId;               ///< The dimm on which the targeted address locates.
2967 } AMD_IDENTIFY_DIMM;
2968
2969 /**
2970  * Get the dimm identification for the address.
2971  */
2972 AGESA_STATUS
2973 AmdIdentifyDimm (
2974   IN OUT   AMD_IDENTIFY_DIMM *AmdDimmIdentify
2975 );
2976
2977 /// Data structure for the Mapping Item between Unified ID for IDS Setup Option
2978 /// and the option value.
2979 ///
2980 typedef struct {
2981   IN    UINT16 IdsNvId;           ///< Unified ID for IDS Setup Option.
2982   OUT UINT16 IdsNvValue;        ///< The value of IDS Setup Option.
2983 } IDS_NV_ITEM;
2984
2985 /// Data Structure for IDS CallOut Function
2986 typedef struct {
2987   IN    AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
2988   IN    IDS_NV_ITEM *IdsNvPtr;              ///< Memory Pointer of IDS NV Table
2989   IN OUT UINTN Reserved;              ///< reserved
2990 } IDS_CALLOUT_STRUCT;
2991
2992 AGESA_STATUS
2993 AmdIdsRunApTaskLate (
2994   IN       AP_EXE_PARAMS  *AmdApExeParams
2995   );
2996
2997
2998 #define AGESA_IDS_DFT_VAL   0xFFFF                  ///<  Default value of every uninitlized NV item, the action for it will be ignored
2999 #define AGESA_IDS_NV_END    0xFFFF                  ///< Flag specify end of option structure
3000 /// WARNING: Don't change the comment below, it used as signature for script
3001 /// AGESA IDS NV ID Definitions
3002 typedef enum {
3003   AGESA_IDS_EXT_ID_START                   = 0x0000,///< 0x0000                                                             specify the start of external NV id
3004
3005   AGESA_IDS_NV_UCODE,                               ///< 0x0001                                                            Enable or disable microcode patching
3006
3007   AGESA_IDS_NV_TARGET_PSTATE,                       ///< 0x0002                                                        Set the P-state required to be activated
3008   AGESA_IDS_NV_POSTPSTATE,                          ///< 0x0003                                           Set the P-state required to be activated through POST
3009
3010   AGESA_IDS_NV_BANK_INTERLEAVE,                     ///< 0x0004                                                               Enable or disable Bank Interleave
3011   AGESA_IDS_NV_CHANNEL_INTERLEAVE,                  ///< 0x0005                                                            Enable or disable Channel Interleave
3012   AGESA_IDS_NV_NODE_INTERLEAVE,                     ///< 0x0006                                                               Enable or disable Node Interleave
3013   AGESA_IDS_NV_MEMHOLE,                             ///< 0x0007                                                                  Enables or disable memory hole
3014
3015   AGESA_IDS_NV_SCRUB_REDIRECTION,                   ///< 0x0008                                           Enable or disable a write to dram with corrected data
3016   AGESA_IDS_NV_DRAM_SCRUB,                          ///< 0x0009                                                   Set the rate of background scrubbing for DRAM
3017   AGESA_IDS_NV_DCACHE_SCRUB,                        ///< 0x000A                                            Set the rate of background scrubbing for the DCache.
3018   AGESA_IDS_NV_L2_SCRUB,                            ///< 0x000B                                           Set the rate of background scrubbing for the L2 cache
3019   AGESA_IDS_NV_L3_SCRUB,                            ///< 0x000C                                           Set the rate of background scrubbing for the L3 cache
3020   AGESA_IDS_NV_ICACHE_SCRUB,                        ///< 0x000D                                             Set the rate of background scrubbing for the Icache
3021   AGESA_IDS_NV_SYNC_ON_ECC_ERROR,                   ///< 0x000E                                    Enable or disable the sync flood on un-correctable ECC error
3022   AGESA_IDS_NV_ECC_SYMBOL_SIZE,                     ///< 0x000F                                                                             Set ECC symbol size
3023
3024   AGESA_IDS_NV_ALL_MEMCLKS,                         ///< 0x0010                                                      Enable or disable all memory clocks enable
3025   AGESA_IDS_NV_DCT_GANGING_MODE,                    ///< 0x0011                                                                             Set the Ganged mode
3026   AGESA_IDS_NV_DRAM_BURST_LENGTH32,                 ///< 0x0012                                                                    Set the DRAM Burst Length 32
3027   AGESA_IDS_NV_MEMORY_POWER_DOWN,                   ///< 0x0013                                                        Enable or disable Memory power down mode
3028   AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE,              ///< 0x0014                                                                  Set the Memory power down mode
3029   AGESA_IDS_NV_DLL_SHUT_DOWN,                       ///< 0x0015                                                                   Enable or disable DLLShutdown
3030   AGESA_IDS_NV_ONLINE_SPARE,                        ///< 0x0016      Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap
3031
3032   AGESA_IDS_NV_HT_ASSIST,                           ///< 0x0017                                                                     Enable or Disable HT Assist
3033   AGESA_IDS_NV_ATMMODE,                             ///< 0x0018                                                                      Enable or Disable ATM mode
3034
3035   AGESA_IDS_NV_HDTOUT,                              ///< 0x0019                                                                Enable or disable HDTOUT feature
3036
3037   AGESA_IDS_NV_HTLINKSOCKET,                        ///< 0x001A                                                                                  HT Link Socket
3038   AGESA_IDS_NV_HTLINKPORT,                          ///< 0x001B                                                                                    HT Link Port
3039   AGESA_IDS_NV_HTLINKFREQ,                          ///< 0x001C                                                                               HT Link Frequency
3040   AGESA_IDS_NV_HTLINKWIDTHIN,                       ///< 0x001D                                                                                HT Link In Width
3041   AGESA_IDS_NV_HTLINKWIDTHOUT,                      ///< 0x001E                                                                               HT Link Out Width
3042
3043   AGESA_IDS_NV_GNBHDAUDIOEN,                        ///< 0x001F                                                                  Enable or disable GNB HD Audio
3044
3045   AGESA_IDS_NV_CPB_EN,                              ///< 0x0020                                                                          Core Performance Boost
3046
3047   AGESA_IDS_NV_HTC_EN,                              ///< 0x0021                                                                                      HTC Enable
3048   AGESA_IDS_NV_HTC_OVERRIDE,                        ///< 0x0022                                                                                    HTC Override
3049   AGESA_IDS_NV_HTC_PSTATE_LIMIT,                    ///< 0x0023                                                                        HTC P-state limit select
3050   AGESA_IDS_NV_HTC_TEMP_HYS,                        ///< 0x0024                                                                      HTC Temperature Hysteresis
3051   AGESA_IDS_NV_HTC_ACT_TEMP,                        ///< 0x0025                                                                             HTC Activation Temp
3052
3053   AGESA_IDS_NV_POWER_POLICY,                        ///< 0x0026                                                                    Select Platform Power Policy
3054   AGESA_IDS_EXT_ID_END,                             ///< 0x0027                                                               specify the end of external NV ID
3055 } IDS_EX_NV_ID;
3056
3057
3058 #define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1)
3059
3060 #endif // _AGESA_H_