7 * Common main functions
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: (Mem)
12 * @e \$Revision: 49794 $ @e \$Date: 2011-03-29 13:59:05 +0800 (Tue, 29 Mar 2011) $
15 /*****************************************************************************
17 * Copyright (c) 2011, Advanced Micro Devices, Inc.
18 * All rights reserved.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are met:
22 * * Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * * Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
28 * its contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
37 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
38 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
40 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * ***************************************************************************
48 /*----------------------------------------------------------------------------
49 * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
51 *----------------------------------------------------------------------------
54 /*-----------------------------------------------------------------------------
55 * DEFINITIONS AND MACROS
57 *-----------------------------------------------------------------------------
60 #define ALLOC_SOCKET_STRUCT_HANDLE 0
61 #define ALLOC_DIE_STRUCT_HANDLE 1
62 #define ALLOC_DCT_STRUCT_HANDLE 2
63 #define ALLOC_CHL_STRUCT_HANDLE 3
64 #define ALLOC_PLATFORM_PTR_HANDLE 4
65 #define ALLOC_FORM_FACTOR_HANDLE 5
66 #define ALLOC_TRN_DATA_HANDLE 6
67 #define ALLOC_DIMM_DATA_HANDLE 7
68 #define ALLOC_PAR_TRN_HANDLE 8
69 #define ALLOC_NB_REG_TABLE 9
71 #define GENERATE_MEM_HANDLE(type, x, y, z) (\
72 AMD_MEM_MISC_HANDLES_START + (((type) << 18) + ((x) << 12) + ((y) << 6) + (z)) \
75 /// Heap handle for each supported family's NB register table
77 NbRegTabDR, ///< Heap handle for DR NB register table
78 NbRegTabDA, ///< Heap handle for DA NB register table
79 NbRegTabC32, ///< Heap handle for C32 NB register table
80 NbRegTabHY, ///< Heap handle for HY NB register table
81 NbRegTabKR, ///< Heap handle for KR NB register table
82 NbRegTabLN, ///< Heap handle for LN NB register table
83 NbRegTabON, ///< Heap handle for ON NB register table
84 NbRegTabOR, ///< Heap handle for OR NB register table
85 NbRegTabTN, ///< Heap handle for TN NB register table
86 NumberOfNbRegTables ///< Number of families that have NB register tables
90 #define VOLT1_5_ENCODED_VAL 0
91 #define VOLT1_35_ENCODED_VAL 1
92 #define VOLT1_25_ENCODED_VAL 2
93 #define CONVERT_VDDIO_TO_ENCODED(VddIo) (\
94 (VddIo == VOLT1_5) ? VOLT1_5_ENCODED_VAL : ((VddIo == VOLT1_35) ? VOLT1_35_ENCODED_VAL : ((VddIo == VOLT1_25) ? VOLT1_25_ENCODED_VAL : 0xFF)) \
96 #define CONVERT_ENCODED_TO_VDDIO(EncodedVal) (\
97 (EncodedVal == VOLT1_5_ENCODED_VAL) ? VOLT1_5 : ((EncodedVal == VOLT1_35_ENCODED_VAL) ? VOLT1_35 : ((EncodedVal == VOLT1_25_ENCODED_VAL) ? VOLT1_25 : VOLT_UNSUPPORTED)) \
99 /*----------------------------------------------------------------------------
100 * TYPEDEFS, STRUCTURES, ENUMS
102 *----------------------------------------------------------------------------
105 /// Bit field names used in memory initialization
107 BFDevVendorIDReg, ///< Bit field DevVendorIDReg
108 BFNodeID, ///< Bit field NodeID
109 BFNodeCnt, ///< Bit field NodeCnt
111 BFDramBaseReg0, ///< Bit field DramBaseReg0
112 BFDramBaseReg1, ///< Bit field DramBaseReg1
113 BFDramBaseReg2, ///< Bit field DramBaseReg2
114 BFDramBaseReg3, ///< Bit field DramBaseReg3
115 BFDramBaseReg4, ///< Bit field DramBaseReg4
116 BFDramBaseReg5, ///< Bit field DramBaseReg5
117 BFDramBaseReg6, ///< Bit field DramBaseReg6
118 BFDramBaseReg7, ///< Bit field DramBaseReg7
120 BFDramLimitReg0, ///< Bit field DramLimitReg0
121 BFDramLimitReg1, ///< Bit field DramLimitReg1
122 BFDramLimitReg2, ///< Bit field DramLimitReg2
123 BFDramLimitReg3, ///< Bit field DramLimitReg3
124 BFDramLimitReg4, ///< Bit field DramLimitReg4
125 BFDramLimitReg5, ///< Bit field DramLimitReg5
126 BFDramLimitReg6, ///< Bit field DramLimitReg6
127 BFDramLimitReg7, ///< Bit field DramLimitReg7
129 BFDramBaseHiReg0, ///< Bit field DramBaseHiReg0
130 BFDramBaseHiReg1, ///< Bit field DramBaseHiReg1
131 BFDramBaseHiReg2, ///< Bit field DramBaseHiReg2
132 BFDramBaseHiReg3, ///< Bit field DramBaseHiReg3
133 BFDramBaseHiReg4, ///< Bit field DramBaseHiReg4
134 BFDramBaseHiReg5, ///< Bit field DramBaseHiReg5
135 BFDramBaseHiReg6, ///< Bit field DramBaseHiReg6
136 BFDramBaseHiReg7, ///< Bit field DramBaseHiReg7
138 BFDramLimitHiReg0, ///< Bit field DramLimitHiReg0
139 BFDramLimitHiReg1, ///< Bit field DramLimitHiReg1
140 BFDramLimitHiReg2, ///< Bit field DramLimitHiReg2
141 BFDramLimitHiReg3, ///< Bit field DramLimitHiReg3
142 BFDramLimitHiReg4, ///< Bit field DramLimitHiReg4
143 BFDramLimitHiReg5, ///< Bit field DramLimitHiReg5
144 BFDramLimitHiReg6, ///< Bit field DramLimitHiReg6
145 BFDramLimitHiReg7, ///< Bit field DramLimitHiReg7
147 BFDramHoleAddrReg, ///< Bit field DramHoleAddrReg
149 BFCSBaseAddr0Reg, ///< Bit field CSBaseAddr0Reg
150 BFCSBaseAddr1Reg, ///< Bit field CSBaseAddr1Reg
151 BFCSBaseAddr2Reg, ///< Bit field CSBaseAddr2Reg
152 BFCSBaseAddr3Reg, ///< Bit field CSBaseAddr3Reg
153 BFCSBaseAddr4Reg, ///< Bit field CSBaseAddr4Reg
154 BFCSBaseAddr5Reg, ///< Bit field CSBaseAddr5Reg
155 BFCSBaseAddr6Reg, ///< Bit field CSBaseAddr6Reg
156 BFCSBaseAddr7Reg, ///< Bit field CSBaseAddr7Reg
158 BFCSMask0Reg, ///< Bit field CSMask0Reg
159 BFCSMask1Reg, ///< Bit field CSMask1Reg
160 BFCSMask2Reg, ///< Bit field CSMask2Reg
161 BFCSMask3Reg, ///< Bit field CSMask3Reg
163 BFRankDef0, ///< Bit field RankDef 0
164 BFRankDef1, ///< Bit field RankDef 1
165 BFRankDef2, ///< Bit field RankDef 2
166 BFRankDef3, ///< Bit field RankDef 3
168 BFDramControlReg, ///< Bit field DramControlReg
169 BFDramInitRegReg, ///< Bit field DramInitRegReg
170 BFDramBankAddrReg, ///< Bit field DramBankAddrReg
171 BFDramMRSReg, ///< Bit field DramMRSReg
172 BFDramTimingLoReg, ///< Bit field DramTimingLoReg
173 BFDramTimingHiReg, ///< Bit field DramTimingHiReg
174 BFDramConfigLoReg, ///< Bit field DramConfigLoReg
175 BFDramConfigHiReg, ///< Bit field DramConfigHiReg
176 BFDctAddlOffsetReg, ///< Bit field DctAddlOffsetReg
177 BFDctAddlDataReg, ///< Bit field DctAddlDataReg
178 BFDctAccessDone, ///< Bit field DctAccessDone
179 BFDctAccessError, ///< Bit field DctAccessError
180 BFDctExtraOffsetReg, ///< Bit field DctExtraOffsetReg
181 BFDctExtraDataReg, ///< Bit field DctExtraDataReg
182 BFDctExtraAccessDone, ///< Bit field DctExtraAccessDone
183 BFDramConfigMiscReg, ///< Bit field DramConfigMiscReg
184 BFDramCtrlMiscReg2, ///< Bit field DramCtrlMiscReg2
185 BFMctCfgHiReg, ///< Bit field MctCfgHiReg
186 BFMctCfgLoReg, ///< Bit field MctCfgLoReg
187 BFExtMctCfgLoReg, ///< Bit field ExtMctCfgLoReg
188 BFExtMctCfgHiReg, ///< Bit field ExtMctCfgHiReg
190 BFDramHoleBase, ///< Bit field DramHoleBase
191 BFDramHoleOffset, ///< Bit field DramHoleOffset
192 BFDramMemHoistValid, ///< Bit field DramMemHoistValid
193 BFDramHtHoleValid, ///< Bit field BFDramHtHoleValid - Orochi
194 BFDramHoleValid, ///< Bit field DramHoleValid
195 BFDramBaseAddr, ///< Bit field DramBaseAddr
196 BFDramIntlvSel, ///< Bit field DramIntlvSel
197 BFDramLimitAddr, ///< Bit field DramLimitAddr
198 BFDramIntlvEn, ///< Bit field DramIntlvEn
199 BFMemPsSel, ///< Bit field MemPsSel
200 BFDctCfgSel, ///< Bit field DctCfgSel
202 BFMcaNbCtlReg, ///< Bit field McaNbCtlReg
203 BFDramEccEn, ///< Bit field DramEccEn
204 BFSyncOnUcEccEn, ///< Bit field SyncOnUcEccEn
205 BFEccSymbolSize, ///< Bit field EccSymbolSize
206 BFMcaNbStatusLoReg, ///< Bit field McaNbStatusLoReg
207 BFMcaNbStatusHiReg, ///< Bit field McaNbStatusHiReg
208 BFDramScrub, ///< Bit field DramScrub
209 BFL2Scrub, ///< Bit field L2Scrub
210 BFDcacheScrub, ///< Bit field DcacheScrub
211 BFL3Scrub, ///< Bit field L3Scrub
212 BFScrubReDirEn, ///< Bit field ScrubReDirEn
213 BFScrubAddrLoReg, ///< Bit field ScrubAddrLoReg
214 BFScrubAddrHiReg, ///< Bit field ScrubAddrHiReg
215 BFC1ClkDivisor, ///< Bit field C1ClkDivisor
216 BFDisDatMsk, ///< Bit field DisDatMsk
217 BFNbFid, ///< Bit field NbFid
218 BFMTC1eEn, ///< Bit field MTC1eEn
219 BFL3Capable, ///< Bit field L3Capable
220 BFDisableL3, ///< Bit field DisableL3
221 BFEnhMemProtCap, ///< Bit field EnhMemProtCap
222 BFNbPsForceReq, ///< Bit field NbPsForceReq
223 BFNbPsCtrlDis, ///< Bit field NbPsCtrlDis
224 BFNbPsCap, ///< Bit field NbPsCap
226 BFNonSPDHi, ///< Bit field NonSPDHi
227 BFRdPtrInit, ///< Bit field RdPtrInit
228 BFAltVidC3MemClkTriEn, ///< Bit field AltVidC3MemClkTriEn
229 BFDqsRcvEnTrain, ///< Bit field DqsRcvEnTrain
230 BFEarlyArbEn, ///< Bit field EarlyArbEn
231 BFMaxLatency, ///< Bit field either MaxRdLat or MaxAsyncLat
233 BFMrsAddress, ///< Bit field MrsAddress
234 BFMrsBank, ///< Bit field MrsBank
235 BFMrsChipSel, ///< Bit field MrsChipSel
236 BFSendPchgAll, ///< Bit field SendPchgAll
237 BFSendAutoRefresh, ///< Bit field SendAutoRefresh
238 BFSendMrsCmd, ///< Bit field SendMrsCmd
239 BFDeassertMemRstX, ///< Bit field DeassertMemRstX
240 BFAssertCke, ///< Bit field AssertCke
241 BFSendZQCmd, ///< Bit field SendZQCmd
242 BFSendCtrlWord, ///< Bit field SendCtrlWord
243 BFEnDramInit, ///< Bit field EnDramInit
244 BFMrsLevel, ///< Bit field MrsLevel
245 BFMrsQoff, ///< Bit field MrsQoff
246 BFMrsAddressHi, ///< Bit field MrsAddress [17:13]
248 BFBurstCtrl, ///< Bit field BurstCtrl
249 BFDrvImpCtrl, ///< Bit field DrvImpCtrl
250 BFDramTerm_DDR3, ///< Bit field DramTerm_DDR3
251 BFDramTermDyn, ///< Bit field DramTermDyn
252 BFQoff, ///< Bit field Qoff
253 BFASR, ///< Bit field ASR
254 BFSRT, ///< Bit field SRT
255 BFTcwl, ///< Bit field Tcwl
256 BFPchgPDModeSel, ///< Bit field PchgPDModeSel
257 BFLowPowerDefault, ///< Bit field LowPowerDefault
259 BFTwrDDR3, ///< Bit field TwrDDR3
260 BFTcl, ///< Bit field Tcl
261 BFTrcd, ///< Bit field Trcd
262 BFTrp, ///< Bit field Trp
263 BFTrtp, ///< Bit field Trtp
264 BFTras, ///< Bit field Tras
265 BFTrc, ///< Bit field Trc
266 BFTwr, ///< Bit field Twr
267 BFTrrd, ///< Bit field Trrd
268 BFMemClkDis, ///< Bit field MemClkDis
269 BFDramTiming0, ///< Bit field BFDramTiming0
270 BFDramTiming1, ///< Bit field BFDramTiming1
271 BFDramTiming2, ///< Bit field BFDramTiming2
272 BFDramTiming3, ///< Bit field BFDramTiming3
273 BFDramTiming4, ///< Bit field BFDramTiming4
274 BFDramTiming5, ///< Bit field BFDramTiming5
275 BFDramTiming6, ///< Bit field BFDramTiming6
276 BFDramTiming10, ///< Bit field BFDramTiming10
277 BFDramNBP0, ///< Bit field BFDramNBP0
279 BFNonSPD, ///< Bit field NonSPD
280 BFTrwtWB, ///< Bit field TrwtWB
281 BFTrwtTO, ///< Bit field TrwtTO
282 BFTwtr, ///< Bit field Twtr
283 BFTwrrd, ///< Bit field Twrrd
284 BFTwrrdHi, ///< Bit field TwrrdHi
285 BFTwrwr, ///< Bit field Twrwr
286 BFTwrwrHi, ///< Bit field TwrwrHi
287 BFTrdrdSD, ///< Bit field TrdrdSD
288 BFTwrwrSD, ///< Bit field TwrwrSD
289 BFTwrrdSD, ///< Bit field TwrrdSD
290 BFTmod, ///< Bit field Tmod
291 BFTmrd, ///< Bit field Tmrd
292 BFRdOdtTrnOnDly, ///< Bit field RdOdtTrnOnDly
293 BFRdOdtOnDuration, ///< Bit field RdOdtOnDuration
294 BFWrOdtTrnOnDly, ///< Bit field WrOdtTrnOnDly
295 BFWrOdtOnDuration, ///< Bit field WrOdtOnDuration
296 BFPrtlChPDDynDly, ///< Bit field PrtlChPDDynDly
298 BFAggrPDDelay, ///< Bit field AggrPDDelay
299 BFPchgPDEnDelay, ///< Bit field PchgPDEnDelay
301 BFTrdrd, ///< Bit field Trdrd
302 BFTrdrdHi, ///< Bit field TrdrdHi
303 BFTref, ///< Bit field Tref
304 BFDisAutoRefresh, ///< Bit field DisAutoRefresh
305 BFTrfc0, ///< Bit field Trfc0
306 BFTrfc1, ///< Bit field Trfc1
307 BFTrfc2, ///< Bit field Trfc2
308 BFTrfc3, ///< Bit field Trfc3
310 BFInitDram, ///< Bit field InitDram
311 BFExitSelfRef, ///< Bit field ExitSelfRef
312 BFDramTerm, ///< Bit field DramTerm
313 BFParEn, ///< Bit field ParEn
314 BFBurstLength32, ///< Bit field BurstLength32
315 BFWidth128, ///< Bit field Width128
316 BFX4Dimm, ///< Bit field X4Dimm
317 BFDimmEccEn, ///< Bit field DimmEccEn
318 BFUnBuffDimm, ///< Bit field UnBuffDimm
319 BFEnterSelfRef, ///< Bit field EnterSelfRef
320 BFDynPageCloseEn, ///< Bit field DynPageCloseEn
321 BFIdleCycInit, ///< Bit field IdleCycInit
322 BFFreqChgInProg, ///< Bit field FreqChgInProg
323 BFForceAutoPchg, ///< Bit field ForceAutoPchg
324 BFStagRefEn, ///< Bit field StagRefEn
325 BFPendRefPaybackS3En, ///< Bit field PendRefPaybackS3En
326 BFEnDispAutoPrecharge, ///< Bit field EnDispAutoPrecharge
327 BFDisDllShutdownSR, ///< Bit field DisDllShutdownSR
328 BFDisSscClkGateData, ///< Bit field DisSscClkGateData
329 BFDisSscClkGateCmdAddr, ///< Bit field DisSscClkGateCmdAddr
330 BFDisSimulRdWr, ///< Bit field DisSimulRdWr
332 BFMemClkFreq, ///< Bit field MemClkFreq
333 BFMemClkFreqVal, ///< Bit field MemClkFreqVal
334 BFDdr3Mode, ///< Bit field Ddr3Mode
335 BFLegacyBiosMode, ///< Bit field LegacyBiosMode
336 BFZqcsInterval, ///< Bit field ZqcsInterval
337 BFRDqsEn, ///< Bit field RDqsEn
338 BFDisDramInterface, ///< Bit field DisDramInterface
339 BFPowerDownEn, ///< Bit field PowerDownEn
340 BFPowerDownMode, ///< Bit field PowerDownMode
341 BFFourRankSoDimm, ///< Bit field FourRankSoDimm
342 BFDcqArbBypassEn, ///< Bit field DcqArbBypassEn
343 BFFourRankRDimm, ///< Bit field FourRankRDimm
344 BFSlowAccessMode, ///< Bit field SlowAccessMode
345 BFBankSwizzleMode, ///< Bit field BankSwizzleMode
346 BFDcqBypassMax, ///< Bit field DcqBypassMax
347 BFFourActWindow, ///< Bit field FourActWindow
348 BFDphyMemPsSelEn, ///< Bit field BFDphyMemPsSelEn
350 BFODTSEn, ///< Bit field ODTSEn
351 BFCmdThrottleMode, ///< Bit field CmdThrottleMode
352 BFBwCapEn, ///< Bit field BwCapEn
354 BFDdr3FourSocketCh, ///< Bit field Ddr3FourSocketCh
355 BFSubMemclkRegDly, ///< Bit field SubMemclkRegDly
356 BFOdtSwizzle, ///< Bit field OdtSwizzle
357 BFProgOdtEn, ///< Bit field ProgOdtEn
358 BFCtrlWordCS, ///< Bit field CtrlWordCS
359 BFRefChCmdMgtDis, ///< Bit field RefChCmdMgtDis
360 BFFastSelfRefEntryDis, ///< Bit field FastSelfRefEntryDis
361 BFPrtlChPDEnhEn, ///< Bit field PrtlChPDEnhEn
362 BFAggrPDEn, ///< Bit field AggrPDEn
363 BFDataTxFifoWrDly, ///< Bit field DataTxFifoWrDly
364 BFWrDqDqsEarly, ///< Bit field WrDqDqsEarly
365 BFCSMux45, ///< Bit field CSMux45
366 BFCSMux67, ///< Bit field CSMux67
367 BFLrDimmMrsCtrl, ///< Bit field LrDimmMrsCtrl
368 BFExtendedParityEn, ///< Bit field ExtendedParityEn
369 BFLrDimmEnhRefEn, ///< Bit field LrDimmEnhRefEn
370 BFCSTimingMux67, ///< Bit field CSTimingMux67
372 BFIntLvRgnSwapEn, ///< Bit field IntLvRgnSwapEn
373 BFIntLvRgnBaseAddr, ///< Bit field IntLvRgnBaseAddr
374 BFIntLvRgnLmtAddr, ///< Bit field IntLvRgnLmtAddr
375 BFIntLvRgnSize, ///< Bit field IntLvRgnSize
377 BFDctSelHiRngEn, ///< Bit field DctSelHiRngEn
378 BFDctSelHi, ///< Bit field DctSelHi
379 BFDctSelIntLvEn, ///< Bit field DctSelIntLvEn
380 BFMemClrInit, ///< Bit field MemClrInit
381 BFDctGangEn, ///< Bit field DctGangEn
382 BFDctDatIntLv, ///< Bit field DctDatIntLv
383 BFDctSelIntLvAddr, ///< Bit field DctSelIntLvAddr
384 BFDctSelIntLvAddrHi, ///< Bit field DctSelIntLvAddrHi
385 BFDramEnabled, ///< Bit field DramEnabled
386 BFMemClrBusy, ///< Bit field MemClrBusy
387 BFMemCleared, ///< Bit field MemCleared
388 BFDctSelBaseAddr, ///< Bit field DctSelBaseAddr
389 BFDctSelBaseOffset, ///< Bit field DctSelBaseOffset
390 BFDctSelBankSwap, ///< Bit field DctSelBankSwap
392 BFAdapPrefMissRatio, ///< Bit field AdapPrefMissRatio
393 BFAdapPrefPosStep, ///< Bit field AdapPrefPosStep
394 BFAdapPrefNegStep, ///< Bit field AdapPrefNegStep
395 BFCohPrefPrbLmt, ///< Bit field CohPrefPrbLmt
397 BFFlushWrOnS3StpGnt, ///< Bit field FlushWrOnS3StpGnt
399 BFPrefDramTrainDone, ///< Bit field PrefDramTrainDone
400 BFWrDramTrainMode, ///< Bit field WrDramTrainMode
401 BFMctPrefReqLimit, ///< Bit field MctPrefReqLimit
402 BFPrefDramTrainMode, ///< Bit field PrefDramTrainMode
403 BFDctWrLimit, ///< Bit field DctWrLimit
404 BFMctWrLimit, ///< Bit field MctWrLimit
405 BFDramTrainPdbDis, ///< Bit field DramTrainPdbDis
406 BFTrainLength, ///< Bit field TrainLength
407 BFRdTrainGo, ///< Bit field RdTrainGo
408 BFWrTrainGo, ///< Bit field WrTrainGo
409 BFWrTrainAdrPtrLo, ///< Bit field WrTrainAdrPtrLo
410 BFWrTrainAdrPtrHi, ///< Bit field WrTrainAdrPtrHi
411 BFWrTrainBufAddr, ///< Bit field WrTrainBufAddr
412 BFWrTrainBufDat, ///< Bit field WrTrainBufDat
413 BFFlushWr, ///< Bit field FlushWr
414 BFFlushWrOnStpGnt, ///< Bit field FlushWrOnStpGnt
415 BFPrefCpuDis, ///< Bit field PrefCpuDis
416 BFPrefIoDis, ///< Bit field PrefIoDis
417 BFTrainCmpSts, ///< Bit field TrainCmpSts
418 BFTrainCmpSts2, ///< Bit field TrainCmpSts2
419 BFTraceModeEn, ///< Bit field TraceModeEn
421 BFAddrCmdDrvStren, ///< Bit field AddrCmdDrvStren
422 BFDataDrvStren, ///< Bit field DataDrvStren
423 BFCkeDrvStren, ///< Bit field CkeDrvStren
424 BFCsOdtDrvStren, ///< Bit field CsOdtDrvStren
425 BFClkDrvStren, ///< Bit field ClkDrvStren
426 BFDqsDrvStren, ///< Bit field DqsDrvStren
427 BFProcOdt, ///< Bit field ProcOdt
428 BFODCControl, ///< Bit field ODCControl
429 BFAddrTmgControl, ///< Bit field AddrTmgControl
430 BFAddrCmdFineDelay, ///< Bit field AddrCmdFineDelay
432 BFWrtLvTrEn, ///< Bit field WrtLvTrEn
433 BFWrtLvTrMode, ///< Bit field WrtLvTrMode
434 BFPhyFenceTrEn, ///< Bit field PhyFenceTrEn
435 BFTrDimmSel, ///< Bit field TrDimmSel
436 BFTrNibbleSel, ///< Bit field TrNibbleSel
437 BFFenceTrSel, ///< Bit field FenceTrSel
438 BFWrLvOdt, ///< Bit field WrLvOdt
439 BFWrLvOdtEn, ///< Bit field WrLvOdtEn
440 BFDqsRcvTrEn, ///< Bit field DqsRcvTrEn
441 BFDisAutoComp, ///< Bit field DisAutoComp
442 BFWrtLvErr, ///< Bit field WrtLvErr
443 BFODTAssertionCtl, ///< Bit field ODTAssertionCtl
444 BFNibbleTrainModeEn, ///< Bit field NibbleTrainModeEn
445 BFRankTrainModeEn, ///< Bit field RankTrainModeEn
446 BFPllMult, ///< Bit field PllMult
447 BFPllDiv, ///< Bit field PllDiv
448 BFDramPhyCtlReg, ///< Bit field Dram Phy Control Register
450 BFDramPhyStatusReg, ///< Bit field DramPhyStatusReg
452 BFD3Cmp2PCal, ///< Bit field D3Cmp2PCal
453 BFD3Cmp2NCal, ///< Bit field D3Cmp2NCal
454 BFD3Cmp1PCal, ///< Bit field D3Cmp1PCal
455 BFD3Cmp1NCal, ///< Bit field D3Cmp1NCal
456 BFD3Cmp0PCal, ///< Bit field D3Cmp0PCal
457 BFD3Cmp0NCal, ///< Bit field D3Cmp0NCal
459 BFPhyFence, ///< Bit field PhyFence
460 BFODTTri, ///< Bit field ODTTri
461 BFCKETri, ///< Bit field CKETri
462 BFChipSelTri, ///< Bit field ChipSelTri
463 BFPhyRODTCSLow, ///< Bit field PhyRODTCSLow
464 BFPhyRODTCSHigh, ///< Bit field PhyRODTCSHigh
465 BFPhyWODTCSLow, ///< Bit field PhyWODTCSLow
466 BFPhyWODTCSHigh, ///< Bit field PhyWODTCSHigh
467 BFUSPLLCtlAll, ///< Bit field USPLLCtlAll
468 BFDSPLLCtlAll, ///< Bit field DSPLLCtlAll
469 BFUSNibbleAlignEn, ///< Bit field USNibbleAlignEn
470 BFChnLinitClkEn, ///< Bit field ChnLinitClkEn
472 BFTSLinkSelect, ///< Bit field TSLinkSelect
473 BFTS2BitLockEn, ///< Bit field TS2BitLockEn
474 BFTS2En, ///< Bit field TS2En
475 BFTS1En, ///< Bit field TS1En
476 BFTS0LinkStarEn, ///< Bit field TS0LinkStarEn
477 BFTS0En, ///< Bit field TS0En
479 BFLinkTrainData, ///< Bit field LinkTrainData
481 BFRstRxFifoPtrs, ///< Bit field RstRxFifoPtrs
482 BFRxFifoPtrInit, ///< Bit field RxFifoPtrInit
483 BFRstTxFifoPtrs, ///< Bit field RstTxFifoPtrs
484 BFTxFifoPtrInit, ///< Bit field TxFifoPtrInit
486 BFLpbkCount, ///< Bit field LpbkCount
487 BFLpbkMap, ///< Bit field LpbkMap
488 BFSendLpbkMaintCmd, ///< Bit field SendLpbkMaintCmd
489 BFLpbkData, ///< Bit field LpbkData
491 BFMbRdPtrEn, ///< Bit field MbRdPtrEn
492 BFLnkLpBkLat, ///< Bit field LnkLpBkLat
493 BFLpbkRndTripLatDone, ///< Bit field LpbkRndTripLatDone
494 BFLnkLatTrainEn, ///< Bit field LnkLatTrainEn
496 BFDsPhyReset, ///< Bit field DsPhyReset
497 BFLinkReset, ///< Bit field LinkReset
499 BFPllLockTime, ///< Bit field PllLockTime
500 BFPllRegWaitTime, ///< Bit field PllRegWaitTime
501 BFNclkFreqDone, ///< Bit field NclkFreqDone
502 BFNbPs0NclkDiv, ///< Bit field NbPs0NclkDiv
503 BFNbPs1NclkDiv, ///< Bit field NbPs1NclkDiv
504 BFNbPsCsrAccSel, ///< Bit field NbPsCsrAccSel
505 BFNbPsDbgEn, ///< Bit field NbPsDbgEn
506 BFNclkRampWithDllRelock, ///< Bit field NclkRampWithDllRelock
508 BFOnLineSpareControl, ///< Bit field OnLineSpareControl
509 BFDdrMaxRate, ///< Bit field DdrMaxRate
511 BFNbPstateDis, ///< Bit field NbPstateDis
512 BFNbPsSel, ///< Bit field NbPsSel
513 BFNbPstateCtlReg, ///< Bit field NB Pstate Control register
514 BFSwNbPstateLoDis, ///< Bit field SwNbPstateLoDis
515 BFNbPstateLo, ///< Bit field NbPstateLo
516 BFNbPstateHi, ///< Bit field NbPstateHi
517 BFNbPstateMaxVal, ///< Bit field NbPstateMaxVal
518 BFCurNbPstate, ///< Bit field NbCurNbPstate
520 BFC6Base, ///< Bit field C6Base
521 BFC6DramLock, ///< Bit field C6DramLock
522 BFCC6SaveEn, ///< Bit field CC6SaveEn
523 BFCoreStateSaveDestNode, ///< Bit field CoreStateSaveDestNode
525 BFRxPtrInitReq, ///< Bit field RxPtrInitReq
526 BFAddrCmdTriEn, ///< Bit field AddrCmdTriEn
527 BFForceCasToSlot0, ///< Bit field ForceCasToSlot0
528 BFDisCutThroughMode, ///< Bit field DisCutThroughMode
529 BFDbeSkidBufDis, ///< Bit field DbeSkidBufDis
530 BFDbeGskMemClkAlignMode, ///< Bit field DbeGskMemClkAlignMode
531 BFEnCpuSerRdBehindNpIoWr, ///< Bit field EnCpuSerRdBehindNpIoWr
532 BFDRAMPhyDLLControl, ///< Bit field DRAMPhyDLLControl
533 BFRxDLLWakeupTime, ///< Bit field RxDllWakeupTime
534 BFRxCPUpdPeriod, ///< Bit field RxCPUpdPeriod
535 BFRxMaxDurDllNoLock, ///< Bit field RxMaxDurDllNoLock
536 BFTxDLLWakeupTime, ///< Bit field TxDllWakeupTime
537 BFTxCPUpdPeriod, ///< Bit field TxCPUpdPeriod
538 BFTxMaxDurDllNoLock, ///< Bit field TxMaxDurDllNoLock
539 BFEnRxPadStandby, ///< Bit field EnRxPadStandby
540 BFMaxSkipErrTrain, ///< Bit field MaxSkipErrTrain
541 BFSlotSel, ///< Bit field SlotSel
542 BFSlot1ExtraClkEn, ///< Bit field Slot1ExtraClkEn
544 BFMemTempHot, ///< Bit field MemTempHot
545 BFDoubleTrefRateEn, ///< Bit field DoubleTrefRateEn
547 BFAcpiPwrStsCtrlHi, ///< Bit field BFAcpiPwrStsCtrlHi
548 BFDramSrHysEn, ///< Bit field BFDramSrHysEn
549 BFDramSrHys, ///< Bit field BFDramSrHys
550 BFMemTriStateEn, ///< Bit field BFMemTriStateEn
551 BFDramSrEn, ///< Bit field BFDramSrEn
553 BFDeassertCke, ///< Bit field BFDeassertCke
554 BFFourRankRDimm0, ///< Bit field BFFourRankRDimm0
555 BFFourRankRDimm1, ///< Bit field BFFourRankRDimm1
556 BFTwrwrSdSc, ///< Bit field BFTwrwrSdSc
557 BFTwrwrSdDc, ///< Bit field BFTwrwrSdDc
558 BFTwrwrDd, ///< Bit field BFTwrwrDd
559 BFTrdrdSdSc, ///< Bit field BFTrdrdSdSc
560 BFTrdrdSdDc, ///< Bit field BFTrdrdSdDc
561 BFTrdrdDd, ///< Bit field BFTrdrdDd
562 BFTstag0, ///< Bit field BFTstag0
563 BFTstag1, ///< Bit field BFTstag1
564 BFTstag2, ///< Bit field BFTstag2
565 BFTstag3, ///< Bit field BFTstag3
567 BFCmdSendInProg, ///< Bit field BFCmdSendInProg
568 BFSendCmd, ///< Bit field BFSendCmd
569 BFTestStatus, ///< Bit field BFTestStatus
570 BFCmdTgt, ///< Bit field BFCmdTgt
571 BFCmdType, ///< Bit field BFCmdType
572 BFStopOnErr, ///< Bit field BFStopOnErr
573 BFResetAllErr, ///< Bit field BFResetAllErr
574 BFCmdTestEnable, ///< Bit field BFCmdTestEnable
575 BFTgtChipSelectA, ///< Bit field BFTgtChipSelectA
576 BFTgtBankA, ///< Bit field BFTgtBankA
577 BFTgtAddressA, ///< Bit field BFTgtAddressA
578 BFTgtChipSelectB, ///< Bit field BFTgtChipSelectB
579 BFTgtBankB, ///< Bit field BFTgtBankB
580 BFTgtAddressB, ///< Bit field BFTgtAddressB
581 BFBubbleCnt2, ///< Bit field BFBubbleCnt2
582 BFBubbleCnt, ///< Bit field BFBubbleCnt
583 BFCmdStreamLen, ///< Bit field BFCmdStreamLen
584 BFCmdCount, ///< Bit field BFCmdCount
585 BFErrDqNum, ///< Bit field BFErrDQNum
586 BFErrCnt, ///< Bit field BFErrCnt
587 BFNibbleErrSts, ///< Bit field BFNibbleErrSts
588 BFNibbleErr180Sts, ///< Bit field BFNibbleErr180Sts
589 BFDataPrbsSeed, ///< Bit field BFDataPrbsSeed
590 BFDramDqMaskLow, ///< Bit field BFDramDqMaskLow
591 BFDramDqMaskHigh, ///< Bit field BFDramDqMaskHigh
592 BFDramEccMask, ///< Bit field BFDramEccMask
593 BFSendActCmd, ///< Bit field BFSendActCmd
594 BFSendPchgCmd, ///< Bit field BFSendPchgCmd
595 BFCmdChipSelect, ///< Bit field BFCmdChipSelect
596 BFCmdBank, ///< Bit field BFCmdBank
597 BFCmdAddress, ///< Bit field BFCmdAddress
598 BFErrBeatNum, ///< Bit Field BFErrBeatNum
599 BFErrCmdNum, ///< Bit field BFBFErrCmdNum
600 BFDQErrLow, ///< Bit field BFDQSErrLow
601 BFDQErrHigh, ///< Bit field BFDQSErrHigh
602 BFEccErr, ///< Bit field BFEccErr
603 BFFastMstateDis, ///< Bit field BFFastMstateDis
605 /* Bit fields for workarounds */
606 BFErr263, ///< Bit field Err263
607 BFErr350, ///< Bit field Err350
608 BFErr322I, ///< Bit field Err322I
609 BFErr322II, ///< Bit field Err322II
610 BFErratum468WorkaroundNotRequired, ///< Bit field Erratum468WorkaroundNotRequired
612 /* Bit fields for Phy */
613 BFEccDLLConf, ///< Bit field EccDLLConf
614 BFProcOdtAdv, ///< Bit field ProcOdtAdv
615 BFEccDLLPwrDnConf, ///< Bit field EccDLLPwrDnConf
616 BFPhyPLLLockTime, ///< Bit field PhyPLLLockTime
617 BFPhyDLLLockTime, ///< Bit field PhyDLLLockTime
618 BFSkewMemClk, ///< Bit field SkewMemClk
619 BFPhyDLLControl, ///< Bit field BFPhyDLLControl
620 BFPhy0x0D080F0C, ///< Bit field BFPhy0x0D080F0C
621 BFPhy0x0D080F10, ///< Bit field BFPhy0x0D080F10
622 BFPhy0x0D080F11, ///< Bit field BFPhy0x0D080F11
623 BFPhy0x0D088F30, ///< Bit field BFPhy0x0D088F30
624 BFPhy0x0D08C030, ///< Bit field BFPhy0x0D08C030
625 BFPhy0x0D082F30, ///< Bit field BFPhy0x0D082F30
626 BFDiffTimingEn, ///< Bit Field DiffTimingEn
627 BFFence, ///< Bit Field Fence
628 BFDelay, ///< Bit Field Delay
629 BFFenceValue, ///< Bit Field FenceValue
631 BFPhy0x0D040F3E, ///< Bit field BFPhy0x0D040F3E
632 BFPhy0x0D042F3E, ///< Bit field BFPhy0x0D042F3E
633 BFPhy0x0D048F3E, ///< Bit field BFPhy0x0D048F3E
634 BFPhy0x0D04DF3E, ///< Bit field BFPhy0x0D04DF3E
636 BFPhyClkDllFine0, ///< Bit field ClkDllFineDly 0
637 BFPhyClkDllFine1, ///< Bit field ClkDllFineDly 1
639 BFPhyClkConfig0, ///< Bit field ClkConfig0
640 BFPhyClkConfig1, ///< Bit field ClkConfig1
641 BFPhyClkConfig2, ///< Bit field ClkConfig2
642 BFPhyClkConfig3, ///< Bit field ClkConfig3
644 BFPhy0x0D0F0F13, ///< Bit field BFPhy0x0D0F0F13
645 BFPhy0x0D0F0F13Bit0to7, ///< Bit field BFPhy0x0D0F0F13Bit0to7
646 BFPhy0x0D0F0830, ///< Bit field BFPhy0x0D0F0830
647 BFPhy0x0D07812F, ///< Bit field BFPhy0x0D0F8108
649 BFDataRxVioLvl, ///< Bit field DataRxVioLvl
650 BFClkRxVioLvl, ///< Bit field ClkRxVioLvl
651 BFCmdRxVioLvl, ///< Bit field CmdRxVioLvl
652 BFAddrRxVioLvl, ///< Bit field AddrRxVioLvl
653 BFCmpVioLvl, ///< Bit field CmpVioLvl
654 BFCsrComparator, ///< Bit field CsrComparator
655 BFAlwaysEnDllClks, ///< Bit field AlwaysEnDllClks
656 BFPhy0x0D0FE00A, ///< Bit field Phy0x0D0FE00A
657 BFPllPdMode, ///< Bit fields SelCsrPllPdMode and CsrPhySrPllPdMode
659 BFDataFence2, ///< Bit field DataFence2
660 BFClkFence2, ///< Bit field ClkFence2
661 BFCmdFence2, ///< Bit field CmdFence2
662 BFAddrFence2, ///< Bit field AddrFence2
664 BFDataByteDMConf, ///< Bit field DataByteDMConf
666 BFAddrCmdTri, ///< Bit field BFAddrCmdTri
667 BFLowPowerDrvStrengthEn, ///< Bit field BFLowPowerDrvStrengthEn
668 BFLevel, ///< Bit field Level
670 BFDbeGskFifoNumerator, ///< Bit field DbeGskFifoNumerator
671 BFDbeGskFifoDenominator, ///< Bit field DbeGskFifoDenominator
672 BFDataTxFifoSchedDlyNegSlot0, ///< Bit field DataTxFifoSchedDlyNegSlot0
673 BFDataTxFifoSchedDlyNegSlot1, ///< Bit field DataTxFifoSchedDlyNegSlot1
674 BFDataTxFifoSchedDlySlot0, ///< Bit field DataTxFifoSchedDlySlot0
675 BFDataTxFifoSchedDlySlot1, ///< Bit field DataTxFifoSchedDlySlot1
677 BFDisablePredriverCal, ///< Bit field DisablePredriverCal
678 BFDataByteTxPreDriverCal, ///< Bit field DataByteTxPreDriverCal
679 BFDataByteTxPreDriverCal2Pad1, ///< Bit field DataByteTxPreDriverCal2Pad1
680 BFDataByteTxPreDriverCal2Pad2, ///< Bit field DataByteTxPreDriverCal2Pad2
681 BFCmdAddr0TxPreDriverCal2Pad1, ///< Bit field CmdAddr0TxPreDriverCal2Pad1
682 BFCmdAddr0TxPreDriverCal2Pad2, ///< Bit field CmdAddr0TxPreDriverCal2Pad2
683 BFCmdAddr1TxPreDriverCal2Pad1, ///< Bit field CmdAddr1TxPreDriverCal2Pad1
684 BFCmdAddr1TxPreDriverCal2Pad2, ///< Bit field CmdAddr1TxPreDriverCal2Pad2
685 BFAddrTxPreDriverCal2Pad1, ///< Bit field AddrTxPreDriverCal2Pad1
686 BFAddrTxPreDriverCal2Pad2, ///< Bit field AddrTxPreDriverCal2Pad2
687 BFAddrTxPreDriverCal2Pad3, ///< Bit field AddrTxPreDriverCal2Pad3
688 BFAddrTxPreDriverCal2Pad4, ///< Bit field AddrTxPreDriverCal2Pad4
689 BFCmdAddr0TxPreDriverCalPad0, ///< Bit field CmdAddr0TxPreDriverCalPad0
690 BFCmdAddr1TxPreDriverCalPad0, ///< Bit field CmdAddr1TxPreDriverCalPad0
691 BFAddrTxPreDriverCalPad0, ///< Bit field AddrTxPreDriverCalPad0
692 BFClock0TxPreDriverCalPad0, ///< Bit field Clock0TxPreDriverCalPad0
693 BFClock1TxPreDriverCalPad0, ///< Bit field Clock1TxPreDriverCalPad0
694 BFClock2TxPreDriverCalPad0, ///< Bit field Clock2TxPreDriverCalPad0
695 BFPNOdtCal, ///< Bit field P/NOdtCal
696 BFPNDrvCal, ///< Bit field P/NDrvCal
697 BFCalVal, ///< Bit field CalVal
698 BFPStateToAccess, ///< Bit field PStateToAccess
700 BFTxp, ///< Bit field Txp
701 BFTxpdll, ///< Bit field Txpdll
702 BFDramPwrMngm1Reg, ///< Bit field DRAM Power Management 1 register
703 BFL3ScrbRedirDis, ///< Bit field L3ScrbRedirDis
704 BFDQOdt03, ///< Bit field DQ Odt 0-3
705 BFDQOdt47, ///< Bit field DQ Odt 4-7
706 BFTriDM, ///< Bit field TriDM
708 BFTcksrx, ///< Bit field Tcksrx
709 BFTcksre, ///< Bit field Tcksre
710 BFTckesr, ///< Bit field Tckesr
711 BFTpd, ///< Bit field Tpd
713 BFFixedErrataSkipPorFreqCap, ///< Bit field FixedErrataSkipPorFreqCap
714 BFPerRankTimingEn, ///< Bit field PerRankTimingEn
715 BFMemPhyPllPdMode, ///< Bit field MemPhyPllPdMode
716 BFBankSwap, ///< Bit field BankSwap
717 BFBwCapCmdThrottleMode, ///< Bit field BwCapCmdThrottleMode
718 BFRxChMntClkEn, ///< Bit field RxChMntClkEn
719 BFBlockRxDqsLock, ///< Bit field BlockRxDqsLock
720 BFRxSsbMntClkEn, ///< Bit field RxSsbMntClkEn
721 BFPhyPSMasterChannel, ///< Bit field PhyPSMasterChannel
723 BFDataByteDllPowerMgnByte0, ///< Bit field DataByteDllPowerManagement for Byte 0
724 BFDataByteDllPowerMgnByte1, ///< Bit field DataByteDllPowerManagement for Byte 1
725 BFDataByteDllPowerMgnByte2, ///< Bit field DataByteDllPowerManagement for Byte 2
726 BFDataByteDllPowerMgnByte3, ///< Bit field DataByteDllPowerManagement for Byte 3
727 BFDataByteDllPowerMgnByte4, ///< Bit field DataByteDllPowerManagement for Byte 4
728 BFDataByteDllPowerMgnByte5, ///< Bit field DataByteDllPowerManagement for Byte 5
729 BFDataByteDllPowerMgnByte6, ///< Bit field DataByteDllPowerManagement for Byte 6
730 BFDataByteDllPowerMgnByte7, ///< Bit field DataByteDllPowerManagement for Byte 7
731 BFDataByteDllPowerMgnByte8, ///< Bit field DataByteDllPowerManagement for Byte ECC
732 BFDataByteDllPowerMgnByteAll, ///< Bit field DataByteDllPowerManagement for all bytes
734 BFM1MemClkFreq, ///< Bit field M1MemClkFreq
735 BFRate, ///< Bit field Rate
736 BFFence2, ///< Bit field Fence2
738 BFNbVid0, ///< Bit field NbVid for NB Pstate 0
739 BFNbVid0Hi, ///< Bit field 7th bit of NbVid for NB Pstate 0
740 BFNbVid1, ///< Bit field NbVid for NB Pstate 1
741 BFNbVid1Hi, ///< Bit field 7th bit of NbVid for NB Pstate 1
742 BFNbVid2, ///< Bit field NbVid for NB Pstate 2
743 BFNbVid2Hi, ///< Bit field 7th bit of NbVid for NB Pstate 2
744 BFNbVid3, ///< Bit field NbVid for NB Pstate 3
745 BFNbVid3Hi, ///< Bit field 7th bit of NbVid for NB Pstate 3
747 BFMemPstate0, ///< Bit field MemPstate for NB Pstate 0
748 BFMemPstate1, ///< Bit field MemPstate for NB Pstate 1
749 BFMemPstate2, ///< Bit field MemPstate for NB Pstate 2
750 BFMemPstate3, ///< Bit field MemPstate for NB Pstate 3
751 BFMemPstateDis, ///< Bit field MemPstateDis
753 BFRxBypass3rd4thStg, ///< Bit field RxBypass3rd4thStg
754 BFRx4thStgEn, ///< Bit field Rx4thStgEn
755 BFDllNoLock, ///< Bit field DllNoLock
756 BFEnSplitMctDatBuffers, ///< Bit field EnSplitMctDatBuffers
757 BFGmcTokenLimit, ///< Bit fieid GmcTokenLimit
758 BFMctTokenLimit, ///< Bit field MctTokenLimit
759 BFGmcToDctControl1, ///< Bit field GmcToDctControl1
760 BFDllCSRBisaTrimDByte, ///< Bit field DllCSRBisaTrimDByte
761 BFDllCSRBisaTrimClk, ///< Bit field DllCSRBisaTrimClk
762 BFDllCSRBisaTrimCsOdt, ///< Bit field DllCSRBisaTrimCsOdt
763 BFDllCSRBisaTrimAByte2, ///< Bit field DllCSRBisaTrimAByte2
764 BFReduceLoop, ///< Bit field ReduceLoop
765 BFEffArbDis, ///< Bit field EffArbDis
768 BFReserved01, ///< Reserved 01
769 BFReserved02, ///< Reserved 02
770 BFReserved03, ///< Reserved 03
771 BFReserved04, ///< Reserved 04
772 BFReserved05, ///< Reserved 05
773 BFReserved06, ///< Reserved 06
774 BFReserved07, ///< Reserved 07
775 BFReserved08, ///< Reserved 08
776 BFReserved09, ///< Reserved 09
777 BFReserved10, ///< Reserved 10
779 BFReserved11, ///< Reserved 11
780 BFReserved12, ///< Reserved 12
781 BFReserved13, ///< Reserved 13
782 BFReserved14, ///< Reserved 14
783 BFReserved15, ///< Reserved 15
784 BFReserved16, ///< Reserved 16
785 BFReserved17, ///< Reserved 17
786 BFReserved18, ///< Reserved 18
787 BFReserved19, ///< Reserved 19
788 BFReserved20, ///< Reserved 20
790 BFDctSelBaseAddrReg, ///< Bit field DctSelBaseAddrReg
791 BFDctSelBaseOffsetReg, ///< Bit field DctSelBaseOffsetReg
793 /* End of accessible list --- entries below this line are for private use ------------*/
794 BFEndOfList, ///< End of bit field list
796 // Only for Table Drive Support define.
797 BFRcvEnDly, ///< F2x[1,0]9C_x[2B:10] Dram DQS Receiver Enable Timing Control Registers
798 BFWrDatDly, ///< F2x[1, 0]9C_x[302:301, 202:201, 102:101, 02:01] DRAM Write Data Timing [High:Low] Registers
799 BFRdDqsDly, ///< F2x[1, 0]9C_x[306:305, 206:205, 106:105, 06:05] DRAM Read DQS Timing Control [High:Low] Registers
800 BFWrDqsDly, ///< F2x[1, 0]9C_x[4A:30] DRAM DQS Write Timing Control Registers
801 BFPhRecDly, ///< F2x[1, 0]9C_x[51:50] DRAM Phase Recovery Control Register [High:Low] Registers
803 /* Do not define any entries beyond this point */
804 BFAbsLimit ///< Beyond this point is reserved for bit field manipulation
808 /// Bit field aliases
809 #define BFMainPllOpFreqId BFNbFid
810 #define BFNbDid BFNbPs0NclkDiv
811 #define BFRdDramTrainMode BFPrefDramTrainMode
812 #define BFThrottleEn BFCmdThrottleMode
813 #define BFIntlvRegionEn BFIntLvRgnSwapEn
814 #define BFIntlvRegionBase BFIntLvRgnBaseAddr
815 #define BFIntlvRegionLimit BFIntLvRgnLmtAddr
816 #define BFRdOdtPatReg BFPhyRODTCSLow
817 #define BFWrOdtPatReg BFPhyWODTCSLow
818 #define BFLockDramCfg BFC6DramLock
819 #define BFRstRcvFifo BFTwr
820 #define BFDramCmd2Reg BFCmdBank
821 #define BFDramODTCtlReg BFRdOdtTrnOnDly
823 /// Bit field names per DRAM CS base address register
825 BFCSEnable = 0, ///< Chip select enable
826 BFSpare = 1, ///< Spare rank
827 BFTestFail = 2, ///< Memory test failed
828 BFOnDimmMirror = 3 ///< on-DIMM mirroring enable
831 /// Flag for exclude dimm
833 NORMAL, ///< Normal mode, exclude the dimm if there is new dimm failure
834 TRAINING, ///< Training mode, exclude dimms that fail during training after training is done
835 END_TRAINING ///< End training mode, exclude all dimms that failed during training
839 #define MAX_NODES_SUPPORTED 8 ///< Maximum number of nodes in the system.
840 #define MAX_CS_PER_CHANNEL 8 ///< Max CS per channel
841 #define MAX_CS_PER_DELAY 2 ///< Max Chip Select Controlled by a set of delays.
843 #define VDDIO_DETERMINED 0xFF ///< VDDIO has been determined yet. Further processing is not needed.
847 /// This structure defines the shared data area that is used by the memory
848 /// code to share data between different northbridge objects. Each substructure
849 /// in the data area defines how this data area is used by a different purpose.
851 /// There should only be one instance of this struct created for all of the memory
854 typedef struct _MEM_SHARED_DATA {
856 // System memory map data
857 UINT32 CurrentNodeSysBase; ///< Base[47:16] (system address) DRAM base address for current node.
858 /// Memory map data for each node
859 BOOLEAN AllECC; ///< ECC support on the system
860 DIMM_EXCLUDE_FLAG DimmExcludeFlag; ///< Control the exclude dimm behavior
861 UINT8 VoltageMap; ///< The commonly supported voltage map in the system
863 UINT8 TopNode; ///< Node that has its memory mapped to TOPMEM/TOPMEM2
864 BOOLEAN C6Enabled; ///< TRUE if C6 is enabled
866 /// Data structure for NB register table
868 UINT64 FamilyId; ///< LogicalCpuid.Family
869 UINT32 *NBRegTable; ///< Pointer to allocated buffer for NBRegTable
870 } NBRegMap[MAX_NODES_SUPPORTED];
872 /// Data structure for node map
874 BOOLEAN IsValid; ///< TRUE if this node contains memory.
875 UINT32 SysBase; ///< Base[47:16] (system address) DRAM base address of this node.
876 UINT32 SysLimit; ///< Base[47:16] (system address) DRAM limit address of this node.
877 } NodeMap[MAX_NODES_SUPPORTED];
878 BOOLEAN UndoHoistingAbove1TB; ///< Undo hoisting above 1TB
880 /// Data structure for node interleave feature
882 BOOLEAN IsValid; ///< TRUE if the data in this structure is valid.
883 UINT8 NodeCnt; ///< Number of nodes in the system.
884 UINT32 NodeMemSize; ///< Total memory of this node.
885 UINT32 Dct0MemSize; ///< Total memory of this DCT 0.
886 UINT8 NodeIntlvSel; ///< Index to each node.
891 /// MEM_MAIN_DATA_BLOCK
893 typedef struct _MEM_MAIN_DATA_BLOCK {
894 struct _MEM_DATA_STRUCT *MemPtr; ///< Pointer to customer shared data
895 struct _MEM_NB_BLOCK *NBPtr; ///< Pointer to array of NB Blocks
896 struct _MEM_TECH_BLOCK *TechPtr; ///< Pointer to array of Tech Blocks
897 struct _MEM_SHARED_DATA *mmSharedPtr; ///< Pointer to shared data area.
898 UINT8 DieCount; ///< Total number of Dies installed
899 } MEM_MAIN_DATA_BLOCK;
901 /*----------------------------------------------------------------------------
902 * FUNCTIONS PROTOTYPE
904 *----------------------------------------------------------------------------
909 node: Indicates the Node
910 - Value ranges from 0-7, 0xF: for all nodes
913 dct: Indicate the DRAM Controller
914 - Value is 0, 1 (0xF: apply setting to all DCTs)
917 dimm: This values specifies which DIMM register will be applied
918 - The value varies from 0 to 3, 0xF: all DIMMs
921 attr - Indicates if the value needs to be added, subtracted, overridden or Auto (not changed)
922 - 0: Do not change the current value in the register
923 - 1: Use the value provided in the table to override the current value in the register (the one that AGESA initially determined)
924 - 2: Add the value provided in the table as an offset to the current value in the register (the one that AGESA initially determined)
925 - 3: Subtract the value provided in the table as an offset to the current value in the register (the one that AGESA initially determined)
928 time - Indicate the timing for the register which is written.
929 - 0: Write register value before Dram init
930 - 1: Write register value before memory training
931 - 2: Write register value after memory training
934 bytelane: bytelane number
935 - This determines specifies which bytelane register will be applied
936 - Bit0 =1 - set value into Bytelane0
937 - Bit1 =1 - set value into Bytelane1
938 - Bit2 =1 - set value into Bytelane2
941 - 0xFFFF: all bytelane
944 bfIndex: Indicate the bitfield index
947 value - Value to be used
948 - This can be an offset (sub or Add) or an override value.
953 // NBACCESS (MTBeforeDInit, MTNodes, MTDct0, BFCSBaseAddr5Reg, MTOverride, 0x400001),
954 // NBACCESS (MTBeforeTrn, MTNodes, MTDct1, BFCSBaseAddr7Reg, MTOverride, 0xFFFFFFFF),
955 // DQSACCESS (MTAfterTrn, MTNodes, MTDcts, MTDIMM0, MTBL1+MTBL2, BFRcvEnDly, MTSubtract, 2),
956 // DQSACCESS (MTAfterTrn, MTNodes, MTDct1, MTDIMM1, MTBLNOECC, BFRcvEnDly, MTAdd, 1),
958 #define ENDMEMTDS 0, 0, 0, 0, 0, 0, 0xFFFFFFFF, 0
960 #define NBACCESS(time, node, dct, bitfield, attr, value) \
962 ((node) & 0x0F) | ((dct) << 4), \
963 (((attr) & 0x07) << 4) | (VT_MSK_VALUE << 7) , \
964 (UINT8)((bitfield) & 0x000000FF), \
965 (UINT8)(((bitfield) >> 8) & 0x000000FF), \
966 (UINT8)(((bitfield) >> 16) & 0x000000FF), \
967 (UINT8)(((bitfield) >> 24) & 0x000000FF), \
969 (UINT8)((value) & 0x000000FF), \
970 (UINT8)(((value) >> 8) & 0x000000FF), \
971 (UINT8)(((value) >> 16) & 0x000000FF), \
972 (UINT8)(((value) >> 24) & 0x000000FF), \
976 #define DQSACCESS(time, node, dct, dimm, bitfield, attr, b0, b1, b2, b3, b4, b5, b6, b7, b8) \
978 ((node) & 0x0F) | ((dct) << 4), \
979 (((dimm) & 0x0F) | ((attr) & 0x07) << 4) | (VT_ARRAY << 7) , \
980 (UINT8)((bitfield) & 0x000000FF), \
981 (UINT8)(((bitfield) >> 8) & 0x000000FF), \
982 (UINT8)(((bitfield) >> 16) & 0x000000FF), \
983 (UINT8)(((bitfield) >> 24) & 0x000000FF), \
984 (b0), (b1), (b2), (b3), (b4), (b5), (b6), (b7), (b8) \
987 /// Type of modification supported by table driven support.
989 MTAuto, ///< Do not change the current value in the register
990 MTOverride, ///< Use the value provided in the table to override the current value in the register
991 MTSubtract, ///< Subtract the value provided in the table as an offset to the current value in the register
992 MTAdd, ///< Add the value provided in the table as an offset to the current value in the reg
993 MTAnd, ///< And the value provided in the table as an offset to the current value in the reg
994 MTOr ///< Or the value provided in the table as an offset to the current value in the reg
997 /// Time for table driven support to make modification.
999 MTBeforeInitializeMCT, ///< Before InitializeMCT
1000 MTAfterAutoCycTiming, ///< After Auto Cycle Timing
1001 MTAfterPlatformSpec, ///< After Platform Specific Configuration
1002 MTBeforeDInit, ///< Before Dram init
1003 MTBeforeTrn, ///< Before memory training
1004 MTAfterTrn, ///< After memory training
1005 MTAfterSwWLTrn, ///< After SW Based WL Training
1006 MTAfterHwWLTrnP1, ///< After HW Based WL Training Part 1
1007 MTAfterHwRxEnTrnP1, ///< After HW Based Receiver Enable Training Part 1
1008 MTAfterFreqChg, ///< After each frequency change
1009 MTAfterHwWLTrnP2, ///< After HW Based WL Training Part 2
1010 MTAfterHwRxEnTrnP2, ///< After HW Based Receiver Enable Training Part 2
1011 MTAfterSwRxEnTrn, ///< After SW Based Receiver Enable Training
1012 MTAfterDqsRwPosTrn, ///< After DQS Read/Write Position Training
1013 MTAfterMaxRdLatTrn, ///< After Max Read Latency Training
1014 MTAfterNbPstateChange, ///< After programming NB Pstate dependent registers
1015 MTAfterInterleave, ///< After Programming Interleave registers
1016 MTAfterFinalizeMCT, ///< After Finalize MCT Programming
1018 MTValidTimePointLimit, ///< Mark the upper bound of the supported time points
1019 MTEnd = 0xFF ///< End of enum define.
1022 /// Node on which modification should be made by table driven support.
1024 MTNode0, ///< Node 0.
1025 MTNode1, ///< Node 1.
1026 MTNode2, ///< Node 2.
1027 MTNode3, ///< Node 3.
1028 MTNode4, ///< Node 4.
1029 MTNode5, ///< Node 5.
1030 MTNode6, ///< Node 6.
1031 MTNode7, ///< Node 7.
1032 MTNodes = 0xF ///< all nodes
1035 /// DCT on which modification should be made by table driven support.
1039 MTDcts = 0xF, ///< all dcts
1042 /// Dimm on which modification should be made by table driven support.
1044 MTDIMM0, ///< Dimm 0.
1045 MTDIMM1, ///< Dimm 1.
1046 MTDIMM2, ///< Dimm 2.
1047 MTDIMM3, ///< Dimm 3.
1048 MTDIMMs = 0xF, ///< all Dimms
1051 /// Bytelane on which modification should be made by table driven support.
1053 MTBL0 = 0x1, ///< set the value into Bytelane0
1054 MTBL1 = 0x2, ///< set the value into Bytelane1
1055 MTBL2 = 0x4, ///< set the value into Bytelane2
1056 MTBL3 = 0x8, ///< set the value into Bytelane3
1057 MTBL4 = 0x10, ///< set the value into Bytelane4
1058 MTBL5 = 0x20, ///< set the value into Bytelane5
1059 MTBL6 = 0x40, ///< set the value into Bytelane6
1060 MTBL7 = 0x80, ///< set the value into Bytelane7
1061 MTBL8 = 0x100, ///< set the value into ECC
1062 MTBLNOECC = 0xFF, ///< all Bytelanes except ECC
1063 MTBLs = 0xFFFF, ///< all Bytelanes
1066 /// Values used to indicate which type of training is being done.
1068 TRN_RCVR_ENABLE, ///< Reciever Enable Training
1069 TRN_DQS_POSITION, ///< Read/Write DQS Position training
1070 TRN_MAX_READ_LATENCY ///< Max read Latency training
1075 MEMORY_PSTATE0, ///< Memory Pstate 0
1076 MEMORY_PSTATE1, ///< Memory Pstate 1
1079 /// Memory Pstate Training Stage
1081 MEMORY_PSTATE_1ST_STAGE = 0xF1, ///< Memory Pstate processing stage 1, in which full training is done at DDR667
1082 MEMORY_PSTATE_2ND_STAGE, ///< Memory Pstate processing stage 2, in which partial trainig will be done at DDR800 - target speed
1083 MEMORY_PSTATE_3RD_STAGE ///< Memory Pstate processing stage 3, in which full training will be done at target frequency and MaxRdLatency training will start
1086 /// RdDqsDly Retrain status
1088 RDDQSDLY_RTN_NEEDED = 0xF1, ///< RdDqsDly retrain may be needed
1089 RDDQSDLY_RTN_SUSPEND, ///< RdDqsDly retrain is suspected
1090 RDDQSDLY_RTN_ONGOING ///< RdDqsDly retrain condition is just detected
1091 } RDDQSDLY_RTN_STAT;
1092 /*----------------------------------------------------------------------------
1093 * FUNCTIONS PROTOTYPE
1095 *----------------------------------------------------------------------------
1099 IN OUT MEM_DATA_STRUCT *MemPtr
1104 IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
1109 IN AGESA_STATUS Errorval,
1110 IN OUT DIE_STRUCT *MCTPtr
1114 AmdMemInitDataStructDefRecovery (
1115 IN OUT MEM_DATA_STRUCT *MemPtr
1120 IN AGESA_STATUS Errorval,
1121 IN OUT DIE_STRUCT *MCTPtr
1125 memDefRetSuccess (VOID);