5 * AMD CPU Reset API, and related functions and structures.
7 * Contains code that initialized the CPU after early reset.
9 * @xrefitem bom "File Content Label" "Release Content"
12 * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
16 ******************************************************************************
18 * Copyright (c) 2011, Advanced Micro Devices, Inc.
19 * All rights reserved.
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22 * modification, are permitted provided that the following conditions are met:
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24 * notice, this list of conditions and the following disclaimer.
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32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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42 ******************************************************************************
45 #ifndef _CPU_EARLY_INIT_H_
46 #define _CPU_EARLY_INIT_H_
49 /*---------------------------------------------------------------------------------------
50 * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
51 *---------------------------------------------------------------------------------------
53 AGESA_FORWARD_DECLARATION (CPU_CORE_LEVELING_FAMILY_SERVICES);
55 /*---------------------------------------------------------------------------------------
56 * D E F I N I T I O N S A N D M A C R O S
57 *---------------------------------------------------------------------------------------
59 //----------------------------------------------------------------------------
60 // CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
62 //----------------------------------------------------------------------------
63 #define CPU_BRAND_ID_LENGTH 48 // Total number of characters supported
64 #define LOW_NODE_DEVICEID 24
65 #define NB_CAPABILITIES 0xE8 //Function 3 Registers
66 //----------------------------------------------------------------------------
67 // CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
69 //----------------------------------------------------------------------------
70 /* All lengths are in bytes */
71 #define MICROCODE_TRIADE_SIZE 28
72 #define MICROCODE_HEADER_LENGTH 64
74 /* Offsets in UCODE PATCH Header */
75 /* Note: Header is 64 bytes */
76 #define DATE_CODE_OFFSET 0 // 4 bytes
77 #define PATCH_ID 4 // 4 bytes
78 #define MICROCODE_PATH_DATA_ID 8 // 2 bytes
79 #define MICROCODE_PATCH_DATA_LENGTH 10 // 1 byte
80 #define MICROCODE_PATCH_DATA_CHECKSUM 12 // 4 bytes
81 #define CHIPSET_1_DEVICE_ID 16 // 4 bytes
82 #define CHIPSET_2_DEVICE_ID 20 // 4 bytes
83 #define PROCESSOR_REV_ID 24 // 2 bytes
84 #define CHIPSET_1_REV_ID 26 // 1 byte
85 #define CHIPSET_2_REV_ID 27 // 1 byte
87 #define MICROCODE_PATCH_2K_SIZE 2048
88 #define MICROCODE_PATCH_4K_SIZE 4096
89 /*---------------------------------------------------------------------------------------
90 * T Y P E D E F S, S T R U C T U R E S, E N U M S
91 *---------------------------------------------------------------------------------------
93 //----------------------------------------------------------------------------
94 // CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
96 //----------------------------------------------------------------------------
97 /// A structure representing BrandId[15:0] from
98 /// CPUID Fn8000_0001_EBX
100 UINT8 String1:4; ///< An index to a string value used to create the name string
101 UINT8 String2:4; ///< An index to a string value used to create the name string
102 UINT8 Page:1; ///< An index to the appropriate page for the String1, String2, and Model values
103 UINT8 Model:7; ///< A field used to create the model number in the name string
104 UINT8 Socket:4; ///< Specifies the package type
105 UINT8 Cores:4; ///< Identifies how many physical cores are present
106 } AMD_CPU_BRAND_DATA;
108 /// A structure containing string1 and string2 values
109 /// as well as information pertaining to their usage
111 IN UINT8 Cores; ///< Appropriate number of physical cores
112 IN UINT8 Page; ///< This string's page number
113 IN UINT8 Index; ///< String index
114 IN UINT8 Socket; ///< Package type information
115 IN CONST CHAR8 *Stringstart; ///< The literal string
116 IN UINT8 Stringlength; ///< Number of characters in the string
119 /// An entire CPU brand table.
121 UINT8 NumberOfEntries; ///< The number of entries in the table.
122 CONST AMD_CPU_BRAND *Table; ///< The table entries.
125 //----------------------------------------------------------------------------
126 // CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
128 //----------------------------------------------------------------------------
129 /// Microcode patch field definitions
131 UINT32 DateCode; ///< Date of patch creation
132 UINT32 PatchID; ///< Patch level
133 UINT16 MicrocodePatchDataID; ///< Internal use only
134 UINT8 MicrocodePatchDataLength; ///< Internal use only
135 UINT8 InitializationFlag; ///< Internal use only
136 UINT32 MicrocodePatchDataChecksum; ///< Doubleword sum of data block
137 UINT32 Chipset1DeviceID; ///< Device ID of 1st HT device to match
138 UINT32 Chipset2DeviceID; ///< Device ID of 2nd HT device to match
139 UINT16 ProcessorRevisionID; ///< Equivalent ID
140 UINT8 Chipset1RevisionID; ///< Revision level of 1st HT device to match
141 UINT8 Chipset2RevisionID; ///< Revision level of 2nd HT device to match
142 UINT8 BiosApiRevision; ///< BIOS INT 15 API revision required
143 UINT8 Reserved1[3]; ///< Reserved
144 UINT32 MatchRegister0; ///< Internal use only
145 UINT32 MatchRegister1; ///< Internal use only
146 UINT32 MatchRegister2; ///< Internal use only
147 UINT32 MatchRegister3; ///< Internal use only
148 UINT32 MatchRegister4; ///< Internal use only
149 UINT32 MatchRegister5; ///< Internal use only
150 UINT32 MatchRegister6; ///< Internal use only
151 UINT32 MatchRegister7; ///< Internal use only
152 UINT8 PatchDataBlock[896]; ///< Raw patch data
153 UINT8 Reserved2[896]; ///< Reserved
154 UINT8 X86CodePresent; ///< Boolean to determine if executable code exists
155 UINT8 X86CodeEntry[191]; ///< Code to execute if X86CodePresent != 0
158 /// Two kilobyte array containing the raw
159 /// microcode patch binary data
161 IN UINT8 MicrocodePatches[MICROCODE_PATCH_2K_SIZE]; ///< 2k UINT8 elements
164 /// Four kilobyte array containing the raw
165 /// microcode patch binary data
167 IN UINT8 MicrocodePatches[MICROCODE_PATCH_4K_SIZE]; ///< 4k UINT8 elements
168 } MICROCODE_PATCHES_4K;
171 * Set down core register
173 * @CpuServiceInstances
175 * @param[in] FamilySpecificServices The current Family Specific Services.
176 * @param[in] Socket Socket ID.
177 * @param[in] Module Module ID in socket.
178 * @param[in] LeveledCores Number of core.
179 * @param[in] CoreLevelMode Core level mode.
180 * @param[in] StdHeader Header for library and services.
182 * @retval TRUE Down Core register is updated.
183 * @retval FALSE Down Core register is not updated.
185 typedef BOOLEAN (F_CPU_SET_DOWN_CORE_REGISTER) (
186 IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
189 IN UINT32 *LeveledCores,
190 IN CORE_LEVELING_TYPE CoreLevelMode,
191 IN AMD_CONFIG_PARAMS *StdHeader
194 /// Reference to a method
195 typedef F_CPU_SET_DOWN_CORE_REGISTER *PF_CPU_SET_DOWN_CORE_REGISTER;
198 * Provide the interface to the Core Leveling Family Specific Services.
200 * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
201 * Each supported Family must provide an implementation for all methods in this interface, even if the
202 * implementation is a CommonReturn().
204 struct _CPU_CORE_LEVELING_FAMILY_SERVICES { // See Forward Declaration above
205 UINT16 Revision; ///< Interface version
207 PF_CPU_SET_DOWN_CORE_REGISTER SetDownCoreRegister; ///< Method: Set down core register.
210 //----------------------------------------------------------------------------
211 // CPU PERFORM EARLY INIT ON CORE
213 //----------------------------------------------------------------------------
215 #define PERFORM_EARLY_WARM_RESET 0x1 // bit 0 --- the related function needs to be run if it's warm reset
216 #define PERFORM_EARLY_COLD_BOOT 0x2 // bit 1 --- the related function needs to be run if it's cold boot
218 #define PERFORM_EARLY_ANY_CONDITION 0xFFFFFFFF // the related function always needs to be run
219 /*---------------------------------------------------------------------------------------
220 * F U N C T I O N P R O T O T Y P E
221 *---------------------------------------------------------------------------------------
224 // These are P U B L I C functions, used by IBVs
227 IN AMD_CONFIG_PARAMS *StdHeader,
228 IN PLATFORM_CONFIGURATION *PlatformConfig
231 // These are P U B L I C functions, used by AGESA
233 SetBrandIdRegisters (
234 IN OUT AMD_CONFIG_PARAMS *StdHeader
238 PmInitializationAtEarly (
239 IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
240 IN AMD_CONFIG_PARAMS *StdHeader
245 IN OUT AMD_CONFIG_PARAMS *StdHeader
247 #endif // _CPU_EARLY_INIT_H_