5 * AMD CPU APIC related utility functions and structures
7 * Contains code that provides mechanism to invoke and control APIC communication.
9 * @xrefitem bom "File Content Label" "Release Content"
12 * @e \$Revision: 44393 $ @e \$Date: 2010-12-24 07:38:46 +0800 (Fri, 24 Dec 2010) $
16 ******************************************************************************
18 * Copyright (c) 2011, Advanced Micro Devices, Inc.
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42 ******************************************************************************
45 #ifndef _CPU_APIC_UTILITIES_H_
46 #define _CPU_APIC_UTILITIES_H_
49 /*---------------------------------------------------------------------------------------
50 * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
51 *---------------------------------------------------------------------------------------
55 /*---------------------------------------------------------------------------------------
56 * D E F I N I T I O N S A N D M A C R O S
57 *---------------------------------------------------------------------------------------
59 #define APIC_CTRL_DWORD 0xF
60 #define APIC_CTRL_REG (APIC_CTRL_DWORD << 4)
61 #define APIC_CTRL_MASK 0xFF
62 #define APIC_CTRL_SHIFT 0
64 #define APIC_DATA_DWORD 0x38
65 #define APIC_DATA_REG (APIC_DATA_DWORD << 4)
67 #define APIC_REMOTE_READ_REG 0xC0
68 #define APIC_CMD_LO_REG 0x300
69 #define APIC_CMD_HI_REG 0x310
71 // APIC_CMD_LO_REG bits
72 #define CMD_REG_DELIVERY_STATUS 0x1000
73 #define CMD_REG_TO_READ 0x300
74 #define CMD_REG_REMOTE_RD_STS_MSK 0x30000
75 #define CMD_REG_REMOTE_DELIVERY_PENDING 0x10000
76 #define CMD_REG_REMOTE_DELIVERY_DONE 0x20000
77 #define CMD_REG_TO_NMI 0x400
80 #define WAIT_FOR_CORE 0x00000001
81 #define TASK_HAS_OUTPUT 0x00000002
82 #define RETURN_PARAMS 0x00000004
83 #define END_AT_HLT 0x00000008
84 #define PASS_EARLY_PARAMS 0x00000010
86 // Control Byte Values
87 // bit 7 indicates the type of message
88 // 1 - control message
89 // 0 - launch + APIC ID = message to go
91 #define CORE_UNAVAILABLE 0xFF
92 #define CORE_IDLE 0xFE
93 #define CORE_IDLE_HLT 0xFD
94 #define CORE_ACTIVE 0xFC
95 #define CORE_NEEDS_PTR 0xFB
96 #define CORE_NEEDS_DATA_SIZE 0xFA
97 #define CORE_STS_DATA_READY_1 0xF9
98 #define CORE_STS_DATA_READY_0 0xF8
99 #define CORE_DATA_FLAGS_READY 0xF7
100 #define CORE_DATA_FLAGS_ACKNOWLEDGE 0xF6
101 #define CORE_DATA_PTR_READY 0xF5
103 // Macro used to determine the number of dwords to transmit to the AP as input
104 #define SIZE_IN_DWORDS(sInput) ((UINT32) (((sizeof (sInput)) + 3) >> 2))
107 #define IDT_DESC_PRESENT 0x80
109 #define IDT_DESC_TYPE_LDT 0x02
110 #define IDT_DESC_TYPE_CALL16 0x04
111 #define IDT_DESC_TYPE_TASK 0x05
112 #define IDT_DESC_TYPE_INT16 0x06
113 #define IDT_DESC_TYPE_TRAP16 0x07
114 #define IDT_DESC_TYPE_CALL32 0x0C
115 #define IDT_DESC_TYPE_INT32 0x0E
116 #define IDT_DESC_TYPE_TRAP32 0x0F
117 /*---------------------------------------------------------------------------------------
118 * T Y P E D E F S, S T R U C T U R E S, E N U M S
119 *---------------------------------------------------------------------------------------
121 typedef VOID (*PF_AP_TASK) (AMD_CONFIG_PARAMS *StdHeader);
122 typedef VOID (*PF_AP_TASK_I) (VOID *, AMD_CONFIG_PARAMS *StdHeader);
123 typedef VOID (*PF_AP_TASK_C) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
124 typedef VOID (*PF_AP_TASK_IC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
125 typedef UINT32 (*PF_AP_TASK_O) (AMD_CONFIG_PARAMS *StdHeader);
126 typedef UINT32 (*PF_AP_TASK_IO) (VOID *, AMD_CONFIG_PARAMS *StdHeader);
127 typedef UINT32 (*PF_AP_TASK_OC) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
128 typedef UINT32 (*PF_AP_TASK_IOC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
130 /// Function pointer union representing the eight different
131 /// types of functions that an AP can be asked to perform.
133 PF_AP_TASK PfApTask; ///< AMD_CONFIG_PARAMS * input with no output
134 PF_AP_TASK_I PfApTaskI; ///< VOID * + AMD_CONFIG_PARAMS * input with no output
135 PF_AP_TASK_C PfApTaskC; ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with no output
136 PF_AP_TASK_IC PfApTaskIC; ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with no output
137 PF_AP_TASK_O PfApTaskO; ///< AMD_CONFIG_PARAMS * input with UINT32 output
138 PF_AP_TASK_IO PfApTaskIO; ///< VOID * + AMD_CONFIG_PARAMS * input with UINT32 output
139 PF_AP_TASK_OC PfApTaskOC; ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with UINT32 output
140 PF_AP_TASK_IOC PfApTaskIOC; ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with UINT32 output
143 /// Input structure for ApUtilTransmitBuffer and ApUtilReceiveBuffer
144 /// containing information about the data transfer from one core
147 IN OUT UINT16 DataSizeInDwords; ///< Size of the data to be transferred rounded up to the nearest dword
148 IN OUT VOID *DataPtr; ///< Pointer to the data
149 IN UINT32 DataTransferFlags; ///< Flags dictating certain aspects of the data transfer
152 /// Input structure for ApUtilRunCodeOnSocketCore.
153 typedef struct _AP_TASK {
154 AP_FUNCTION_PTR FuncAddress; ///< Pointer to the function that the AP will run
155 AP_DATA_TRANSFER DataTransfer; ///< Data transfer struct for optionally passing data that the AP should use as input to the function
156 UINT32 ExeFlags; ///< Flags dictating certain aspects of the AP tasking sequence
159 /// Input structure for ApUtilWaitForCoreStatus.
161 IN UINT8 *Status; ///< Pointer to the 1st element of an array of values to wait for
162 IN UINT8 NumberOfElements; ///< Number of elements in the array
163 IN UINT32 RetryCount; ///< Number of remote read cycles to complete before quitting
164 IN UINT32 WaitForStatusFlags; ///< Flags dictating certain aspects of ApUtilWaitForCoreStatus
165 } AP_WAIT_FOR_STATUS;
167 /// Interrupt Descriptor Table entry
169 UINT16 OffsetLo; ///< Lower 16 bits of the interrupt handler routine's offset
170 UINT16 Selector; ///< Interrupt handler routine's selector
171 UINT8 Rsvd; ///< Reserved
172 UINT8 Flags; ///< Interrupt flags
173 UINT16 OffsetHi; ///< Upper 16 bits of the interrupt handler routine's offset
174 UINT32 Offset64; ///< High order 32 bits of the handler's offset needed when in 64 bit mode
175 UINT32 Rsvd64; ///< Reserved
178 /// Structure needed to load the IDTR using the lidt instruction
180 UINT16 Limit; ///< Interrupt Descriptor Table size
181 UINT64 Base; ///< Interrupt Descriptor Table base address
184 #define WAIT_STATUS_EQUALITY 0x00000001
185 #define WAIT_INFINITELY 0
187 // Data Transfer Flags
188 #define DATA_IN_MEMORY 0x00000001
191 /*---------------------------------------------------------------------------------------
192 * F U N C T I O N P R O T O T Y P E
193 *---------------------------------------------------------------------------------------
195 // These are P U B L I C functions, used by AGESA
197 ApUtilReadRemoteControlByte (
198 IN UINT32 TargetApicId,
199 IN AMD_CONFIG_PARAMS *StdHeader
203 ApUtilWriteControlByte (
205 IN AMD_CONFIG_PARAMS *StdHeader
209 ApUtilReadRemoteDataDword (
210 IN UINT32 TargetApicId,
211 IN AMD_CONFIG_PARAMS *StdHeader
215 ApUtilWriteDataDword (
217 IN AMD_CONFIG_PARAMS *StdHeader
221 ApUtilRunCodeOnSocketCore (
225 IN AMD_CONFIG_PARAMS *StdHeader
229 ApUtilWaitForCoreStatus (
230 IN UINT32 TargetApicId,
231 IN AP_WAIT_FOR_STATUS *WaitParamsPtr,
232 IN AMD_CONFIG_PARAMS *StdHeader
237 IN AMD_CONFIG_PARAMS *StdHeader,
238 IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
242 ApUtilTaskOnExecutingCore (
244 IN AMD_CONFIG_PARAMS *StdHeader,
245 IN VOID *ConfigParams
249 ApUtilTransmitBuffer (
252 IN AP_DATA_TRANSFER *BufferInfo,
253 IN AMD_CONFIG_PARAMS *StdHeader
257 ApUtilReceiveBuffer (
260 IN OUT AP_DATA_TRANSFER *BufferInfo,
261 IN AMD_CONFIG_PARAMS *StdHeader
265 GetLocalApicIdForCore (
266 IN UINT32 TargetSocket,
267 IN UINT32 TargetCore,
268 OUT UINT32 *LocalApicId,
269 IN AMD_CONFIG_PARAMS *StdHeader
273 ApUtilRunCodeOnAllLocalCoresAtEarly (
275 IN AMD_CONFIG_PARAMS *StdHeader,
276 IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
280 RelinquishControlOfAllAPs (
281 IN AMD_CONFIG_PARAMS *StdHeader
287 IN AMD_CONFIG_PARAMS *StdHeader
292 IN IDT_BASE_LIMIT *IdtInfo,
293 IN AMD_CONFIG_PARAMS *StdHeader
298 IN IDT_BASE_LIMIT *IdtInfo,
299 IN AMD_CONFIG_PARAMS *StdHeader
302 #endif /* _CPU_APIC_UTILITIES_H_ */