1 // Code for handling EHCI USB controllers.
3 // Copyright (C) 2010 Kevin O'Connor <kevin@koconnor.net>
5 // This file may be distributed under the terms of the GNU LGPLv3 license.
7 #include "util.h" // dprintf
8 #include "pci.h" // pci_bdf_to_bus
9 #include "config.h" // CONFIG_*
10 #include "ioport.h" // outw
11 #include "usb-ehci.h" // struct ehci_qh
12 #include "pci_ids.h" // PCI_CLASS_SERIAL_USB_UHCI
13 #include "pci_regs.h" // PCI_BASE_ADDRESS_0
14 #include "usb.h" // struct usb_s
15 #include "farptr.h" // GET_FLATPTR
16 #include "usb-uhci.h" // init_uhci
17 #include "usb-ohci.h" // init_ohci
21 struct ehci_caps *caps;
22 struct ehci_regs *regs;
23 struct ehci_qh *async_qh;
24 struct pci_device *companion[8];
30 /****************************************************************
32 ****************************************************************/
34 #define EHCI_TIME_POSTPOWER 20
35 #define EHCI_TIME_POSTRESET 2
37 // Check if need companion controllers for full/low speed devices
39 ehci_note_port(struct usb_ehci_s *cntl)
41 if (--cntl->checkports)
42 // Ports still being detected.
44 if (! cntl->legacycount)
45 // No full/low speed devices found.
47 // Start companion controllers.
49 for (i=0; i<ARRAY_SIZE(cntl->companion); i++) {
50 struct pci_device *pci = cntl->companion[i];
54 // ohci/uhci_init call pci_config_XXX - don't run from irq handler.
57 if (pci_classprog(pci) == PCI_CLASS_SERIAL_USB_UHCI)
58 uhci_init(pci, cntl->usb.busid + i);
59 else if (pci_classprog(pci) == PCI_CLASS_SERIAL_USB_OHCI)
60 ohci_init(pci, cntl->usb.busid + i);
64 // Check if device attached to port
66 ehci_hub_detect(struct usbhub_s *hub, u32 port)
68 struct usb_ehci_s *cntl = container_of(hub->cntl, struct usb_ehci_s, usb);
69 u32 *portreg = &cntl->regs->portsc[port];
70 u32 portsc = readl(portreg);
73 if (!(portsc & PORT_POWER)) {
75 writel(portreg, portsc);
76 msleep(EHCI_TIME_POSTPOWER);
78 msleep(1); // XXX - time for connect to be detected.
80 portsc = readl(portreg);
82 if (!(portsc & PORT_CONNECT))
86 if ((portsc & PORT_LINESTATUS_MASK) == PORT_LINESTATUS_KSTATE) {
89 writel(portreg, portsc | PORT_OWNER);
93 // XXX - if just powered up, need to wait for USB_TIME_ATTDB?
95 // Begin reset on port
96 portsc = (portsc & ~PORT_PE) | PORT_RESET;
97 writel(portreg, portsc);
98 msleep(USB_TIME_DRSTR);
102 ehci_note_port(cntl);
106 // Reset device on port
108 ehci_hub_reset(struct usbhub_s *hub, u32 port)
110 struct usb_ehci_s *cntl = container_of(hub->cntl, struct usb_ehci_s, usb);
111 u32 *portreg = &cntl->regs->portsc[port];
112 u32 portsc = readl(portreg);
114 // Finish reset on port
115 portsc &= ~PORT_RESET;
116 writel(portreg, portsc);
117 msleep(EHCI_TIME_POSTRESET);
120 portsc = readl(portreg);
121 if (!(portsc & PORT_CONNECT))
122 // No longer connected
124 if (!(portsc & PORT_PE)) {
127 writel(portreg, portsc | PORT_OWNER);
133 ehci_note_port(cntl);
139 ehci_hub_disconnect(struct usbhub_s *hub, u32 port)
141 struct usb_ehci_s *cntl = container_of(hub->cntl, struct usb_ehci_s, usb);
142 u32 *portreg = &cntl->regs->portsc[port];
143 u32 portsc = readl(portreg);
144 writel(portreg, portsc & ~PORT_PE);
147 static struct usbhub_op_s ehci_HubOp = {
148 .detect = ehci_hub_detect,
149 .reset = ehci_hub_reset,
150 .disconnect = ehci_hub_disconnect,
153 // Find any devices connected to the root hub.
155 check_ehci_ports(struct usb_ehci_s *cntl)
159 memset(&hub, 0, sizeof(hub));
160 hub.cntl = &cntl->usb;
161 hub.portcount = cntl->checkports;
162 hub.op = &ehci_HubOp;
168 /****************************************************************
170 ****************************************************************/
173 configure_ehci(void *data)
175 struct usb_ehci_s *cntl = data;
177 // Allocate ram for schedule storage
178 struct ehci_framelist *fl = memalign_high(sizeof(*fl), sizeof(*fl));
179 struct ehci_qh *intr_qh = memalign_high(EHCI_QH_ALIGN, sizeof(*intr_qh));
180 struct ehci_qh *async_qh = memalign_high(EHCI_QH_ALIGN, sizeof(*async_qh));
181 if (!fl || !intr_qh || !async_qh) {
186 // XXX - check for halted?
189 u32 cmd = readl(&cntl->regs->usbcmd);
190 writel(&cntl->regs->usbcmd, (cmd & ~(CMD_ASE | CMD_PSE)) | CMD_HCRESET);
191 u64 end = calc_future_tsc(250);
193 cmd = readl(&cntl->regs->usbcmd);
194 if (!(cmd & CMD_HCRESET))
196 if (check_tsc(end)) {
203 // Disable interrupts (just to be safe).
204 writel(&cntl->regs->usbintr, 0);
206 // Set schedule to point to primary intr queue head
207 memset(intr_qh, 0, sizeof(*intr_qh));
208 intr_qh->next = EHCI_PTR_TERM;
209 intr_qh->info2 = (0x01 << QH_SMASK_SHIFT);
210 intr_qh->token = QTD_STS_HALT;
211 intr_qh->qtd_next = intr_qh->alt_next = EHCI_PTR_TERM;
213 for (i=0; i<ARRAY_SIZE(fl->links); i++)
214 fl->links[i] = (u32)intr_qh | EHCI_PTR_QH;
215 writel(&cntl->regs->periodiclistbase, (u32)fl);
217 // Set async list to point to primary async queue head
218 memset(async_qh, 0, sizeof(*async_qh));
219 async_qh->next = (u32)async_qh | EHCI_PTR_QH;
220 async_qh->info1 = QH_HEAD;
221 async_qh->token = QTD_STS_HALT;
222 async_qh->qtd_next = async_qh->alt_next = EHCI_PTR_TERM;
223 cntl->async_qh = async_qh;
224 writel(&cntl->regs->asynclistbase, (u32)async_qh);
227 writel(&cntl->regs->usbcmd, cmd | CMD_ASE | CMD_PSE | CMD_RUN);
229 // Set default of high speed for root hub.
230 writel(&cntl->regs->configflag, 1);
231 cntl->checkports = readl(&cntl->caps->hcsparams) & HCS_N_PORTS_MASK;
234 int count = check_ehci_ports(cntl);
235 free_pipe(cntl->usb.defaultpipe);
240 // No devices found - shutdown and free controller.
241 writel(&cntl->regs->usbcmd, cmd & ~CMD_RUN);
242 msleep(4); // 2ms to stop reading memory - XXX
251 ehci_init(struct pci_device *pci, int busid, struct pci_device *comppci)
253 if (! CONFIG_USB_EHCI)
257 u32 baseaddr = pci_config_readl(bdf, PCI_BASE_ADDRESS_0);
258 struct ehci_caps *caps = (void*)(baseaddr & PCI_BASE_ADDRESS_MEM_MASK);
259 u32 hcc_params = readl(&caps->hccparams);
260 if (hcc_params & HCC_64BIT_ADDR) {
261 dprintf(1, "No support for 64bit EHCI\n");
265 struct usb_ehci_s *cntl = malloc_tmphigh(sizeof(*cntl));
270 memset(cntl, 0, sizeof(*cntl));
271 cntl->usb.busid = busid;
273 cntl->usb.type = USB_TYPE_EHCI;
275 cntl->regs = (void*)caps + readb(&caps->caplength);
277 dprintf(1, "EHCI init on dev %02x:%02x.%x (regs=%p)\n"
278 , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf)
279 , pci_bdf_to_fn(bdf), cntl->regs);
281 pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_MASTER);
283 // XXX - check for and disable SMM control?
285 // Find companion controllers.
288 if (!comppci || comppci == pci)
290 if (pci_classprog(comppci) == PCI_CLASS_SERIAL_USB_UHCI)
291 cntl->companion[count++] = comppci;
292 else if (pci_classprog(comppci) == PCI_CLASS_SERIAL_USB_OHCI)
293 cntl->companion[count++] = comppci;
294 comppci = comppci->next;
297 run_thread(configure_ehci, cntl);
302 /****************************************************************
303 * End point communication
304 ****************************************************************/
308 struct ehci_qtd *next_td, *tds;
310 struct usb_pipe pipe;
313 // Wait for next USB async frame to start - for ensuring safe memory release.
315 ehci_waittick(struct usb_ehci_s *cntl)
321 // Wait for access to "doorbell"
324 u64 end = calc_future_tsc(100);
326 sts = readl(&cntl->regs->usbsts);
327 if (!(sts & STS_IAA)) {
328 cmd = readl(&cntl->regs->usbcmd);
329 if (!(cmd & CMD_IAAD))
332 if (check_tsc(end)) {
339 writel(&cntl->regs->usbcmd, cmd | CMD_IAAD);
340 // Wait for completion
342 sts = readl(&cntl->regs->usbsts);
345 if (check_tsc(end)) {
352 writel(&cntl->regs->usbsts, STS_IAA);
356 ehci_reset_pipe(struct ehci_pipe *pipe)
358 SET_FLATPTR(pipe->qh.qtd_next, EHCI_PTR_TERM);
359 SET_FLATPTR(pipe->qh.alt_next, EHCI_PTR_TERM);
361 SET_FLATPTR(pipe->qh.token, GET_FLATPTR(pipe->qh.token) & QTD_TOGGLE);
365 ehci_wait_td(struct ehci_pipe *pipe, struct ehci_qtd *td, int timeout)
367 u64 end = calc_future_tsc(timeout);
371 if (!(status & QTD_STS_ACTIVE))
373 if (check_tsc(end)) {
374 u32 cur = GET_FLATPTR(pipe->qh.current);
375 u32 tok = GET_FLATPTR(pipe->qh.token);
376 u32 next = GET_FLATPTR(pipe->qh.qtd_next);
378 dprintf(1, "ehci pipe=%p cur=%08x tok=%08x next=%x td=%p status=%x\n"
379 , pipe, cur, tok, next, td, status);
380 ehci_reset_pipe(pipe);
381 struct usb_ehci_s *cntl = container_of(
382 GET_FLATPTR(pipe->pipe.cntl), struct usb_ehci_s, usb);
388 if (status & QTD_STS_HALT) {
389 dprintf(1, "ehci_wait_td error - status=%x\n", status);
390 ehci_reset_pipe(pipe);
397 ehci_free_pipe(struct usb_pipe *p)
399 if (! CONFIG_USB_EHCI)
401 dprintf(7, "ehci_free_pipe %p\n", p);
402 struct ehci_pipe *pipe = container_of(p, struct ehci_pipe, pipe);
403 struct usb_ehci_s *cntl = container_of(
404 pipe->pipe.cntl, struct usb_ehci_s, usb);
406 struct ehci_qh *start = cntl->async_qh;
407 struct ehci_qh *pos = start;
409 struct ehci_qh *next = (void*)(pos->next & ~EHCI_PTR_BITS);
411 // Not found?! Exit without freeing.
412 warn_internalerror();
415 if (next == &pipe->qh) {
416 pos->next = next->next;
426 ehci_alloc_control_pipe(struct usb_pipe *dummy)
428 if (! CONFIG_USB_EHCI)
430 struct usb_ehci_s *cntl = container_of(
431 dummy->cntl, struct usb_ehci_s, usb);
432 dprintf(7, "ehci_alloc_control_pipe %p\n", &cntl->usb);
434 // Allocate a queue head.
435 struct ehci_pipe *pipe = memalign_tmphigh(EHCI_QH_ALIGN, sizeof(*pipe));
440 memset(pipe, 0, sizeof(*pipe));
441 memcpy(&pipe->pipe, dummy, sizeof(pipe->pipe));
442 pipe->qh.qtd_next = pipe->qh.alt_next = EHCI_PTR_TERM;
444 // Add queue head to controller list.
445 struct ehci_qh *async_qh = cntl->async_qh;
446 pipe->qh.next = async_qh->next;
448 async_qh->next = (u32)&pipe->qh | EHCI_PTR_QH;
453 fillTDbuffer(struct ehci_qtd *td, u16 maxpacket, const void *buf, int bytes)
458 if (pos >= &td->buf[ARRAY_SIZE(td->buf)])
459 // More data than can transfer in a single qtd - only use
460 // full packets to prevent a babble error.
461 return ALIGN_DOWN(dest - (u32)buf, maxpacket);
463 u32 max = 0x1000 - (dest & 0xfff);
471 return dest - (u32)buf;
475 ehci_control(struct usb_pipe *p, int dir, const void *cmd, int cmdsize
476 , void *data, int datasize)
479 if (! CONFIG_USB_EHCI)
481 dprintf(5, "ehci_control %p (dir=%d cmd=%d data=%d)\n"
482 , p, dir, cmdsize, datasize);
483 if (datasize > 4*4096 || cmdsize > 4*4096) {
484 // XXX - should support larger sizes.
488 struct ehci_pipe *pipe = container_of(p, struct ehci_pipe, pipe);
490 u16 maxpacket = pipe->pipe.maxpacket;
491 int speed = pipe->pipe.speed;
493 // Setup fields in qh
495 (1 << QH_MULT_SHIFT) | (speed != USB_HIGHSPEED ? QH_CONTROL : 0)
496 | (maxpacket << QH_MAXPACKET_SHIFT)
498 | (speed << QH_SPEED_SHIFT)
499 | (pipe->pipe.ep << QH_EP_SHIFT)
500 | (pipe->pipe.devaddr << QH_DEVADDR_SHIFT));
501 pipe->qh.info2 = ((1 << QH_MULT_SHIFT)
502 | (pipe->pipe.tt_port << QH_HUBPORT_SHIFT)
503 | (pipe->pipe.tt_devaddr << QH_HUBADDR_SHIFT));
505 // Setup transfer descriptors
506 struct ehci_qtd *tds = memalign_tmphigh(EHCI_QTD_ALIGN, sizeof(*tds) * 3);
511 memset(tds, 0, sizeof(*tds) * 3);
512 struct ehci_qtd *td = tds;
514 td->qtd_next = (u32)&td[1];
515 td->alt_next = EHCI_PTR_TERM;
516 td->token = (ehci_explen(cmdsize) | QTD_STS_ACTIVE
517 | QTD_PID_SETUP | ehci_maxerr(3));
518 fillTDbuffer(td, maxpacket, cmd, cmdsize);
522 td->qtd_next = (u32)&td[1];
523 td->alt_next = EHCI_PTR_TERM;
524 td->token = (QTD_TOGGLE | ehci_explen(datasize) | QTD_STS_ACTIVE
525 | (dir ? QTD_PID_IN : QTD_PID_OUT) | ehci_maxerr(3));
526 fillTDbuffer(td, maxpacket, data, datasize);
530 td->qtd_next = EHCI_PTR_TERM;
531 td->alt_next = EHCI_PTR_TERM;
532 td->token = (QTD_TOGGLE | QTD_STS_ACTIVE
533 | (dir ? QTD_PID_OUT : QTD_PID_IN) | ehci_maxerr(3));
537 pipe->qh.qtd_next = (u32)tds;
539 for (i=0; i<3; i++) {
540 struct ehci_qtd *td = &tds[i];
541 ret = ehci_wait_td(pipe, td, 500);
550 ehci_alloc_bulk_pipe(struct usb_pipe *dummy)
552 // XXX - this func is same as alloc_control except for malloc_low
553 if (! CONFIG_USB_EHCI)
555 struct usb_ehci_s *cntl = container_of(
556 dummy->cntl, struct usb_ehci_s, usb);
557 dprintf(7, "ehci_alloc_bulk_pipe %p\n", &cntl->usb);
559 // Allocate a queue head.
560 struct ehci_pipe *pipe = memalign_low(EHCI_QH_ALIGN, sizeof(*pipe));
565 memset(pipe, 0, sizeof(*pipe));
566 memcpy(&pipe->pipe, dummy, sizeof(pipe->pipe));
567 pipe->qh.qtd_next = pipe->qh.alt_next = EHCI_PTR_TERM;
569 // Add queue head to controller list.
570 struct ehci_qh *async_qh = cntl->async_qh;
571 pipe->qh.next = async_qh->next;
573 async_qh->next = (u32)&pipe->qh | EHCI_PTR_QH;
580 ehci_send_bulk(struct usb_pipe *p, int dir, void *data, int datasize)
582 if (! CONFIG_USB_EHCI)
584 struct ehci_pipe *pipe = container_of(p, struct ehci_pipe, pipe);
585 dprintf(7, "ehci_send_bulk qh=%p dir=%d data=%p size=%d\n"
586 , &pipe->qh, dir, data, datasize);
588 // Allocate 4 tds on stack (16byte aligned)
589 u8 tdsbuf[sizeof(struct ehci_qtd) * STACKQTDS + EHCI_QTD_ALIGN - 1];
590 struct ehci_qtd *tds = (void*)ALIGN((u32)tdsbuf, EHCI_QTD_ALIGN);
591 memset(tds, 0, sizeof(*tds) * STACKQTDS);
593 // Setup fields in qh
594 u16 maxpacket = GET_FLATPTR(pipe->pipe.maxpacket);
595 SET_FLATPTR(pipe->qh.info1
596 , ((1 << QH_MULT_SHIFT)
597 | (maxpacket << QH_MAXPACKET_SHIFT)
598 | (GET_FLATPTR(pipe->pipe.speed) << QH_SPEED_SHIFT)
599 | (GET_FLATPTR(pipe->pipe.ep) << QH_EP_SHIFT)
600 | (GET_FLATPTR(pipe->pipe.devaddr) << QH_DEVADDR_SHIFT)));
601 SET_FLATPTR(pipe->qh.info2
602 , ((1 << QH_MULT_SHIFT)
603 | (GET_FLATPTR(pipe->pipe.tt_port) << QH_HUBPORT_SHIFT)
604 | (GET_FLATPTR(pipe->pipe.tt_devaddr) << QH_HUBADDR_SHIFT)));
606 SET_FLATPTR(pipe->qh.qtd_next, (u32)MAKE_FLATPTR(GET_SEG(SS), tds));
610 struct ehci_qtd *td = &tds[tdpos++ % STACKQTDS];
611 int ret = ehci_wait_td(pipe, td, 5000);
615 struct ehci_qtd *nexttd_fl = MAKE_FLATPTR(GET_SEG(SS)
616 , &tds[tdpos % STACKQTDS]);
618 int transfer = fillTDbuffer(td, maxpacket, data, datasize);
619 td->qtd_next = (transfer==datasize ? EHCI_PTR_TERM : (u32)nexttd_fl);
620 td->alt_next = EHCI_PTR_TERM;
622 td->token = (ehci_explen(transfer) | QTD_STS_ACTIVE
623 | (dir ? QTD_PID_IN : QTD_PID_OUT) | ehci_maxerr(3));
626 datasize -= transfer;
629 for (i=0; i<STACKQTDS; i++) {
630 struct ehci_qtd *td = &tds[tdpos++ % STACKQTDS];
631 int ret = ehci_wait_td(pipe, td, 5000);
640 ehci_alloc_intr_pipe(struct usb_pipe *dummy, int frameexp)
642 if (! CONFIG_USB_EHCI)
644 struct usb_ehci_s *cntl = container_of(
645 dummy->cntl, struct usb_ehci_s, usb);
646 dprintf(7, "ehci_alloc_intr_pipe %p %d\n", &cntl->usb, frameexp);
650 int maxpacket = dummy->maxpacket;
651 // Determine number of entries needed for 2 timer ticks.
652 int ms = 1<<frameexp;
653 int count = DIV_ROUND_UP(PIT_TICK_INTERVAL * 1000 * 2, PIT_TICK_RATE * ms);
654 struct ehci_pipe *pipe = memalign_low(EHCI_QH_ALIGN, sizeof(*pipe));
655 struct ehci_qtd *tds = memalign_low(EHCI_QTD_ALIGN, sizeof(*tds) * count);
656 void *data = malloc_low(maxpacket * count);
657 if (!pipe || !tds || !data) {
661 memset(pipe, 0, sizeof(*pipe));
662 memcpy(&pipe->pipe, dummy, sizeof(pipe->pipe));
663 pipe->next_td = pipe->tds = tds;
668 | (maxpacket << QH_MAXPACKET_SHIFT)
669 | (pipe->pipe.speed << QH_SPEED_SHIFT)
670 | (pipe->pipe.ep << QH_EP_SHIFT)
671 | (pipe->pipe.devaddr << QH_DEVADDR_SHIFT));
672 pipe->qh.info2 = ((1 << QH_MULT_SHIFT)
673 | (pipe->pipe.tt_port << QH_HUBPORT_SHIFT)
674 | (pipe->pipe.tt_devaddr << QH_HUBADDR_SHIFT)
675 | (0x01 << QH_SMASK_SHIFT)
676 | (0x1c << QH_CMASK_SHIFT));
677 pipe->qh.qtd_next = (u32)tds;
680 for (i=0; i<count; i++) {
681 struct ehci_qtd *td = &tds[i];
682 td->qtd_next = (i==count-1 ? (u32)tds : (u32)&td[1]);
683 td->alt_next = EHCI_PTR_TERM;
684 td->token = (ehci_explen(maxpacket) | QTD_STS_ACTIVE
685 | QTD_PID_IN | ehci_maxerr(3));
686 td->buf[0] = (u32)data + maxpacket * i;
689 // Add to interrupt schedule.
690 struct ehci_framelist *fl = (void*)readl(&cntl->regs->periodiclistbase);
692 // Add to existing interrupt entry.
693 struct ehci_qh *intr_qh = (void*)(fl->links[0] & ~EHCI_PTR_BITS);
694 pipe->qh.next = intr_qh->next;
696 intr_qh->next = (u32)&pipe->qh | EHCI_PTR_QH;
698 int startpos = 1<<(frameexp-1);
699 pipe->qh.next = fl->links[startpos];
701 for (i=startpos; i<ARRAY_SIZE(fl->links); i+=ms)
702 fl->links[i] = (u32)&pipe->qh | EHCI_PTR_QH;
714 ehci_poll_intr(struct usb_pipe *p, void *data)
717 if (! CONFIG_USB_EHCI)
719 struct ehci_pipe *pipe = container_of(p, struct ehci_pipe, pipe);
720 struct ehci_qtd *td = GET_FLATPTR(pipe->next_td);
721 u32 token = GET_FLATPTR(td->token);
722 if (token & QTD_STS_ACTIVE)
725 // XXX - check for errors.
728 int maxpacket = GET_FLATPTR(pipe->pipe.maxpacket);
729 int pos = td - GET_FLATPTR(pipe->tds);
730 void *tddata = GET_FLATPTR(pipe->data) + maxpacket * pos;
731 memcpy_far(GET_SEG(SS), data
732 , FLATPTR_TO_SEG(tddata), (void*)FLATPTR_TO_OFFSET(tddata)
736 struct ehci_qtd *next = (void*)(GET_FLATPTR(td->qtd_next) & ~EHCI_PTR_BITS);
737 SET_FLATPTR(pipe->next_td, next);
738 SET_FLATPTR(td->buf[0], (u32)tddata);
740 SET_FLATPTR(td->token, (ehci_explen(maxpacket) | QTD_STS_ACTIVE
741 | QTD_PID_IN | ehci_maxerr(3)));