2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 --use work.gen_pkg.all;
7 -- type STATE_UART_TX is (IDLE, STARTBITS, PAYLOAD, PARITY, STOP, DONE);
8 -- type PARITY_TYPE is (ODD, EVEN, NONE);
9 --end package int_types;
13 sys_clk : in std_logic;
14 sys_res : in std_logic;
15 --txd : out std_logic;
16 --tx_data : in std_logic;
17 tx_new : in std_logic;
18 tx_done : out std_logic
22 architecture beh of uart_tx is
23 signal timer : integer range 0 to 65535;
24 signal timer_next : integer range 0 to 65535;
25 constant timer_max : integer := 35;
26 signal counter : integer;
27 signal counter_next : integer;
29 process (sys_clk, sys_res)
34 elsif rising_edge(sys_clk) then
35 counter <= counter_next;
41 process (timer, counter)
43 if (timer = timer_max) then
45 counter_next <= counter + 1;
47 timer_next <= timer + 1;
48 counter_next <= counter;