2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
8 sys_clk : in std_logic;
9 sys_res : in std_logic;
10 txd : in std_logic; -- warning: this is asynchronous input!
11 tx_data : out std_logic_vector(7 downto 0); -- map this to a larger register with containing input
12 tx_new : out std_logic
16 architecture beh of uart_rx is
17 constant timer_max : integer := 35;
19 type STATE_UART_RX is (IDLE, BUSY, DONE);
21 signal timer, timer_next : integer range 0 to 65535;
22 signal counter, counter_next : integer range 0 to 15;
23 signal state, state_next : STATE_UART_RX;
24 signal tx_data_prev : std_logic_vector(7 downto 0); -- FIXME: this isnt named next so that the interface isn't called tx_data_next ...
26 -- these are internal signals that are actually used as in and output
27 signal tx_data_i : std_logic_vector(7 downto 0);
28 signal tx_new_i : std_logic;
35 process(sys_clk, sys_res)
37 if (sys_res = '0') then
40 tx_data_prev <= X"00";
41 elsif rising_edge(sys_clk) then
44 tx_data_prev <= tx_data_i;
48 process(state, txd, counter)
59 if (counter = 9) then --FIXME: is this true?
75 -- Calculate the outputs
76 -- based on the current
87 -- END FIXME: do fill this out CORRECTLY
89 process (sys_clk, sys_res)
94 elsif rising_edge(sys_clk) then
95 counter <= counter_next;
102 if (timer = timer_max) then
105 timer_next <= timer + 1;
109 process (timer, counter, tx_new_i)
111 if (tx_new_i = '1') then
112 if (timer = timer_max) then
113 if (counter > 10) then
116 counter_next <= counter + 1;
119 counter_next <= counter;
126 process (counter, txd)
128 tx_data_i <= tx_data_prev;
129 -- TODO: we probably want oversampling and averaging + failure!
130 -- FIXME: this is per se not synthesisable
132 when 0 => --start bit
150 when 9 => -- stop bit
152 when others => -- idle
157 end architecture beh;