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3 -- Filename: console_sm_sync_beh.vhd
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6 -- Short Description:
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7 -- ==================
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8 -- Behavioral implementation of the synchronizer for the cosole mode
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9 -- finite state machine. It synchronizes all signal crossing
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10 -- from the system and the VGA clock domain and vice versa.
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15 use ieee.std_logic_1164.all;
16 use ieee.numeric_std.all;
17 use work.textmode_vga_pkg.all;
18 use work.textmode_vga_platform_dependent_pkg.all;
19 use work.font_pkg.all;
21 architecture beh of console_sm_sync is
22 type SYNC_STATE_TYPE is (STATE_IDLE, STATE_WAIT_ACK, STATE_FINISHED, STATE_WAIT_ACK_RELEASE);
23 signal sync_state, sync_state_next : SYNC_STATE_TYPE;
24 signal command_req_sync : std_logic_vector(0 to SYNC_STAGES - 1);
25 signal command_req_sys : std_logic;
26 signal ack_sync : std_logic_vector(0 to SYNC_STAGES - 1);
27 signal ack_sys : std_logic;
28 signal command_latched, command_latched_next : std_logic_vector(COMMAND_SIZE - 1 downto 0);
29 signal command_data_latched, command_data_latched_next : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE - 1 downto 0);
30 signal command_req_next : std_logic;
32 command_vga <= command_latched;
33 command_data_vga <= command_data_latched;
34 command_req_vga <= command_req_sync(SYNC_STAGES - 1);
35 synchronizer_sys_vga : process(vga_clk, vga_res_n)
37 if vga_res_n = '0' then
38 command_req_sync <= (others => '0');
39 elsif rising_edge(vga_clk) then
40 command_req_sync(0) <= command_req_sys;
41 for i in 1 to SYNC_STAGES - 1 loop
42 command_req_sync(i) <= command_req_sync(i - 1);
45 end process synchronizer_sys_vga;
47 ack_sys <= ack_sync(SYNC_STAGES - 1);
48 synchronizer_vga_sys : process(sys_clk, sys_res_n)
50 if sys_res_n = '0' then
51 ack_sync <= (others => '0');
52 elsif rising_edge(sys_clk) then
53 ack_sync(0) <= ack_vga;
54 for i in 1 to SYNC_STAGES - 1 loop
55 ack_sync(i) <= ack_sync(i - 1);
58 end process synchronizer_vga_sys;
60 process(sync_state, command_sys, ack_sys)
62 sync_state_next <= sync_state;
66 if command_sys /= COMMAND_NOP then
68 sync_state_next <= STATE_WAIT_ACK;
70 sync_state_next <= STATE_WAIT_ACK_RELEASE;
73 when STATE_WAIT_ACK =>
75 sync_state_next <= STATE_FINISHED;
77 when STATE_FINISHED =>
78 sync_state_next <= STATE_IDLE;
79 when STATE_WAIT_ACK_RELEASE =>
81 sync_state_next <= STATE_WAIT_ACK;
86 process(sync_state, command_latched, command_data_latched, command_sys, command_data_sys)
88 command_latched_next <= command_latched;
89 command_data_latched_next <= command_data_latched;
90 command_req_next <= '0';
95 command_latched_next <= command_sys;
96 command_data_latched_next <= command_data_sys;
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98 when STATE_WAIT_ACK =>
99 command_req_next <= '1';
100 when STATE_FINISHED =>
102 when STATE_WAIT_ACK_RELEASE =>
107 process(sys_clk, sys_res_n)
109 if sys_res_n = '0' then
110 command_latched <= COMMAND_NOP;
111 command_data_latched <= COLOR_BLACK & CHAR_NULL;
112 sync_state <= STATE_IDLE;
113 command_req_sys <= '0';
114 elsif rising_edge(sys_clk) then
115 command_latched <= command_latched_next;
116 command_data_latched <= command_data_latched_next;
117 sync_state <= sync_state_next;
118 command_req_sys <= command_req_next;
121 end architecture beh;