src/superio/winbond/w83627uhg/superio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2009 Dynon Avionics
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 $
  19  */
  20
  21 #include <arch/io.h>
  22 #include <device/device.h>
  23 #include <device/pnp.h>
  24 #include <console/console.h>
  25 #include <string.h>
  26 #include <stdint.h>
  27 #include <stdlib.h>
  28 #include <bitops.h>
  29 #include <uart8250.h>
  30 #include <pc80/keyboard.h>
  31 #include "chip.h"
  32 #include "w83627uhg.h"
  33
  34 static void w83627uhg_enter_ext_func_mode(device_t dev)
  35 {
  36         outb(0x87, dev->path.pnp.port);
  37         outb(0x87, dev->path.pnp.port);
  38 }
  39
  40 static void w83627uhg_exit_ext_func_mode(device_t dev)
  41 {
  42         outb(0xaa, dev->path.pnp.port);
  43 }
  44
  45 /*
  46  * Set the UART clock source.
  47  *
  48  * Possible UART clock source speeds are:
  49  *
  50  *   0 = 1.8462 MHz (default)
  51  *   1 = 2 MHz
  52  *   2 = 24 MHz
  53  *   3 = 14.769 MHz
  54  *
  55  * The faster clocks allow for BAUD rates up to 2mbits.
  56  *
  57  * Warning: The kernel will need to be adjusted since it assumes
  58  * a 1.8462 MHz clock.
  59  */
  60 static void set_uart_clock_source(device_t dev, u8 uart_clock)
  61 {
  62         u8 value;
  63
  64         w83627uhg_enter_ext_func_mode(dev);
  65         pnp_set_logical_device(dev);
  66         value = pnp_read_config(dev, 0xf0);
  67         value &= ~0x03;
  68         value |= (uart_clock & 0x03);
  69         pnp_write_config(dev, 0xf0, value);
  70         w83627uhg_exit_ext_func_mode(dev);
  71 }
  72
  73 static void w83627uhg_init(device_t dev)
  74 {
  75         struct superio_winbond_w83627uhg_config *conf = dev->chip_info;
  76
  77         if (!dev->enabled)
  78                 return;
  79
  80         switch(dev->path.pnp.device) {
  81         case W83627UHG_SP1:
  82                 /* set_uart_clock_source(dev, 0); */
  83                 break;
  84         case W83627UHG_SP2:
  85                 /* set_uart_clock_source(dev, 0); */
  86                 break;
  87         case W83627UHG_SP3:
  88                 /* set_uart_clock_source(dev, 0); */
  89                 break;
  90         case W83627UHG_SP4:
  91                 /* set_uart_clock_source(dev, 0); */
  92                 break;
  93         case W83627UHG_SP5:
  94                 /* set_uart_clock_source(dev, 0); */
  95                 break;
  96         case W83627UHG_SP6:
  97                 /* set_uart_clock_source(dev, 0); */
  98                 break;
  99         case W83627UHG_KBC:
 100                 pc_keyboard_init(&conf->keyboard);
 101                 break;
 102         }
 103 }
 104
 105 static void w83627uhg_set_resources(device_t dev)
 106 {
 107         w83627uhg_enter_ext_func_mode(dev);
 108         pnp_set_resources(dev);
 109         w83627uhg_exit_ext_func_mode(dev);
 110 }
 111
 112 static void w83627uhg_enable_resources(device_t dev)
 113 {
 114         w83627uhg_enter_ext_func_mode(dev);
 115         pnp_enable_resources(dev);
 116         w83627uhg_exit_ext_func_mode(dev);
 117 }
 118
 119 static void w83627uhg_enable(device_t dev)
 120 {
 121         w83627uhg_enter_ext_func_mode(dev);
 122         pnp_enable(dev);
 123         w83627uhg_exit_ext_func_mode(dev);
 124 }
 125
 126 static struct device_operations ops = {
 127         .read_resources   = pnp_read_resources,
 128         .set_resources    = w83627uhg_set_resources,
 129         .enable_resources = w83627uhg_enable_resources,
 130         .enable           = w83627uhg_enable,
 131         .init             = w83627uhg_init,
 132 };
 133
 134 static struct pnp_info pnp_dev_info[] = {
 135         { &ops, W83627UHG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
 136         { &ops, W83627UHG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
 137         { &ops, W83627UHG_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 138         { &ops, W83627UHG_SP2,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 139         { &ops, W83627UHG_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
 140         { &ops, W83627UHG_SP3,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 141         { &ops, W83627UHG_GPIO3_4, },
 142         { &ops, W83627UHG_WDTO_PLED_GPIO5_6, },
 143         { &ops, W83627UHG_GPIO1_2, },
 144         { &ops, W83627UHG_ACPI, PNP_IRQ0, },
 145         { &ops, W83627UHG_HWM,  PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
 146         { &ops, W83627UHG_PECI_SST, },
 147         { &ops, W83627UHG_SP4,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 148         { &ops, W83627UHG_SP5,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 149         { &ops, W83627UHG_SP6,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 150 };
 151
 152 static void enable_dev(device_t dev)
 153 {
 154         pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 155 }
 156
 157 struct chip_operations superio_winbond_w83627uhg_ops = {
 158         CHIP_NAME("Winbond W83627UHG Super I/O")
 159         .enable_dev = enable_dev,
 160 };