src/superio/winbond/w83627hf/superio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2000 AG Electronics Ltd.
   5  * Copyright (C) 2003-2004 Linux Networx
   6  * Copyright (C) 2004 Tyan
   7  * Copyright (C) 2010 Win Enterprises (anishp@win-ent.com)
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22  */
  23
  24 #include <arch/io.h>
  25 #include <device/device.h>
  26 #include <device/pnp.h>
  27 #include <console/console.h>
  28 #include <string.h>
  29 #include <bitops.h>
  30 #include <uart8250.h>
  31 #include <pc80/keyboard.h>
  32 #include <pc80/mc146818rtc.h>
  33 #include <stdlib.h>
  34 #include "chip.h"
  35 #include "w83627hf.h"
  36
  37 static void pnp_enter_ext_func_mode(device_t dev)
  38 {
  39         outb(0x87, dev->path.pnp.port);
  40         outb(0x87, dev->path.pnp.port);
  41 }
  42
  43 static void pnp_exit_ext_func_mode(device_t dev)
  44 {
  45         outb(0xaa, dev->path.pnp.port);
  46 }
  47
  48 static void pnp_write_index(u16 port, u8 reg, u8 value)
  49 {
  50         outb(reg, port);
  51         outb(value, port + 1);
  52 }
  53
  54 static u8 pnp_read_index(u16 port, u8 reg)
  55 {
  56         outb(reg, port);
  57         return inb(port + 1);
  58 }
  59
  60 static void enable_hwm_smbus(device_t dev)
  61 {
  62         u8 reg8;
  63
  64         /* Configure pins 91/92 as SDA/SCL (I2C bus). */
  65         reg8 = pnp_read_config(dev, 0x2b);
  66         reg8 &= 0x3f;
  67         pnp_write_config(dev, 0x2b, reg8);
  68 }
  69
  70 static void init_acpi(device_t dev)
  71 {
  72         u8 value = 0x20; /* FIXME: The 0x20 value here is never used? */
  73         int power_on = 1;
  74
  75         get_option(&power_on, "power_on_after_fail");
  76
  77         pnp_enter_ext_func_mode(dev);
  78         pnp_set_logical_device(dev);
  79         value = pnp_read_config(dev, 0xE4);
  80         value &= ~(3 << 5);
  81         if (power_on)
  82                 value |= (1 << 5);
  83         pnp_write_config(dev, 0xE4, value);
  84         pnp_exit_ext_func_mode(dev);
  85 }
  86
  87 static void init_hwm(u16 base)
  88 {
  89         u8 reg, value;
  90         int i;
  91
  92         u8 hwm_reg_values[] = {
  93         /*      reg   mask  data */
  94                 0x40, 0xff, 0x81, /* Start HWM. */
  95                 0x48, 0xaa, 0x2a, /* Set SMBus base to 0x2a (0x54 >> 1). */
  96                 0x4a, 0x21, 0x21, /* Set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1. */
  97                 0x4e, 0x80, 0x00,
  98                 0x43, 0x00, 0xff,
  99                 0x44, 0x00, 0x3f,
 100                 0x4c, 0xbf, 0x18,
 101                 0x4d, 0xff, 0x80, /* Turn off beep */
 102         };
 103
 104         for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) {
 105                 reg = hwm_reg_values[i];
 106                 value = pnp_read_index(base, reg);
 107                 value &= 0xff & hwm_reg_values[i + 1];
 108                 value |= 0xff & hwm_reg_values[i + 2];
 109                 printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, "
 110                        "value = 0x%02x\n", base, reg, value);
 111                 pnp_write_index(base, reg, value);
 112         }
 113 }
 114
 115 static void w83627hf_init(device_t dev)
 116 {
 117         struct superio_winbond_w83627hf_config *conf = dev->chip_info;
 118         struct resource *res0;
 119
 120         if (!dev->enabled)
 121                 return;
 122
 123         switch(dev->path.pnp.device) {
 124         case W83627HF_KBC:
 125                 pc_keyboard_init(&conf->keyboard);
 126                 break;
 127         case W83627HF_HWM:
 128                 res0 = find_resource(dev, PNP_IDX_IO0);
 129 #define HWM_INDEX_PORT 5
 130                 init_hwm(res0->base + HWM_INDEX_PORT);
 131                 break;
 132         case W83627HF_ACPI:
 133                 init_acpi(dev);
 134                 break;
 135         }
 136 }
 137
 138 static void w83627hf_pnp_set_resources(device_t dev)
 139 {
 140         pnp_enter_ext_func_mode(dev);
 141         pnp_set_resources(dev);
 142         pnp_exit_ext_func_mode(dev);
 143 }
 144
 145 static void w83627hf_pnp_enable_resources(device_t dev)
 146 {
 147         pnp_enter_ext_func_mode(dev);
 148         pnp_enable_resources(dev);
 149         switch(dev->path.pnp.device) {
 150         case W83627HF_HWM:
 151                 printk(BIOS_DEBUG, "W83627HF HWM SMBus enabled\n");
 152                 enable_hwm_smbus(dev);
 153                 break;
 154         }
 155         pnp_exit_ext_func_mode(dev);
 156 }
 157
 158 static void w83627hf_pnp_enable(device_t dev)
 159 {
 160         pnp_enter_ext_func_mode(dev);
 161         pnp_set_logical_device(dev);
 162         pnp_set_enable(dev, !!dev->enabled);
 163         pnp_exit_ext_func_mode(dev);
 164 }
 165
 166 static struct device_operations ops = {
 167         .read_resources   = pnp_read_resources,
 168         .set_resources    = w83627hf_pnp_set_resources,
 169         .enable_resources = w83627hf_pnp_enable_resources,
 170         .enable           = w83627hf_pnp_enable,
 171         .init             = w83627hf_init,
 172 };
 173
 174 static struct pnp_info pnp_dev_info[] = {
 175         { &ops, W83627HF_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
 176         { &ops, W83627HF_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
 177         { &ops, W83627HF_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 178         { &ops, W83627HF_SP2,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 179         { &ops, W83627HF_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
 180         { &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 181         { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, },
 182         { &ops, W83627HF_GPIO2, },
 183         { &ops, W83627HF_GPIO3, },
 184         { &ops, W83627HF_ACPI, },
 185         { &ops, W83627HF_HWM,  PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
 186 };
 187
 188 static void enable_dev(struct device *dev)
 189 {
 190         pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 191 }
 192
 193 struct chip_operations superio_winbond_w83627hf_ops = {
 194         CHIP_NAME("Winbond W83627HF Super I/O")
 195         .enable_dev = enable_dev,
 196 };