src/superio/winbond/w83627ehg/superio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2000 AG Electronics Ltd.
   5  * Copyright (C) 2003-2004 Linux Networx
   6  * Copyright (C) 2004 Tyan
   7  * Copyright (C) 2007 AMD
   8  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22  */
  23
  24 #include <arch/io.h>
  25 #include <device/device.h>
  26 #include <device/pnp.h>
  27 #include <console/console.h>
  28 #include <string.h>
  29 #include <bitops.h>
  30 #include <uart8250.h>
  31 #include <pc80/keyboard.h>
  32 #include <pc80/mc146818rtc.h>
  33 #include "chip.h"
  34 #include "w83627ehg.h"
  35
  36 static void pnp_enter_ext_func_mode(device_t dev)
  37 {
  38         outb(0x87, dev->path.u.pnp.port);
  39         outb(0x87, dev->path.u.pnp.port);
  40 }
  41
  42 static void pnp_exit_ext_func_mode(device_t dev)
  43 {
  44         outb(0xaa, dev->path.u.pnp.port);
  45 }
  46
  47 static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t value)
  48 {
  49         outb(reg, port_base);
  50         outb(value, port_base + 1);
  51 }
  52
  53 static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg)
  54 {
  55         outb(reg, port_base);
  56         return inb(port_base + 1);
  57 }
  58
  59 static void enable_hwm_smbus(device_t dev) {
  60         /* Set the pin 91,92 as I2C bus. */
  61         uint8_t reg, value;
  62         reg = 0x2a;
  63         value = pnp_read_config(dev, reg);
  64         value |= (1 << 1);
  65         pnp_write_config(dev, reg, value);
  66 }
  67
  68 static void init_acpi(device_t dev)
  69 {
  70         uint8_t value = 0x20;
  71         int power_on = 1;
  72
  73         get_option(&power_on, "power_on_after_fail");
  74         pnp_enter_ext_func_mode(dev);
  75         pnp_write_index(dev->path.u.pnp.port, 7, 0x0a);
  76         value = pnp_read_config(dev, 0xe4);
  77         value &= ~(3 << 5);
  78         if (power_on) {
  79                 value |= (1 << 5);
  80         }
  81         pnp_write_config(dev, 0xe4, value);
  82         pnp_exit_ext_func_mode(dev);
  83 }
  84
  85 static void init_hwm(unsigned long base)
  86 {
  87         int i;
  88         uint8_t reg, value;
  89
  90         /* reg mask data */
  91         unsigned hwm_reg_values[] = {
  92                 0x40, 0xff, 0x81, /* Start HWM. */
  93                 0x48, 0x7f, 0x2a, /* Set SMBus base to 0x54 >> 1. */
  94         };
  95
  96         for(i = 0; i < sizeof(hwm_reg_values)/sizeof(hwm_reg_values[0]); i += 3) {
  97                 reg = hwm_reg_values[i];
  98                 value = pnp_read_index(base, reg);
  99                 value &= 0xff & (~(hwm_reg_values[i + 1]));
 100                 value |= 0xff & hwm_reg_values[i + 2];
 101                 // printk_debug("base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value);
 102                 pnp_write_index(base, reg, value);
 103         }
 104 }
 105
 106 static void w83627ehg_init(device_t dev)
 107 {
 108         struct superio_winbond_w83627ehg_config *conf;
 109         struct resource *res0, *res1;
 110         if (!dev->enabled) {
 111                 return;
 112         }
 113         conf = dev->chip_info;
 114         switch(dev->path.u.pnp.device) {
 115         case W83627EHG_SP1:
 116                 res0 = find_resource(dev, PNP_IDX_IO0);
 117                 init_uart8250(res0->base, &conf->com1);
 118                 break;
 119         case W83627EHG_SP2:
 120                 res0 = find_resource(dev, PNP_IDX_IO0);
 121                 init_uart8250(res0->base, &conf->com2);
 122                 break;
 123         case W83627EHG_KBC:
 124                 res0 = find_resource(dev, PNP_IDX_IO0);
 125                 res1 = find_resource(dev, PNP_IDX_IO1);
 126                 init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
 127                 break;
 128         case W83627EHG_HWM:
 129                 res0 = find_resource(dev, PNP_IDX_IO0);
 130 #define HWM_INDEX_PORT 5
 131                 init_hwm(res0->base + HWM_INDEX_PORT);
 132                 break;
 133         case W83627EHG_ACPI:
 134                 init_acpi(dev);
 135                 break;
 136         }
 137 }
 138
 139 void w83627ehg_pnp_set_resources(device_t dev)
 140 {
 141         pnp_enter_ext_func_mode(dev);
 142         pnp_set_resources(dev);
 143         pnp_exit_ext_func_mode(dev);
 144 }
 145
 146 void w83627ehg_pnp_enable_resources(device_t dev)
 147 {
 148         pnp_enter_ext_func_mode(dev);
 149         pnp_enable_resources(dev);
 150
 151         switch (dev->path.u.pnp.device) {
 152         case W83627EHG_HWM:
 153                 printk_debug("w83627ehg hwm smbus enabled\n");
 154                 enable_hwm_smbus(dev);
 155                 break;
 156         }
 157
 158         pnp_exit_ext_func_mode(dev);
 159 }
 160
 161 void w83627ehg_pnp_enable(device_t dev)
 162 {
 163         if (!dev->enabled) {
 164                 pnp_enter_ext_func_mode(dev);
 165                 pnp_set_logical_device(dev);
 166                 pnp_set_enable(dev, 0);
 167                 pnp_exit_ext_func_mode(dev);
 168         }
 169 }
 170
 171 static struct device_operations ops = {
 172         .read_resources   = pnp_read_resources,
 173         .set_resources    = w83627ehg_pnp_set_resources,
 174         .enable_resources = w83627ehg_pnp_enable_resources,
 175         .enable           = w83627ehg_pnp_enable,
 176         .init             = w83627ehg_init,
 177 };
 178
 179 static struct pnp_info pnp_dev_info[] = {
 180         { &ops, W83627EHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
 181         { &ops, W83627EHG_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
 182         { &ops, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 183         { &ops, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 184         // No 4 { 0,},
 185         { &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
 186         { &ops, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 187         { &ops, W83627EHG_WDTO_PLED, },
 188         { &ops, W83627EHG_ACPI, },
 189         { &ops, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
 190         { &ops, W83627EHG_GAME, PNP_IO0, { 0x7ff, 0 }, },
 191         { &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 } , {0x7fe, 0x4}, },
 192         { &ops, W83627EHG_GPIO1, },
 193         { &ops, W83627EHG_GPIO2, },
 194         { &ops, W83627EHG_GPIO3, },
 195         { &ops, W83627EHG_GPIO4, },
 196         { &ops, W83627EHG_GPIO5, },
 197         { &ops, W83627EHG_GPIO6, },
 198 };
 199
 200 static void enable_dev(struct device *dev)
 201 {
 202         pnp_enable_devices(dev, &ops,
 203                 sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
 204 }
 205
 206 struct chip_operations superio_winbond_w83627ehg_ops = {
 207         CHIP_NAME("Winbond W83627EHG Super I/O")
 208         .enable_dev = enable_dev,
 209 };
 210