2 * This file is part of the coreboot project.
4 * Copyright (C) 2000 AG Electronics Ltd.
5 * Copyright (C) 2003-2004 Linux Networx
6 * Copyright (C) 2004 Tyan
7 * Copyright (C) 2005 Digital Design Corporation
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 /* RAM-based driver for SMSC LPC47N217 Super I/O chip. */
25 /* Based on coreboot code for SMSC 47B397. */
28 #include <device/device.h>
29 #include <device/pnp.h>
30 #include <console/console.h>
31 #include <device/smbus.h>
38 #include "lpc47n217.h"
40 // Forward declarations
41 static void enable_dev(device_t dev);
42 static void lpc47n217_pnp_set_resources(device_t dev);
43 static void lpc47n217_pnp_enable_resources(device_t dev);
44 static void lpc47n217_pnp_enable(device_t dev);
45 static void lpc47n217_init(device_t dev);
47 static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource);
48 static void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase);
49 static void lpc47n217_pnp_set_drq(device_t dev, unsigned drq);
50 static void lpc47n217_pnp_set_irq(device_t dev, unsigned irq);
51 static void lpc47n217_pnp_set_enable(device_t dev, int enable);
53 static void pnp_enter_conf_state(device_t dev);
54 static void pnp_exit_conf_state(device_t dev);
57 struct chip_operations superio_smsc_lpc47n217_ops = {
58 CHIP_NAME("SMSC LPC47N217 Super I/O")
59 .enable_dev = enable_dev,
62 static struct device_operations ops = {
63 .read_resources = pnp_read_resources,
64 .set_resources = lpc47n217_pnp_set_resources,
65 .enable_resources = lpc47n217_pnp_enable_resources,
66 .enable = lpc47n217_pnp_enable,
67 .init = lpc47n217_init,
70 static struct pnp_info pnp_dev_info[] = {
71 { &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
72 { &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
73 { &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }
76 /**********************************************************************************/
77 /* PUBLIC INTERFACE */
78 /**********************************************************************************/
80 //----------------------------------------------------------------------------------
81 // Function: enable_dev
82 // Parameters: dev - pointer to structure describing a Super I/O device
84 // Description: Create device structures and allocate resources to devices
85 // specified in the pnp_dev_info array (above).
87 static void enable_dev(device_t dev)
89 pnp_enable_devices(dev, &pnp_ops,
90 ARRAY_SIZE(pnp_dev_info),
94 //----------------------------------------------------------------------------------
95 // Function: lpc47n217_pnp_set_resources
96 // Parameters: dev - pointer to structure describing a Super I/O device
98 // Description: Configure the specified Super I/O device with the resources
99 // (I/O space, etc.) that have been allocate for it.
101 static void lpc47n217_pnp_set_resources(device_t dev)
105 pnp_enter_conf_state(dev);
107 // NOTE: Cannot use pnp_set_resources() here because it assumes chip
108 // support for logical devices, which the LPC47N217 doesn't have
109 for(i = 0; i < dev->resources; i++)
110 lpc47n217_pnp_set_resource(dev, &dev->resource[i]);
112 // dump_pnp_device(dev);
114 pnp_exit_conf_state(dev);
117 static void lpc47n217_pnp_enable_resources(device_t dev)
119 pnp_enter_conf_state(dev);
121 // NOTE: Cannot use pnp_enable_resources() here because it assumes chip
122 // support for logical devices, which the LPC47N217 doesn't have
123 lpc47n217_pnp_set_enable(dev, 1);
125 pnp_exit_conf_state(dev);
128 static void lpc47n217_pnp_enable(device_t dev)
130 pnp_enter_conf_state(dev);
132 // NOTE: Cannot use pnp_set_enable() here because it assumes chip
133 // support for logical devices, which the LPC47N217 doesn't have
136 lpc47n217_pnp_set_enable(dev, 1);
139 lpc47n217_pnp_set_enable(dev, 0);
142 pnp_exit_conf_state(dev);
145 //----------------------------------------------------------------------------------
146 // Function: lpc47n217_init
147 // Parameters: dev - pointer to structure describing a Super I/O device
148 // Return Value: None
149 // Description: Initialize the specified Super I/O device.
150 // Devices other than COM ports are ignored.
151 // For COM ports, we configure the baud rate.
153 static void lpc47n217_init(device_t dev)
155 struct superio_smsc_lpc47n217_config* conf = dev->chip_info;
156 struct resource *res0;
161 switch(dev->path.pnp.device) {
163 res0 = find_resource(dev, PNP_IDX_IO0);
164 init_uart8250(res0->base, &conf->com1);
168 res0 = find_resource(dev, PNP_IDX_IO0);
169 init_uart8250(res0->base, &conf->com2);
175 /**********************************************************************************/
176 /* PRIVATE FUNCTIONS */
177 /**********************************************************************************/
179 static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)
181 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
182 printk_err("ERROR: %s %02x not allocated\n",
183 dev_path(dev), resource->index);
187 /* Now store the resource */
188 // NOTE: Cannot use pnp_set_XXX() here because they assume chip
189 // support for logical devices, which the LPC47N217 doesn't have
191 if (resource->flags & IORESOURCE_IO) {
192 lpc47n217_pnp_set_iobase(dev, resource->base);
194 else if (resource->flags & IORESOURCE_DRQ) {
195 lpc47n217_pnp_set_drq(dev, resource->base);
197 else if (resource->flags & IORESOURCE_IRQ) {
198 lpc47n217_pnp_set_irq(dev, resource->base);
201 printk_err("ERROR: %s %02x unknown resource type\n",
202 dev_path(dev), resource->index);
205 resource->flags |= IORESOURCE_STORED;
207 report_resource_stored(dev, resource, "");
210 static void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
212 ASSERT(!(iobase & 0x3));
214 switch(dev->path.pnp.device) {
216 pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
220 pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
224 pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
233 static void lpc47n217_pnp_set_drq(device_t dev, unsigned drq)
235 if (dev->path.pnp.device == LPC47N217_PP) {
236 const uint8_t PP_DMA_MASK = 0x0F;
237 const uint8_t PP_DMA_SELECTION_REGISTER = 0x26;
238 uint8_t current_config = pnp_read_config(dev, PP_DMA_SELECTION_REGISTER);
241 ASSERT(!(drq & ~PP_DMA_MASK)); // DRQ out of range??
242 new_config = (current_config & ~PP_DMA_MASK) | drq;
243 pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
249 static void lpc47n217_pnp_set_irq(device_t dev, unsigned irq)
251 uint8_t irq_config_register = 0;
252 uint8_t irq_config_mask = 0;
253 uint8_t current_config;
256 switch(dev->path.pnp.device) {
258 irq_config_register = 0x27;
259 irq_config_mask = 0x0F;
263 irq_config_register = 0x28;
264 irq_config_mask = 0xF0;
269 irq_config_register = 0x28;
270 irq_config_mask = 0x0F;
278 ASSERT(!(irq & ~irq_config_mask)); // IRQ out of range??
280 current_config = pnp_read_config(dev, irq_config_register);
281 new_config = (current_config & ~irq_config_mask) | irq;
282 pnp_write_config(dev, irq_config_register, new_config);
285 static void lpc47n217_pnp_set_enable(device_t dev, int enable)
287 uint8_t power_register = 0;
288 uint8_t power_mask = 0;
289 uint8_t current_power;
292 switch(dev->path.pnp.device) {
294 power_register = 0x01;
299 power_register = 0x02;
304 power_register = 0x02;
313 current_power = pnp_read_config(dev, power_register);
314 new_power = current_power & ~power_mask; // disable by default
317 struct resource* ioport_resource = find_resource(dev, PNP_IDX_IO0);
318 lpc47n217_pnp_set_iobase(dev, ioport_resource->base);
320 new_power |= power_mask; // Enable
323 lpc47n217_pnp_set_iobase(dev, 0);
325 pnp_write_config(dev, power_register, new_power);
329 //----------------------------------------------------------------------------------
330 // Function: pnp_enter_conf_state
331 // Parameters: dev - pointer to structure describing a Super I/O device
332 // Return Value: None
333 // Description: Enable access to the LPC47N217's configuration registers.
335 static void pnp_enter_conf_state(device_t dev)
337 outb(0x55, dev->path.pnp.port);
340 //----------------------------------------------------------------------------------
341 // Function: pnp_exit_conf_state
342 // Parameters: dev - pointer to structure describing a Super I/O device
343 // Return Value: None
344 // Description: Disable access to the LPC47N217's configuration registers.
346 static void pnp_exit_conf_state(device_t dev)
348 outb(0xaa, dev->path.pnp.port);
352 //----------------------------------------------------------------------------------
353 // Function: dump_pnp_device
354 // Parameters: dev - pointer to structure describing a Super I/O device
355 // Return Value: None
356 // Description: Print the values of all of the LPC47N217's configuration registers.
357 // NOTE: The LPC47N217 must be in configuration mode when this
358 // function is called.
360 static void dump_pnp_device(device_t dev)
365 for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) {
366 uint8_t register_value;
368 if ((register_index & 0x0f) == 0) {
369 print_debug_hex8(register_index);
370 print_debug_char(':');
373 // Skip over 'register' that would cause exit from configuration mode
374 if (register_index == 0xaa)
375 register_value = 0xaa;
377 register_value = pnp_read_config(dev, register_index);
379 print_debug_char(' ');
380 print_debug_hex8(register_value);
381 if ((register_index & 0x0f) == 0x0f) {