src/superio/smsc/lpc47n217/superio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2000 AG Electronics Ltd.
   5  * Copyright (C) 2003-2004 Linux Networx
   6  * Copyright (C) 2004 Tyan
   7  * Copyright (C) 2005 Digital Design Corporation
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22  */
  23
  24 /* RAM-based driver for SMSC LPC47N217 Super I/O chip. */
  25
  26 #include <arch/io.h>
  27 #include <device/device.h>
  28 #include <device/pnp.h>
  29 #include <console/console.h>
  30 #include <device/smbus.h>
  31 #include <string.h>
  32 #include <bitops.h>
  33 #include <uart8250.h>
  34 #include <assert.h>
  35 #include <stdlib.h>
  36 #include "chip.h"
  37 #include "lpc47n217.h"
  38
  39 /* Forward declarations */
  40 static void enable_dev(device_t dev);
  41 static void lpc47n217_pnp_set_resources(device_t dev);
  42 static void lpc47n217_pnp_enable_resources(device_t dev);
  43 static void lpc47n217_pnp_enable(device_t dev);
  44 static void lpc47n217_init(device_t dev);
  45 static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource);
  46 static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase);
  47 static void lpc47n217_pnp_set_drq(device_t dev, u8 drq);
  48 static void lpc47n217_pnp_set_irq(device_t dev, u8 irq);
  49 static void lpc47n217_pnp_set_enable(device_t dev, int enable);
  50 static void pnp_enter_conf_state(device_t dev);
  51 static void pnp_exit_conf_state(device_t dev);
  52
  53 struct chip_operations superio_smsc_lpc47n217_ops = {
  54         CHIP_NAME("SMSC LPC47N217 Super I/O")
  55         .enable_dev = enable_dev,
  56 };
  57
  58 static struct device_operations ops = {
  59         .read_resources   = pnp_read_resources,
  60         .set_resources    = lpc47n217_pnp_set_resources,
  61         .enable_resources = lpc47n217_pnp_enable_resources,
  62         .enable           = lpc47n217_pnp_enable,
  63         .init             = lpc47n217_init,
  64 };
  65
  66 static struct pnp_info pnp_dev_info[] = {
  67         { &ops, LPC47N217_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
  68         { &ops, LPC47N217_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
  69         { &ops, LPC47N217_SP2,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }
  70 };
  71
  72 /**
  73  * Create device structures and allocate resources to devices specified in the
  74  * pnp_dev_info array (above).
  75  *
  76  * @param dev Pointer to structure describing a Super I/O device.
  77  */
  78 static void enable_dev(device_t dev)
  79 {
  80         pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info),
  81                            pnp_dev_info);
  82 }
  83
  84 /**
  85  * Configure the specified Super I/O device with the resources (I/O space,
  86  * etc.) that have been allocate for it.
  87  *
  88  * NOTE: Cannot use pnp_set_resources() here because it assumes chip
  89  * support for logical devices, which the LPC47N217 doesn't have.
  90  *
  91  * @param dev Pointer to structure describing a Super I/O device.
  92  */
  93 static void lpc47n217_pnp_set_resources(device_t dev)
  94 {
  95         struct resource *res;
  96
  97         pnp_enter_conf_state(dev);
  98         for (res = dev->resource_list; res; res = res->next)
  99                 lpc47n217_pnp_set_resource(dev, res);
 100         /* dump_pnp_device(dev); */
 101         pnp_exit_conf_state(dev);
 102 }
 103
 104 /*
 105  * NOTE: Cannot use pnp_enable_resources() here because it assumes chip
 106  * support for logical devices, which the LPC47N217 doesn't have.
 107  */
 108 static void lpc47n217_pnp_enable_resources(device_t dev)
 109 {
 110         pnp_enter_conf_state(dev);
 111         lpc47n217_pnp_set_enable(dev, 1);
 112         pnp_exit_conf_state(dev);
 113 }
 114
 115 /*
 116  * NOTE: Cannot use pnp_set_enable() here because it assumes chip
 117  * support for logical devices, which the LPC47N217 doesn't have.
 118  */
 119 static void lpc47n217_pnp_enable(device_t dev)
 120 {
 121         pnp_enter_conf_state(dev);
 122         lpc47n217_pnp_set_enable(dev, !!dev->enabled);
 123         pnp_exit_conf_state(dev);
 124 }
 125
 126 /**
 127  * Initialize the specified Super I/O device.
 128  *
 129  * Devices other than COM ports are ignored. For COM ports, we configure the
 130  * baud rate.
 131  *
 132  * @param dev Pointer to structure describing a Super I/O device.
 133  */
 134 static void lpc47n217_init(device_t dev)
 135 {
 136         struct superio_smsc_lpc47n217_config* conf = dev->chip_info;
 137
 138         if (!dev->enabled)
 139                 return;
 140 }
 141
 142 static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)
 143 {
 144         if (!(resource->flags & IORESOURCE_ASSIGNED)) {
 145                 printk(BIOS_ERR, "ERROR: %s %02x not allocated\n",
 146                        dev_path(dev), resource->index);
 147                 return;
 148         }
 149
 150         /* Now store the resource. */
 151
 152         /*
 153          * NOTE: Cannot use pnp_set_XXX() here because they assume chip
 154          * support for logical devices, which the LPC47N217 doesn't have.
 155          */
 156         if (resource->flags & IORESOURCE_IO) {
 157                 lpc47n217_pnp_set_iobase(dev, resource->base);
 158         } else if (resource->flags & IORESOURCE_DRQ) {
 159                 lpc47n217_pnp_set_drq(dev, resource->base);
 160         } else if (resource->flags & IORESOURCE_IRQ) {
 161                 lpc47n217_pnp_set_irq(dev, resource->base);
 162         } else {
 163                 printk(BIOS_ERR, "ERROR: %s %02x unknown resource type\n",
 164                        dev_path(dev), resource->index);
 165                 return;
 166         }
 167         resource->flags |= IORESOURCE_STORED;
 168
 169         report_resource_stored(dev, resource, "");
 170 }
 171
 172 static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase)
 173 {
 174         ASSERT(!(iobase & 0x3));
 175
 176         switch(dev->path.pnp.device) {
 177         case LPC47N217_PP:
 178                 pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
 179                 break;
 180         case LPC47N217_SP1:
 181                 pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
 182                 break;
 183         case LPC47N217_SP2:
 184                 pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
 185                 break;
 186         default:
 187                 BUG();
 188                 break;
 189         }
 190 }
 191
 192 static void lpc47n217_pnp_set_drq(device_t dev, u8 drq)
 193 {
 194         const u8 PP_DMA_MASK = 0x0F;
 195         const u8 PP_DMA_SELECTION_REGISTER = 0x26;
 196         u8 current_config, new_config;
 197
 198         if (dev->path.pnp.device == LPC47N217_PP) {
 199                 current_config = pnp_read_config(dev,
 200                                                  PP_DMA_SELECTION_REGISTER);
 201                 ASSERT(!(drq & ~PP_DMA_MASK)); /* DRQ out of range? */
 202                 new_config = (current_config & ~PP_DMA_MASK) | drq;
 203                 pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
 204         } else {
 205                 BUG();
 206         }
 207 }
 208
 209 static void lpc47n217_pnp_set_irq(device_t dev, u8 irq)
 210 {
 211         u8 irq_config_register = 0, irq_config_mask = 0;
 212         u8 current_config, new_config;
 213
 214         switch(dev->path.pnp.device) {
 215         case LPC47N217_PP:
 216                 irq_config_register = 0x27;
 217                 irq_config_mask = 0x0F;
 218                 break;
 219         case LPC47N217_SP1:
 220                 irq_config_register = 0x28;
 221                 irq_config_mask = 0xF0;
 222                 irq <<= 4;
 223                 break;
 224         case LPC47N217_SP2:
 225                 irq_config_register = 0x28;
 226                 irq_config_mask = 0x0F;
 227                 break;
 228         default:
 229                 BUG();
 230                 return;
 231         }
 232
 233         ASSERT(!(irq & ~irq_config_mask)); /* IRQ out of range? */
 234
 235         current_config = pnp_read_config(dev, irq_config_register);
 236         new_config = (current_config & ~irq_config_mask) | irq;
 237         pnp_write_config(dev, irq_config_register, new_config);
 238 }
 239
 240 static void lpc47n217_pnp_set_enable(device_t dev, int enable)
 241 {
 242         u8 power_register = 0, power_mask = 0, current_power, new_power;
 243
 244         switch(dev->path.pnp.device) {
 245         case LPC47N217_PP:
 246                 power_register = 0x01;
 247                 power_mask = 0x04;
 248                 break;
 249         case LPC47N217_SP1:
 250                 power_register = 0x02;
 251                 power_mask = 0x08;
 252                 break;
 253         case LPC47N217_SP2:
 254                 power_register = 0x02;
 255                 power_mask = 0x80;
 256                 break;
 257         default:
 258                 BUG();
 259                 return;
 260         }
 261
 262         current_power = pnp_read_config(dev, power_register);
 263         new_power = current_power & ~power_mask; /* Disable by default. */
 264         if (enable) {
 265                 struct resource* ioport_resource;
 266                 ioport_resource = find_resource(dev, PNP_IDX_IO0);
 267                 lpc47n217_pnp_set_iobase(dev, ioport_resource->base);
 268                 new_power |= power_mask; /* Enable. */
 269         } else {
 270                 lpc47n217_pnp_set_iobase(dev, 0);
 271         }
 272         pnp_write_config(dev, power_register, new_power);
 273 }
 274
 275 static void pnp_enter_conf_state(device_t dev)
 276 {
 277         outb(0x55, dev->path.pnp.port);
 278 }
 279
 280 static void pnp_exit_conf_state(device_t dev)
 281 {
 282         outb(0xaa, dev->path.pnp.port);
 283 }
 284
 285 #if 0
 286 /**
 287  * Print the values of all of the LPC47N217's configuration registers.
 288  *
 289  * NOTE: The LPC47N217 must be in config mode when this function is called.
 290  *
 291  * @param dev Pointer to structure describing a Super I/O device.
 292  */
 293 static void dump_pnp_device(device_t dev)
 294 {
 295         int i;
 296         print_debug("\n");
 297
 298         for (i = 0; i <= LPC47N217_MAX_CONFIG_REGISTER; i++) {
 299                 u8 register_value;
 300
 301                 if ((i & 0x0f) == 0) {
 302                         print_debug_hex8(i);
 303                         print_debug_char(':');
 304                 }
 305
 306                 /*
 307                  * Skip over 'register' that would cause exit from
 308                  * configuration mode.
 309                  */
 310                 if (i == 0xaa)
 311                         register_value = 0xaa;
 312                 else
 313                         register_value = pnp_read_config(dev, i);
 314
 315                 print_debug_char(' ');
 316                 print_debug_hex8(register_value);
 317                 if ((i & 0x0f) == 0x0f)
 318                         print_debug("\n");
 319         }
 320
 321         print_debug("\n");
 322 }
 323 #endif