2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 /* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */
22 #include <arch/romcc_io.h>
25 static inline void pnp_enter_conf_state(device_t dev)
27 unsigned port = dev>>8;
31 static void pnp_exit_conf_state(device_t dev)
33 unsigned port = dev>>8;
37 static inline void kbc1100_early_init(unsigned port)
40 dev = PNP_DEV (port, KBC1100_KBC);
42 pnp_enter_conf_state(dev);
44 /* Serial IRQ enabled */
48 /* Enable SMSC UART 0 */
49 dev = PNP_DEV (port, SMSCSUPERIO_SP1);
50 pnp_set_logical_device(dev);
51 pnp_set_enable(dev, 0);
52 pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
53 pnp_set_enable(dev, 1);
56 dev = PNP_DEV (port, KBC1100_KBC);
57 pnp_set_logical_device(dev);
58 pnp_set_enable(dev, 0);
59 pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
60 pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
61 pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */
62 pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */
63 pnp_set_enable(dev, 1);
65 /* Enable EC Channel 0 */
66 dev = PNP_DEV (port, KBC1100_EC0);
67 pnp_set_logical_device(dev);
68 pnp_set_enable(dev, 1);
70 pnp_exit_conf_state(dev);
72 /* disable the 1s timer */