2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
6 * Copyright (C) 2007 AMD
7 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <arch/romcc_io.h>
27 /* The base address is 0x2e or 0x4e, depending on config bytes. */
29 #define SIO_INDEX SIO_BASE
30 #define SIO_DATA SIO_BASE+1
32 /* Global configuration registers. */
33 #define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
34 #define IT8716F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
35 #define IT8716F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
36 #define IT8716F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
37 #define IT8716F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
39 #define IT8716F_CONFIGURATION_PORT 0x2e /* Write-only. */
41 /* Perform MB PnP setup to put the SIO chip at 0x2e. */
42 /* Base address 0x2e: 0x87 0x01 0x55 0x55. */
43 /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
44 static inline void pnp_enter_ext_func_mode(device_t dev)
46 unsigned port = dev >> 8;
57 static void pnp_exit_ext_func_mode(device_t dev)
59 pnp_write_config(dev, 0x02, 0x02);
62 void it8716f_enable_serial(device_t dev, unsigned iobase)
64 pnp_enter_ext_func_mode(dev);
65 pnp_set_logical_device(dev);
66 pnp_set_enable(dev, 0);
67 pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
68 pnp_set_enable(dev, 1);
69 pnp_exit_ext_func_mode(dev);