2 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 #include <arch/romcc_io.h>
22 /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
23 #define SIO_BASE 0x3f0
24 #define SIO_INDEX SIO_BASE
25 #define SIO_DATA SIO_BASE+1
27 /* Global Configuration Registers. */
28 #define IT8661F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
29 #define IT8661F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
30 #define IT8661F_CONFIG_REG_LDE 0x23 /* PnP Logical Device Enable. */
31 #define IT8661F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend + Clock Select. */
33 #define IT8661F_CONFIGURATION_PORT 0x0279 /* Write-only. */
35 /* Special values used for entering MB PnP mode. The first four bytes of
36 * each line determine the address port, the last four are data. */
37 static const uint8_t init_values[] = {
38 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
39 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
40 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
41 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
44 /* The content of IT8661F_CONFIG_REG_LDN (index 0x07) must be set to the
45 * LDN the register belongs to, before you can access the register. */
46 static void it8661f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
48 outb(IT8661F_CONFIG_REG_LDN, SIO_BASE);
50 outb(index, SIO_BASE);
51 outb(value, SIO_DATA);
54 /* Enable the peripheral devices on the IT8661F Super IO chip. */
55 static void it8661f_enable_serial(device_t dev, unsigned iobase)
59 /* (1) Enter the configuration state (MB PnP mode). */
61 /* Perform MB PnP setup to put the SIO chip at 0x3f0. */
62 /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
63 /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
64 /* Base address 0x370: 0x86 0x80 0xaa 0x55. */
65 outb(0x86, IT8661F_CONFIGURATION_PORT);
66 outb(0x80, IT8661F_CONFIGURATION_PORT);
67 outb(0x55, IT8661F_CONFIGURATION_PORT);
68 outb(0x55, IT8661F_CONFIGURATION_PORT);
70 /* Sequentially write the 32 special values. */
71 for (i = 0; i < 32; i++) {
72 outb(init_values[i], SIO_BASE);
75 /* (2) Modify the data of configuration registers. */
77 /* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2),
78 PP (3), IR (4). Bits 5-7 are reserved. */
79 it8661f_sio_write(0x00, IT8661F_CONFIG_REG_LDE, 0x1f);
81 /* Enable all devices. */
82 it8661f_sio_write(IT8661F_FDC, 0x30, 0x1); /* Floppy */
83 it8661f_sio_write(IT8661F_SP1, 0x30, 0x1); /* Serial port 1 */
84 it8661f_sio_write(IT8661F_SP2, 0x30, 0x1); /* Serial port 2 */
85 it8661f_sio_write(IT8661F_PP, 0x30, 0x1); /* Parallel port */
86 it8661f_sio_write(IT8661F_IR, 0x30, 0x1); /* IR */
88 /* Select 24MHz CLKIN (clear bit 1) and clear software suspend mode
90 it8661f_sio_write(0x00, IT8661F_CONFIG_REG_SWSUSP, 0x00);
92 /* (3) Exit the configuration state (MB PnP mode). */
93 it8661f_sio_write(0x00, IT8661F_CONFIG_REG_CC, 0x02);