src/southbridge/winbond/w83c553/w83c553f.c

   1 /*
   2  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   3  * Andreas Heppel <aheppel@sysgo.de>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Initialisation of the PCI-to-ISA bridge and disabling the BIOS
  26  * write protection (for flash) in function 0 of the chip.
  27  * Enabling function 1 (IDE controller of the chip.
  28  */
  29
  30 #include <arch/io.h>
  31 #include <device/pci.h>
  32 #include <console/console.h>
  33 #include "w83c553f.h"
  34
  35 #ifndef CONFIG_ISA_MEM
  36 #define CONFIG_ISA_MEM          0xFD000000
  37 #endif
  38 #ifndef CONFIG_ISA_IO
  39 #define CONFIG_ISA_IO           0xFE000000
  40 #endif
  41
  42 #ifndef CONFIG_IDE_MAXBUS
  43 #define CONFIG_IDE_MAXBUS       2
  44 #endif
  45 #ifndef CONFIG_IDE_MAXDEVICE
  46 #define CONFIG_IDE_MAXDEVICE    (CONFIG_IDE_MAXBUS*2)
  47 #endif
  48
  49 uint32_t ide_bus_offset[CONFIG_IDE_MAXBUS];
  50
  51 void initialise_pic(void);
  52 void initialise_dma(void);
  53
  54 extern struct pci_ops pci_direct_ppc;
  55
  56 #if 0
  57 void southbridge_early_init(void)
  58 {
  59         unsigned char reg8;
  60
  61         /*
  62          * Set ISA memory space
  63          */
  64         pci_direct_ppc.read_byte(0, 0x58, W83C553F_IPADCR, &reg8);
  65         /* 16 MB ISA memory space */
  66         reg8 |= (W83C553F_IPADCR_IPATOM4 | W83C553F_IPADCR_IPATOM5 | W83C553F_IPADCR_IPATOM6 | W83C553F_IPADCR_IPATOM7);
  67         reg8 &= ~W83C553F_IPADCR_MBE512;
  68         pci_direct_ppc.write_byte(0, 0x58, W83C553F_IPADCR, &reg8);
  69 }
  70 #endif
  71
  72 void southbridge_init(void)
  73 {
  74         struct device  *dev;
  75         unsigned char reg8;
  76         unsigned short reg16;
  77         unsigned int reg32;
  78
  79         dev = dev_find_device(W83C553F_VID, W83C553F_DID, 0);
  80         if (dev == 0)
  81         {
  82                 printk_info("Error: Cannot find W83C553F controller on any PCI bus\n");
  83                 return;
  84         }
  85
  86         printk_info("Found W83C553F controller\n");
  87
  88         /* always enabled */
  89 #if 0
  90         reg16 = pci_read_config16(dev, PCI_COMMAND);
  91         reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
  92         pci_write_config16(dev, PCI_COMMAND, reg16);
  93 #endif
  94
  95         /*
  96          * Set ISA memory space
  97          */
  98         reg8 = pci_read_config8(dev, W83C553F_IPADCR);
  99         /* 16 MB ISA memory space */
 100         reg8 |= (W83C553F_IPADCR_IPATOM4 | W83C553F_IPADCR_IPATOM5 | W83C553F_IPADCR_IPATOM6 | W83C553F_IPADCR_IPATOM7);
 101         reg8 &= ~W83C553F_IPADCR_MBE512;
 102         pci_write_config8(dev, W83C553F_IPADCR, reg8);
 103
 104         /*
 105          * Chip select: switch off BIOS write protection
 106          */
 107         reg8 = pci_read_config8(dev, W83C553F_CSCR);
 108         reg8 |= W83C553F_CSCR_UBIOSCSE;
 109         reg8 &= ~W83C553F_CSCR_BIOSWP;
 110         pci_write_config8(dev, W83C553F_CSCR, reg8);
 111
 112
 113         /*
 114          * Enable Port 92
 115          */
 116         reg8 = W83C553F_ATSCR_P92E | W83C553F_ATSCR_KRCEE;
 117         pci_write_config8(dev, W83C553F_CSCR, reg8);
 118
 119         /*
 120          * Route IDE interrupts to IRQ 14 & 15 on 8259.
 121          */
 122         pci_write_config8(dev, W83C553F_IDEIRCR, 0xef);
 123         pci_write_config16(dev, W83C553F_PCIIRCR, 0x0000);
 124
 125         /*
 126          * Read IDE bus offsets from function 1 device.
 127          * We must unmask the LSB indicating that it is an IO address.
 128          */
 129         dev = dev_find_device(W83C553F_VID, W83C553F_IDE, 0);
 130         if (dev == 0)
 131         {
 132                 printk_info("Error: Cannot find W83C553F function 1 device\n");
 133                 return;
 134         }
 135
 136         /*
 137          * Enable native mode on IDE ports and set base address.
 138          */
 139         reg8 = W83C553F_PIR_P1NL | W83C553F_PIR_P0NL;
 140         pci_write_config8(dev, W83C553F_PIR, reg8);
 141         pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0xffffffff);
 142         reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 143         pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0x1f0);
 144         reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 145         pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0xffffffff);
 146         reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
 147         pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x3f6);
 148         reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
 149         pci_write_config32(dev, PCI_BASE_ADDRESS_2, 0xffffffff);
 150         reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_2);
 151         pci_write_config32(dev, PCI_BASE_ADDRESS_2, 0x170);
 152         reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_2);
 153         pci_write_config32(dev, PCI_BASE_ADDRESS_3, 0xffffffff);
 154         reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_3);
 155         pci_write_config32(dev, PCI_BASE_ADDRESS_3, 0x376);
 156         reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_3);
 157
 158         /*
 159          * Set read-ahead duration to 0xff
 160          * Enable P0 and P1
 161          */
 162         reg32 = 0x00ff0000 | W83C553F_IDECSR_P1EN | W83C553F_IDECSR_P0EN;
 163         pci_write_config32(dev, W83C553F_IDECSR, reg32);
 164
 165         ide_bus_offset[0] = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 166         printk_debug("ide bus offset = 0x%x\n", ide_bus_offset[0]);
 167         ide_bus_offset[0] &= ~1;
 168 #if CONFIG_IDE_MAXBUS > 1
 169         ide_bus_offset[1] = pci_read_config32(dev, PCI_BASE_ADDRESS_2);
 170         ide_bus_offset[1] &= ~1;
 171 #endif
 172
 173         /*
 174          * Enable function 1, IDE -> busmastering and IO space access
 175          */
 176         reg16 = pci_read_config16(dev, PCI_COMMAND);
 177         reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
 178         pci_write_config16(dev, PCI_COMMAND, reg16);
 179         reg16 = pci_read_config16(dev, PCI_COMMAND);
 180
 181         /*
 182          * Initialise ISA interrupt controller
 183          */
 184         initialise_pic();
 185
 186         /*
 187          * Initialise DMA controller
 188          */
 189         initialise_dma();
 190
 191         printk_info("W83C553F configuration complete\n");
 192 }
 193
 194 void initialise_pic(void)
 195 {
 196         outb(W83C553F_PIC1_ICW1, 0x11); /* start init sequence, ICW4 needed */
 197         outb(W83C553F_PIC1_ICW2, 0x08); /* base address 00001 */
 198         outb(W83C553F_PIC1_ICW3, 0x04); /* slave on IRQ2 */
 199         outb(W83C553F_PIC1_ICW4, 0x01); /* x86 mode */
 200         outb(W83C553F_PIC1_OCW1, 0xfb); /* enable IRQ 2 */
 201         outb(W83C553F_PIC1_ELC, 0xf8);  /* all IRQ's edge sensitive */
 202
 203         outb(W83C553F_PIC2_ICW1, 0x11); /* start init sequence, ICW4 needed */
 204         outb(W83C553F_PIC2_ICW2, 0x08); /* base address 00001 */
 205         outb(W83C553F_PIC2_ICW3, 0x02); /* slave ID 2 */
 206         outb(W83C553F_PIC2_ICW4, 0x01); /* x86 mode */
 207         outb(W83C553F_PIC2_OCW1, 0xff); /* disable all IRQ's */
 208         outb(W83C553F_PIC2_ELC, 0xde);  /* all IRQ's edge sensitive */
 209
 210         outb(W83C553F_TMR1_CMOD, 0x74);
 211
 212         outb(W83C553F_PIC2_OCW1, 0x20);
 213         outb(W83C553F_PIC1_OCW1, 0x20);
 214
 215         outb(W83C553F_PIC2_OCW1, 0x2b);
 216         outb(W83C553F_PIC1_OCW1, 0x2b);
 217 }
 218
 219 void initialise_dma(void)
 220 {
 221         unsigned int channel;
 222         unsigned int rvalue1, rvalue2;
 223
 224         /* perform a H/W reset of the devices */
 225
 226         outb(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00);
 227         outw(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000);
 228
 229         /* initialise all channels to a sane state */
 230
 231         for (channel = 0; channel < 4; channel++) {
 232                 /*
 233                  * dependent upon the channel, setup the specifics:
 234                  *
 235                  * demand
 236                  * address-increment
 237                  * autoinitialize-disable
 238                  * verify-transfer
 239                  */
 240
 241                 switch (channel) {
 242                 case 0:
 243                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY);
 244                         rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL);
 245                         break;
 246                 case 1:
 247                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
 248                         rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
 249                         break;
 250                 case 2:
 251                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
 252                         rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
 253                         break;
 254                 case 3:
 255                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
 256                         rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
 257                         break;
 258                 default:
 259                         rvalue1 = 0x00;
 260                         rvalue2 = 0x00;
 261                         break;
 262                 }
 263
 264                 /* write to write mode registers */
 265
 266                 outb(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF);
 267                 outw(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF);
 268         }
 269
 270         /* enable all channels */
 271
 272         outb(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00);
 273         outw(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000);
 274         /*
 275          * initialize the global DMA configuration
 276          *
 277          * DACK# active low
 278          * DREQ active high
 279          * fixed priority
 280          * channel group enable
 281          */
 282
 283         outb(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00);
 284         outw(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000);
 285 }