src/southbridge/winbond/w83c553/w83c553f.c

   1 /*
   2  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   3  * Andreas Heppel <aheppel@sysgo.de>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Initialisation of the PCI-to-ISA bridge and disabling the BIOS
  26  * write protection (for flash) in function 0 of the chip.
  27  * Enabling function 1 (IDE controller of the chip.
  28  */
  29
  30 #include <arch/io.h>
  31 #include <device/pci.h>
  32 #include <device/chip.h>
  33 #include <console/console.h>
  34 #include "w83c553f.h"
  35 #include "chip.h"
  36
  37 #ifndef CONFIG_ISA_MEM
  38 #define CONFIG_ISA_MEM          0xFD000000
  39 #endif
  40 #ifndef CONFIG_ISA_IO
  41 #define CONFIG_ISA_IO           0xFE000000
  42 #endif
  43
  44 #ifndef CONFIG_IDE_MAXBUS
  45 #define CONFIG_IDE_MAXBUS       2
  46 #endif
  47 #ifndef CONFIG_IDE_MAXDEVICE
  48 #define CONFIG_IDE_MAXDEVICE    (CONFIG_IDE_MAXBUS*2)
  49 #endif
  50
  51 uint32_t ide_bus_offset[CONFIG_IDE_MAXBUS];
  52
  53 void initialise_pic(void);
  54 void initialise_dma(void);
  55
  56 extern struct pci_ops pci_direct_ppc;
  57
  58 #if 0
  59 void southbridge_early_init(void)
  60 {
  61         unsigned char reg8;
  62
  63         /*
  64          * Set ISA memory space
  65          */
  66         pci_direct_ppc.read_byte(0, 0x58, W83C553F_IPADCR, &reg8);
  67         /* 16 MB ISA memory space */
  68         reg8 |= (W83C553F_IPADCR_IPATOM4 | W83C553F_IPADCR_IPATOM5 | W83C553F_IPADCR_IPATOM6 | W83C553F_IPADCR_IPATOM7);
  69         reg8 &= ~W83C553F_IPADCR_MBE512;
  70         pci_direct_ppc.write_byte(0, 0x58, W83C553F_IPADCR, &reg8);
  71 }
  72 #endif
  73
  74 void w83c553_init(void)
  75 {
  76         struct device  *dev;
  77         unsigned char reg8;
  78         unsigned short reg16;
  79         unsigned int reg32;
  80
  81         dev = dev_find_device(W83C553F_VID, W83C553F_DID, 0);
  82         if (dev == 0)
  83         {
  84                 printk_info("Error: Cannot find W83C553F controller on any PCI bus\n");
  85                 return;
  86         }
  87
  88         printk_info("Found W83C553F controller\n");
  89
  90         /* always enabled */
  91 #if 0
  92         reg16 = pci_read_config16(dev, PCI_COMMAND);
  93         reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
  94         pci_write_config16(dev, PCI_COMMAND, reg16);
  95 #endif
  96
  97         /*
  98          * Set ISA memory space
  99          */
 100         reg8 = pci_read_config8(dev, W83C553F_IPADCR);
 101         /* 16 MB ISA memory space */
 102         reg8 |= (W83C553F_IPADCR_IPATOM4 | W83C553F_IPADCR_IPATOM5 | W83C553F_IPADCR_IPATOM6 | W83C553F_IPADCR_IPATOM7);
 103         reg8 &= ~W83C553F_IPADCR_MBE512;
 104         pci_write_config8(dev, W83C553F_IPADCR, reg8);
 105
 106         /*
 107          * Chip select: switch off BIOS write protection
 108          */
 109         reg8 = pci_read_config8(dev, W83C553F_CSCR);
 110         reg8 |= W83C553F_CSCR_UBIOSCSE;
 111         reg8 &= ~W83C553F_CSCR_BIOSWP;
 112         pci_write_config8(dev, W83C553F_CSCR, reg8);
 113
 114
 115         /*
 116          * Enable Port 92
 117          */
 118         reg8 = W83C553F_ATSCR_P92E | W83C553F_ATSCR_KRCEE;
 119         pci_write_config8(dev, W83C553F_CSCR, reg8);
 120
 121         /*
 122          * Route IDE interrupts to IRQ 14 & 15 on 8259.
 123          */
 124         pci_write_config8(dev, W83C553F_IDEIRCR, 0xef);
 125         pci_write_config16(dev, W83C553F_PCIIRCR, 0x0000);
 126
 127         /*
 128          * Read IDE bus offsets from function 1 device.
 129          * We must unmask the LSB indicating that it is an IO address.
 130          */
 131         dev = dev_find_device(W83C553F_VID, W83C553F_IDE, 0);
 132         if (dev == 0)
 133         {
 134                 printk_info("Error: Cannot find W83C553F function 1 device\n");
 135                 return;
 136         }
 137
 138         /*
 139          * Enable native mode on IDE ports and set base address.
 140          */
 141         reg8 = W83C553F_PIR_P1NL | W83C553F_PIR_P0NL;
 142         pci_write_config8(dev, W83C553F_PIR, reg8);
 143         pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0xffffffff);
 144         reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 145         pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0x1f0);
 146         reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 147         pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0xffffffff);
 148         reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
 149         pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x3f6);
 150         reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
 151         pci_write_config32(dev, PCI_BASE_ADDRESS_2, 0xffffffff);
 152         reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_2);
 153         pci_write_config32(dev, PCI_BASE_ADDRESS_2, 0x170);
 154         reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_2);
 155         pci_write_config32(dev, PCI_BASE_ADDRESS_3, 0xffffffff);
 156         reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_3);
 157         pci_write_config32(dev, PCI_BASE_ADDRESS_3, 0x376);
 158         reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_3);
 159
 160         /*
 161          * Set read-ahead duration to 0xff
 162          * Enable P0 and P1
 163          */
 164         reg32 = 0x00ff0000 | W83C553F_IDECSR_P1EN | W83C553F_IDECSR_P0EN;
 165         pci_write_config32(dev, W83C553F_IDECSR, reg32);
 166
 167         ide_bus_offset[0] = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 168         printk_debug("ide bus offset = 0x%x\n", ide_bus_offset[0]);
 169         ide_bus_offset[0] &= ~1;
 170 #if CONFIG_IDE_MAXBUS > 1
 171         ide_bus_offset[1] = pci_read_config32(dev, PCI_BASE_ADDRESS_2);
 172         ide_bus_offset[1] &= ~1;
 173 #endif
 174
 175         /*
 176          * Enable function 1, IDE -> busmastering and IO space access
 177          */
 178         reg16 = pci_read_config16(dev, PCI_COMMAND);
 179         reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
 180         pci_write_config16(dev, PCI_COMMAND, reg16);
 181         reg16 = pci_read_config16(dev, PCI_COMMAND);
 182
 183         /*
 184          * Initialise ISA interrupt controller
 185          */
 186         initialise_pic();
 187
 188         /*
 189          * Initialise DMA controller
 190          */
 191         initialise_dma();
 192
 193         printk_info("W83C553F configuration complete\n");
 194 }
 195
 196 void initialise_pic(void)
 197 {
 198         outb(W83C553F_PIC1_ICW1, 0x11); /* start init sequence, ICW4 needed */
 199         outb(W83C553F_PIC1_ICW2, 0x08); /* base address 00001 */
 200         outb(W83C553F_PIC1_ICW3, 0x04); /* slave on IRQ2 */
 201         outb(W83C553F_PIC1_ICW4, 0x01); /* x86 mode */
 202         outb(W83C553F_PIC1_OCW1, 0xfb); /* enable IRQ 2 */
 203         outb(W83C553F_PIC1_ELC, 0xf8);  /* all IRQ's edge sensitive */
 204
 205         outb(W83C553F_PIC2_ICW1, 0x11); /* start init sequence, ICW4 needed */
 206         outb(W83C553F_PIC2_ICW2, 0x08); /* base address 00001 */
 207         outb(W83C553F_PIC2_ICW3, 0x02); /* slave ID 2 */
 208         outb(W83C553F_PIC2_ICW4, 0x01); /* x86 mode */
 209         outb(W83C553F_PIC2_OCW1, 0xff); /* disable all IRQ's */
 210         outb(W83C553F_PIC2_ELC, 0xde);  /* all IRQ's edge sensitive */
 211
 212         outb(W83C553F_TMR1_CMOD, 0x74);
 213
 214         outb(W83C553F_PIC2_OCW1, 0x20);
 215         outb(W83C553F_PIC1_OCW1, 0x20);
 216
 217         outb(W83C553F_PIC2_OCW1, 0x2b);
 218         outb(W83C553F_PIC1_OCW1, 0x2b);
 219 }
 220
 221 void initialise_dma(void)
 222 {
 223         unsigned int channel;
 224         unsigned int rvalue1, rvalue2;
 225
 226         /* perform a H/W reset of the devices */
 227
 228         outb(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00);
 229         outw(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000);
 230
 231         /* initialise all channels to a sane state */
 232
 233         for (channel = 0; channel < 4; channel++) {
 234                 /*
 235                  * dependent upon the channel, setup the specifics:
 236                  *
 237                  * demand
 238                  * address-increment
 239                  * autoinitialize-disable
 240                  * verify-transfer
 241                  */
 242
 243                 switch (channel) {
 244                 case 0:
 245                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY);
 246                         rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL);
 247                         break;
 248                 case 1:
 249                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
 250                         rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
 251                         break;
 252                 case 2:
 253                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
 254                         rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
 255                         break;
 256                 case 3:
 257                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
 258                         rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
 259                         break;
 260                 default:
 261                         rvalue1 = 0x00;
 262                         rvalue2 = 0x00;
 263                         break;
 264                 }
 265
 266                 /* write to write mode registers */
 267
 268                 outb(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF);
 269                 outw(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF);
 270         }
 271
 272         /* enable all channels */
 273
 274         outb(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00);
 275         outw(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000);
 276         /*
 277          * initialize the global DMA configuration
 278          *
 279          * DACK# active low
 280          * DREQ active high
 281          * fixed priority
 282          * channel group enable
 283          */
 284
 285         outb(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00);
 286         outw(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000);
 287 }
 288
 289 void southbridge_init(struct chip *chip, enum chip_pass pass)
 290 {
 291
 292         struct southbridge_winbond_w83c553_config *conf = (struct southbridge_winbond_w83c553_config *)chip->chip_info;
 293
 294         switch (pass) {
 295         case CONF_PASS_POST_PCI:
 296                 w83c553_init();
 297                 break;
 298
 299         default:
 300                 /* nothing yet */
 301                 break;
 302         }
 303 }
 304
 305 struct chip_control southbridge_winbond_w83c553_control = {
 306         enable: southbridge_init,
 307         name:   "Winbond W83C553"
 308 };