src/southbridge/winbond/w83c553/w83c553f.c

   1 /*
   2  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   3  * Andreas Heppel <aheppel@sysgo.de>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Initialisation of the PCI-to-ISA bridge and disabling the BIOS
  26  * write protection (for flash) in function 0 of the chip.
  27  * Enabling function 1 (IDE controller of the chip.
  28  */
  29
  30 #ifndef CONFIG_ISA_IO
  31 #define CONFIG_ISA_IO         0xFE000000
  32 #endif
  33
  34 #include <arch/io.h>
  35 #include <device/pci.h>
  36 #include <device/pci_ids.h>
  37 #include <device/chip.h>
  38 #include <console/console.h>
  39 #include "w83c553f.h"
  40
  41 void initialise_pic(void);
  42 void initialise_dma(void);
  43
  44 static void
  45 w83c553_init(struct device *dev)
  46 {
  47         printk_info("Configure W83C553F ISA Bridge (Function 0)\n");
  48
  49 #if 0
  50         /*
  51          * Set ISA memory space NOT SURE ABOUT THIS???
  52          */
  53         reg8 = pci_read_config8(dev, W83C553F_IPADCR);
  54         /* 16 MB ISA memory space */
  55         reg8 |= (W83C553F_IPADCR_IPATOM4 | W83C553F_IPADCR_IPATOM5 | W83C553F_IPADCR_IPATOM6 | W83C553F_IPADCR_IPATOM7);
  56         reg8 &= ~W83C553F_IPADCR_MBE512;
  57         pci_write_config8(dev, W83C553F_IPADCR, reg8);
  58
  59         /*
  60          * Chip select: switch off BIOS write protection
  61          */
  62         reg8 = pci_read_config8(dev, W83C553F_CSCR);
  63         reg8 |= W83C553F_CSCR_UBIOSCSE;
  64         reg8 &= ~W83C553F_CSCR_BIOSWP;
  65         pci_write_config8(dev, W83C553F_CSCR, reg8);
  66
  67         /*
  68          * Enable Port 92
  69          */
  70         reg8 = W83C553F_ATSCR_P92E | W83C553F_ATSCR_KRCEE;
  71         pci_write_config8(dev, W83C553F_CSCR, reg8);
  72
  73         /*
  74          * Route IDE interrupts to IRQ 14 & 15 on 8259.
  75          */
  76         pci_write_config8(dev, W83C553F_IDEIRCR, 0x90);
  77         pci_write_config16(dev, W83C553F_PCIIRCR, 0xABEF);
  78
  79         /*
  80          * Initialise ISA interrupt controller
  81          */
  82         initialise_pic();
  83
  84         /*
  85          * Initialise DMA controller
  86          */
  87         initialise_dma();
  88 #endif
  89
  90         printk_info("W83C553F configuration complete\n");
  91 }
  92
  93 void initialise_pic(void)
  94 {
  95         outb(W83C553F_PIC1_ICW1, 0x11); /* start init sequence, ICW4 needed */
  96         outb(W83C553F_PIC1_ICW2, 0x08); /* base address 00001 */
  97         outb(W83C553F_PIC1_ICW3, 0x04); /* slave on IRQ2 */
  98         outb(W83C553F_PIC1_ICW4, 0x01); /* x86 mode */
  99         outb(W83C553F_PIC1_OCW1, 0xfb); /* enable IRQ 2 */
 100         outb(W83C553F_PIC1_ELC, 0xf8);  /* all IRQ's edge sensitive */
 101
 102         outb(W83C553F_PIC2_ICW1, 0x11); /* start init sequence, ICW4 needed */
 103         outb(W83C553F_PIC2_ICW2, 0x08); /* base address 00001 */
 104         outb(W83C553F_PIC2_ICW3, 0x02); /* slave ID 2 */
 105         outb(W83C553F_PIC2_ICW4, 0x01); /* x86 mode */
 106         outb(W83C553F_PIC2_OCW1, 0xff); /* disable all IRQ's */
 107         outb(W83C553F_PIC2_ELC, 0xde);  /* all IRQ's edge sensitive */
 108
 109         outb(W83C553F_TMR1_CMOD, 0x74);
 110
 111         outb(W83C553F_PIC2_OCW1, 0x20);
 112         outb(W83C553F_PIC1_OCW1, 0x20);
 113
 114         outb(W83C553F_PIC2_OCW1, 0x2b);
 115         outb(W83C553F_PIC1_OCW1, 0x2b);
 116 }
 117
 118 void initialise_dma(void)
 119 {
 120         unsigned int channel;
 121         unsigned int rvalue1, rvalue2;
 122
 123         /* perform a H/W reset of the devices */
 124
 125         outb(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00);
 126         outw(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000);
 127
 128         /* initialise all channels to a sane state */
 129
 130         for (channel = 0; channel < 4; channel++) {
 131                 /*
 132                  * dependent upon the channel, setup the specifics:
 133                  *
 134                  * demand
 135                  * address-increment
 136                  * autoinitialize-disable
 137                  * verify-transfer
 138                  */
 139
 140                 switch (channel) {
 141                 case 0:
 142                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY);
 143                         rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL);
 144                         break;
 145                 case 1:
 146                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
 147                         rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
 148                         break;
 149                 case 2:
 150                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
 151                         rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
 152                         break;
 153                 case 3:
 154                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
 155                         rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
 156                         break;
 157                 default:
 158                         rvalue1 = 0x00;
 159                         rvalue2 = 0x00;
 160                         break;
 161                 }
 162
 163                 /* write to write mode registers */
 164
 165                 outb(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF);
 166                 outw(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF);
 167         }
 168
 169         /* enable all channels */
 170
 171         outb(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00);
 172         outw(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000);
 173         /*
 174          * initialize the global DMA configuration
 175          *
 176          * DACK# active low
 177          * DREQ active high
 178          * fixed priority
 179          * channel group enable
 180          */
 181
 182         outb(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00);
 183         outw(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000);
 184 }
 185
 186 struct device_operations w83c553_ops  = {
 187         .read_resources   = pci_dev_read_resources,
 188         .set_resources    = pci_dev_set_resources,
 189         .enable_resources = pci_dev_enable_resources,
 190         .init             = w83c553_init,
 191         .scan_bus         = 0,
 192 };
 193
 194 struct pci_driver w83c553f_pci_driver __pci_driver = {
 195         /* w83c553f */
 196         .ops = &w83c553_ops,
 197         .device = PCI_DEVICE_ID_WINBOND_83C553,
 198         .vendor = PCI_VENDOR_ID_WINBOND,
 199 };