src/southbridge/winbond/w83c553/w83c553f.c

   1 /*
   2  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   3  * Andreas Heppel <aheppel@sysgo.de>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Initialisation of the PCI-to-ISA bridge and disabling the BIOS
  26  * write protection (for flash) in function 0 of the chip.
  27  * Enabling function 1 (IDE controller of the chip.
  28  */
  29
  30 #ifndef CONFIG_ISA_IO
  31 #define CONFIG_ISA_IO         0xFE000000
  32 #endif
  33
  34 #include <arch/io.h>
  35 #include <device/pci.h>
  36 #include <device/pci_ids.h>
  37 #include <console/console.h>
  38 #include "w83c553f.h"
  39
  40 void initialise_pic(void);
  41 void initialise_dma(void);
  42
  43 static void
  44 w83c553_init(struct device *dev)
  45 {
  46         printk_info("Configure W83C553F ISA Bridge (Function 0)\n");
  47
  48 #if 0
  49         /*
  50          * Set ISA memory space NOT SURE ABOUT THIS???
  51          */
  52         reg8 = pci_read_config8(dev, W83C553F_IPADCR);
  53         /* 16 MB ISA memory space */
  54         reg8 |= (W83C553F_IPADCR_IPATOM4 | W83C553F_IPADCR_IPATOM5 | W83C553F_IPADCR_IPATOM6 | W83C553F_IPADCR_IPATOM7);
  55         reg8 &= ~W83C553F_IPADCR_MBE512;
  56         pci_write_config8(dev, W83C553F_IPADCR, reg8);
  57
  58         /*
  59          * Chip select: switch off BIOS write protection
  60          */
  61         reg8 = pci_read_config8(dev, W83C553F_CSCR);
  62         reg8 |= W83C553F_CSCR_UBIOSCSE;
  63         reg8 &= ~W83C553F_CSCR_BIOSWP;
  64         pci_write_config8(dev, W83C553F_CSCR, reg8);
  65
  66         /*
  67          * Enable Port 92
  68          */
  69         reg8 = W83C553F_ATSCR_P92E | W83C553F_ATSCR_KRCEE;
  70         pci_write_config8(dev, W83C553F_CSCR, reg8);
  71
  72         /*
  73          * Route IDE interrupts to IRQ 14 & 15 on 8259.
  74          */
  75         pci_write_config8(dev, W83C553F_IDEIRCR, 0x90);
  76         pci_write_config16(dev, W83C553F_PCIIRCR, 0xABEF);
  77
  78         /*
  79          * Initialise ISA interrupt controller
  80          */
  81         initialise_pic();
  82
  83         /*
  84          * Initialise DMA controller
  85          */
  86         initialise_dma();
  87 #endif
  88
  89         printk_info("W83C553F configuration complete\n");
  90 }
  91
  92 void initialise_pic(void)
  93 {
  94         outb(W83C553F_PIC1_ICW1, 0x11); /* start init sequence, ICW4 needed */
  95         outb(W83C553F_PIC1_ICW2, 0x08); /* base address 00001 */
  96         outb(W83C553F_PIC1_ICW3, 0x04); /* slave on IRQ2 */
  97         outb(W83C553F_PIC1_ICW4, 0x01); /* x86 mode */
  98         outb(W83C553F_PIC1_OCW1, 0xfb); /* enable IRQ 2 */
  99         outb(W83C553F_PIC1_ELC, 0xf8);  /* all IRQ's edge sensitive */
 100
 101         outb(W83C553F_PIC2_ICW1, 0x11); /* start init sequence, ICW4 needed */
 102         outb(W83C553F_PIC2_ICW2, 0x08); /* base address 00001 */
 103         outb(W83C553F_PIC2_ICW3, 0x02); /* slave ID 2 */
 104         outb(W83C553F_PIC2_ICW4, 0x01); /* x86 mode */
 105         outb(W83C553F_PIC2_OCW1, 0xff); /* disable all IRQ's */
 106         outb(W83C553F_PIC2_ELC, 0xde);  /* all IRQ's edge sensitive */
 107
 108         outb(W83C553F_TMR1_CMOD, 0x74);
 109
 110         outb(W83C553F_PIC2_OCW1, 0x20);
 111         outb(W83C553F_PIC1_OCW1, 0x20);
 112
 113         outb(W83C553F_PIC2_OCW1, 0x2b);
 114         outb(W83C553F_PIC1_OCW1, 0x2b);
 115 }
 116
 117 void initialise_dma(void)
 118 {
 119         unsigned int channel;
 120         unsigned int rvalue1, rvalue2;
 121
 122         /* perform a H/W reset of the devices */
 123
 124         outb(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00);
 125         outw(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000);
 126
 127         /* initialise all channels to a sane state */
 128
 129         for (channel = 0; channel < 4; channel++) {
 130                 /*
 131                  * dependent upon the channel, setup the specifics:
 132                  *
 133                  * demand
 134                  * address-increment
 135                  * autoinitialize-disable
 136                  * verify-transfer
 137                  */
 138
 139                 switch (channel) {
 140                 case 0:
 141                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY);
 142                         rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL);
 143                         break;
 144                 case 1:
 145                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
 146                         rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
 147                         break;
 148                 case 2:
 149                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
 150                         rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
 151                         break;
 152                 case 3:
 153                         rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
 154                         rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
 155                         break;
 156                 default:
 157                         rvalue1 = 0x00;
 158                         rvalue2 = 0x00;
 159                         break;
 160                 }
 161
 162                 /* write to write mode registers */
 163
 164                 outb(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF);
 165                 outw(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF);
 166         }
 167
 168         /* enable all channels */
 169
 170         outb(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00);
 171         outw(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000);
 172         /*
 173          * initialize the global DMA configuration
 174          *
 175          * DACK# active low
 176          * DREQ active high
 177          * fixed priority
 178          * channel group enable
 179          */
 180
 181         outb(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00);
 182         outw(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000);
 183 }
 184
 185 struct device_operations w83c553_ops  = {
 186         .read_resources   = pci_dev_read_resources,
 187         .set_resources    = pci_dev_set_resources,
 188         .enable_resources = pci_dev_enable_resources,
 189         .init             = w83c553_init,
 190         .scan_bus         = 0,
 191 };
 192
 193 struct pci_driver w83c553f_pci_driver __pci_driver = {
 194         /* w83c553f */
 195         .ops = &w83c553_ops,
 196         .device = PCI_DEVICE_ID_WINBOND_83C553,
 197         .vendor = PCI_VENDOR_ID_WINBOND,
 198 };