2 * This file is part of the coreboot project.
4 * Copyright (C) 2006-2007 Uwe Hermann <uwe@hermann-uwe.de>
5 * Copyright (C) 2007 Corey Osgood <corey_osgood@verizon.net>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 /* This has been ported to the VIA VT82C686(A/B) from the SMSC FDC37M60x
23 * by Corey Osgood. See vt82c686.h for more information. */
25 #include <arch/romcc_io.h>
26 #include <device/pci_ids.h>
29 #define SIO_INDEX 0x3f0
30 #define SIO_DATA 0x3f1
33 * Configure the chip by writing the byte 'value' into the register
34 * specified by 'index'.
36 * @param index The index of the register to modify.
37 * @param value The value to write into the register.
39 static void vt82c686_sio_write(uint8_t index, uint8_t value)
41 outb(index, SIO_INDEX);
42 outb(value, SIO_DATA);
46 * Enable the serial port(s) of the VT82C686(A/B) Super I/O chip.
51 static void vt82c686_enable_serial(device_t dev, unsigned iobase)
56 /* TODO: Use info from 'dev' and 'iobase'. */
57 /* TODO: Only enable one serial port (depending on config) or both? */
59 /* (1) Enter configuration mode (set Function 0 Rx85[1] = 1). */
61 /* Find the southbridge. Die upon error. */
62 sbdev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
63 PCI_DEVICE_ID_VIA_82C686), 0);
64 // sbdev = PCI_DEV(0, 7, 0);
65 if (sbdev == PCI_DEV_INVALID) {
66 /* Serial output is not yet working at this point, but
67 * die() emits the POST code 0xff and halts the CPU, too. */
68 die("Southbridge not found.\n");
71 /* Enable Super-I/O (bit 0) and Super-I/O Configuration (bit 1). */
72 reg = pci_read_config8(sbdev, 0x85);
73 pci_write_config8(sbdev, 0x85, reg | 0x3); /* Set bits 0 and 1. */
75 /* (2) Configure the chip. */
77 /* Enable serial port 1 (set bit 2) and 2 (set bit 3). */
78 vt82c686_sio_write(VT82C686_FS, 0xf);
80 // vt82c686_sio_write(VT82C686_POWER, 0x00); /* No powerdown */
81 // vt82c686_sio_write(VT82C686_SP_CTRL, 0x00); /* Normal operation */
82 vt82c686_sio_write(VT82C686_SP1, 0xfe); /* SP1: 0x3f8 */
83 vt82c686_sio_write(VT82C686_SP2, 0xbe); /* SP2: 0x2f8 */
85 /* Enable high speed on serial port 1 (set bit 6) and 2 (set bit 7). */
86 vt82c686_sio_write(VT82C686_SP_CFG, 0xc0);
88 /* (3) Exit configuration mode (set Function 0 Rx85[1] = 0). */
89 reg = pci_read_config8(sbdev, 0x85);
90 pci_write_config8(sbdev, 0x85, reg & 0xfd); /* Clear bit 1. */