2 * This file is part of the coreboot project.
4 * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pci_ids.h>
25 #define SATA_MISC_CTRL 0x45
27 static void sata_i_init(struct device *dev)
31 printk(BIOS_DEBUG, "Configuring VIA SATA controller\n");
34 reg = pci_read_config8(dev, SATA_MISC_CTRL);
35 reg &= 0x7f; /* Sub Class Write Protect off */
36 pci_write_config8(dev, SATA_MISC_CTRL, reg);
38 /* Change the device class to SATA from RAID. */
39 pci_write_config8(dev, PCI_CLASS_DEVICE, 0x1);
40 reg |= 0x80; /* Sub Class Write Protect on */
41 pci_write_config8(dev, SATA_MISC_CTRL, reg);
46 static void sata_ii_init(struct device *dev)
53 * Analog black magic, you may or may not need to adjust 0x60-0x6f,
59 * CDR bandwidth [6:5] = 3
60 * Squelch Window Select [4:3] = 1
61 * CDR Charge Pump [2:0] = 1
64 pci_write_config8(dev, 0x64, 0x49);
66 /* Adjust driver current source value to 9. */
67 reg = pci_read_config8(dev, 0x65);
70 pci_write_config8(dev, 0x65, reg);
72 /* Set all manual termination 50ohm bits [2:0] and enable [4]. */
73 reg = pci_read_config8(dev, 0x6a);
75 pci_write_config8(dev, 0x6a, reg);
79 * CDR bandwidth [5:4] = 2
80 * Pre / De-emphasis Level [7:6] controls bits [3:2], rest in 0x6e
81 * CDR Charge Pump [2:0] = 1
84 reg = pci_read_config8(dev, 0x6f);
87 pci_write_config8(dev, 0x6f, reg);
89 /* Check if staggered spinup is supported. */
90 reg = pci_read_config8(dev, 0x83);
91 if ((reg & 0x8) == 0) {
92 /* Start OOB sequence on both drives. */
94 pci_write_config8(dev, 0x83, reg);
98 static const struct device_operations sata_i_ops = {
99 .read_resources = pci_dev_read_resources,
100 .set_resources = pci_dev_set_resources,
101 .enable_resources = pci_dev_enable_resources,
107 static const struct device_operations sata_ii_ops = {
108 .read_resources = pci_dev_read_resources,
109 .set_resources = pci_dev_set_resources,
110 .enable_resources = pci_dev_enable_resources,
111 .init = sata_ii_init,
116 static const struct pci_driver northbridge_driver_ii __pci_driver = {
118 .vendor = PCI_VENDOR_ID_VIA,
119 .device = PCI_DEVICE_ID_VIA_VT8237_SATA,
122 static const struct pci_driver northbridge_driver_i __pci_driver = {
124 .vendor = PCI_VENDOR_ID_VIA,
125 .device = PCI_DEVICE_ID_VIA_VT6420_SATA,