2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License v2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 /* Based on other VIA SB code. */
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pci_ops.h>
25 #include <device/pci_ids.h>
26 #include <console/console.h>
31 * No native mode. Interrupts from unconnected HDDs might occur if
32 * IRQ14/15 is used for PCI. Therefore no native mode support.
34 static void ide_init(struct device *dev)
36 struct southbridge_via_vt8237r_config *sb =
37 (struct southbridge_via_vt8237r_config *)dev->chip_info;
42 printk_info("%s IDE interface %s\n", "Primary",
43 sb->ide0_enable ? "enabled" : "disabled");
44 printk_info("%s IDE interface %s\n", "Secondary",
45 sb->ide1_enable ? "enabled" : "disabled");
46 enables = pci_read_config8(dev, IDE_CS) & ~0x3;
47 enables |= (sb->ide0_enable << 1) | sb->ide1_enable;
48 pci_write_config8(dev, IDE_CS, enables);
49 enables = pci_read_config8(dev, IDE_CS);
50 printk_debug("Enables in reg 0x40 read back as 0x%x\n", enables);
52 /* Enable only compatibility mode. */
53 enables = pci_read_config8(dev, IDE_CONF_II);
55 pci_write_config8(dev, IDE_CONF_II, enables);
56 enables = pci_read_config8(dev, IDE_CONF_II);
57 printk_debug("Enables in reg 0x42 read back as 0x%x\n", enables);
59 /* Enable prefetch buffers. */
60 enables = pci_read_config8(dev, IDE_CONF_I);
62 pci_write_config8(dev, IDE_CONF_I, enables);
64 /* Flush FIFOs at half. */
65 enables = pci_read_config8(dev, IDE_CONF_FIFO);
67 enables |= (1 << 2) | (1 << 0);
68 pci_write_config8(dev, IDE_CONF_FIFO, enables);
70 /* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */
71 enables = pci_read_config8(dev, IDE_MISC_I);
73 enables |= (1 << 4) | (1 << 3);
74 pci_write_config8(dev, IDE_MISC_I, enables);
76 /* Use memory read multiple, Memory-Write-and-Invalidate. */
77 enables = pci_read_config8(dev, IDE_MISC_II);
78 enables |= (1 << 2) | (1 << 3);
79 pci_write_config8(dev, IDE_MISC_II, enables);
81 /* Force interrupts to use compat mode. */
82 pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0);
83 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff);
86 cablesel = pci_read_config32(dev, IDE_UDMA);
87 cablesel &= ~((1 << 28) | (1 << 20) | (1 << 12) | (1 << 4));
88 cablesel |= (sb->ide0_80pin_cable << 28) |
89 (sb->ide0_80pin_cable << 20) |
90 (sb->ide1_80pin_cable << 12) |
91 (sb->ide1_80pin_cable << 4);
92 pci_write_config32(dev, IDE_UDMA, cablesel);
95 static const struct device_operations ide_ops = {
96 .read_resources = pci_dev_read_resources,
97 .set_resources = pci_dev_set_resources,
98 .enable_resources = pci_dev_enable_resources,
104 static const struct pci_driver northbridge_driver __pci_driver = {
106 .vendor = PCI_VENDOR_ID_VIA,
107 .device = PCI_DEVICE_ID_VIA_82C586_1,