2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 u16 osys; /* 0x00 - Operating System */
23 u8 smif; /* 0x02 - SMI function call ("TRAP") */
24 u8 prm0; /* 0x03 - SMI function call parameter */
25 u8 prm1; /* 0x04 - SMI function call parameter */
26 u8 scif; /* 0x05 - SCI function call (via _L00) */
27 u8 prm2; /* 0x06 - SCI function call parameter */
28 u8 prm3; /* 0x07 - SCI function call parameter */
29 u8 lckf; /* 0x08 - Global Lock function for EC */
30 u8 prm4; /* 0x09 - Lock function parameter */
31 u8 prm5; /* 0x0a - Lock function parameter */
32 u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
33 u8 lids; /* 0x0f - LID state (open = 1) */
34 u8 pwrs; /* 0x10 - Power state (AC = 1) */
35 u8 dbgs; /* 0x11 - Debug state */
36 u8 linx; /* 0x12 - Linux OS */
37 u8 dckn; /* 0x13 - PCIe docking state */
39 /* Processor Identification */
40 u8 apic; /* 0x28 - APIC enabled */
41 u8 mpen; /* 0x29 - MP capable/enabled */
42 u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
43 u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
44 u8 ppcm; /* 0x2c - Max. PPC state */
45 } __attribute__((packed)) global_nvs_t;