2 * This file is part of the coreboot project.
4 * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
5 * Copyright (C) 2009 Jon Harrison <bothlyn@blueyonder.co.uk>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 /* Inspiration from other VIA SB code. */
24 #include <console/console.h>
25 #include <device/device.h>
26 #include <device/pci.h>
27 #include <device/pci_ids.h>
28 #include <pc80/mc146818rtc.h>
29 #include <arch/ioapic.h>
30 #include <cpu/x86/lapic.h>
32 #include <pc80/keyboard.h>
33 #include <pc80/i8259.h>
35 #include <arch/acpi.h>
39 static void southbridge_init_common(struct device *dev);
41 #if CONFIG_EPIA_VT8237R_INIT
42 /* Interrupts for INT# A B C D */
43 static const unsigned char pciIrqs[4] = { 10, 11, 12, 0};
45 /* Interrupt Assignments for Pins 1 2 3 4 */
46 static const unsigned char sataPins[4] = { 'A','B','C','D'};
47 static const unsigned char vgaPins[4] = { 'A','B','C','D'};
48 static const unsigned char usbPins[4] = { 'A','B','C','D'};
49 static const unsigned char enetPins[4] = { 'A','B','C','D'};
50 static const unsigned char vt8237Pins[4] = { 'A','B','C','D'};
51 static const unsigned char slotPins[4] = { 'C','D','A','B'};
52 static const unsigned char riserPins[4] = { 'D','C','B','A'};
54 static unsigned char *pin_to_irq(const unsigned char *pin)
56 static unsigned char Irqs[4];
58 for (i = 0 ; i < 4 ; i++)
59 Irqs[i] = pciIrqs[ pin[i] - 'A' ];
65 /** Set up PCI IRQ routing, route everything through APIC. */
66 static void pci_routing_fixup(struct device *dev)
68 #if CONFIG_EPIA_VT8237R_INIT
72 /* PCI PNP Interrupt Routing INTE/F - disable */
73 pci_write_config8(dev, 0x44, 0x00);
75 /* PCI PNP Interrupt Routing INTG/H - disable */
76 pci_write_config8(dev, 0x45, 0x00);
78 /* Gate Interrupts until RAM Writes are flushed */
79 pci_write_config8(dev, 0x49, 0x20);
81 #if CONFIG_EPIA_VT8237R_INIT
83 /* Share INTE-INTH with INTA-INTD as per stock BIOS. */
84 pci_write_config8(dev, 0x46, 0x00);
86 /* setup PCI IRQ routing (For PCI Slot)*/
87 pci_write_config8(dev, 0x55, pciIrqs[0] << 4);
88 pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) );
89 pci_write_config8(dev, 0x57, pciIrqs[3] << 4);
91 /* PCI Routing Fixup */
94 pci_assign_irqs(0, 0x14, pin_to_irq(slotPins));
96 // Via 2 slot riser card 2nd slot
97 pci_assign_irqs(0, 0x13, pin_to_irq(riserPins));
100 pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
102 //Setup VT8237R Sound
103 pci_assign_irqs(0, 0x11, pin_to_irq(vt8237Pins));
106 pci_assign_irqs(0, 0x12, pin_to_irq(enetPins));
109 pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins));
111 /* APIC Routing Fixup */
114 pdev = dev_find_device(PCI_VENDOR_ID_VIA,
115 PCI_DEVICE_ID_VIA_VT6420_SATA, 0);
116 pci_write_config8(pdev, PCI_INTERRUPT_PIN, 0x02);
117 pci_assign_irqs(0, 0x0f, pin_to_irq(sataPins));
120 // Setup PATA Override
121 pdev = dev_find_device(PCI_VENDOR_ID_VIA,
122 PCI_DEVICE_ID_VIA_82C586_1, 0);
123 pci_write_config8(pdev, PCI_INTERRUPT_PIN, 0x01);
124 pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF);
127 /* Route INTE-INTH through registers above, no map to INTA-INTD. */
128 pci_write_config8(dev, 0x46, 0x10);
130 /* PCI Interrupt Polarity */
131 pci_write_config8(dev, 0x54, 0x00);
133 /* PCI INTA# Routing */
134 pci_write_config8(dev, 0x55, 0x00);
136 /* PCI INTB#/C# Routing */
137 pci_write_config8(dev, 0x56, 0x00);
139 /* PCI INTD# Routing */
140 pci_write_config8(dev, 0x57, 0x00);
147 * Set up the power management capabilities directly into ACPI mode.
148 * This avoids having to handle any System Management Interrupts (SMIs).
151 static void setup_pm(device_t dev)
154 /* Debounce LID and PWRBTN# Inputs for 16ms. */
155 pci_write_config8(dev, 0x80, 0x20);
157 /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
158 pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
160 /* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */
161 pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ);
163 #if CONFIG_EPIA_VT8237R_INIT
164 /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
165 pci_write_config16(dev, 0x84, 0x3052);
167 /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
168 pci_write_config16(dev, 0x84, 0x30b2);
171 /* SMI output level to low, 7.5us throttle clock */
172 pci_write_config8(dev, 0x8d, 0x18);
174 /* GP Timer Control 1s */
175 pci_write_config8(dev, 0x93, 0x88);
178 * 7 = SMBus clock from RTC 32.768KHz
179 * 5 = Internal PLL reset from susp disabled
182 pci_write_config8(dev, 0x94, 0xa0);
185 * 7 = stp to sust delay 1msec
186 * 6 = SUSST# Deasserted Before PWRGD for STD
187 * 5 = Keyboard/Mouse Swap
188 * 4 = PWRGOOD reset on VT8237A/S
189 * 3 = GPO26/GPO27 is GPO
190 * 2 = Disable Alert on Lan
195 #if CONFIG_EPIA_VT8237R_INIT
196 pci_write_config8(dev, 0x95, 0xc2);
198 pci_write_config8(dev, 0x95, 0xcc);
201 /* Disable GP3 timer. */
202 pci_write_config8(dev, 0x98, 0);
204 /* Enable ACPI accessm RTC signal gated with PSON. */
205 pci_write_config8(dev, 0x81, 0x84);
207 /* Clear status events. */
208 outw(0xffff, VT8237R_ACPI_IO_BASE + 0x00);
209 outw(0xffff, VT8237R_ACPI_IO_BASE + 0x20);
210 outw(0xffff, VT8237R_ACPI_IO_BASE + 0x28);
211 outl(0xffffffff, VT8237R_ACPI_IO_BASE + 0x30);
213 /* Disable SCI on GPIO. */
214 outw(0x0, VT8237R_ACPI_IO_BASE + 0x22);
216 /* Disable SMI on GPIO. */
217 outw(0x0, VT8237R_ACPI_IO_BASE + 0x24);
219 /* Disable all global enable SMIs, except SW SMI */
220 outw(0x40, VT8237R_ACPI_IO_BASE + 0x2a);
222 /* Primary activity SMI disable. */
223 outl(0x0, VT8237R_ACPI_IO_BASE + 0x34);
225 /* GP timer reload on none. */
226 outl(0x0, VT8237R_ACPI_IO_BASE + 0x38);
228 /* Disable extended IO traps. */
229 outb(0x0, VT8237R_ACPI_IO_BASE + 0x42);
231 /* SCI is generated for RTC/pwrBtn/slpBtn. */
232 tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
233 #if CONFIG_HAVE_ACPI_RESUME == 1
234 acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
235 printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
238 /* All SMI on, both IDE buses ON, PSON rising edge. */
239 outw(0x1, VT8237R_ACPI_IO_BASE + 0x2c);
244 outw(tmp, VT8237R_ACPI_IO_BASE + 0x04);
247 static void vt8237r_init(struct device *dev)
251 #if CONFIG_EPIA_VT8237R_INIT
252 printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n");
254 * TODO: Looks like stock BIOS can do this but causes a hang
255 * Enable SATA LED, disable special CPU Frequency Change -
256 * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
257 * Setup to match EPIA default
260 enables = pci_read_config8(dev, 0xe5);
262 pci_write_config8(dev, 0xe5, enables);
265 * Enable Flash Write Access.
266 * Note EPIA-N Does not use REQ5 or PCISTP#(Hang)
268 enables = pci_read_config8(dev, 0xe4);
270 pci_write_config8(dev, 0xe4, enables);
272 /* Enables Extra RTC Ports */
273 enables = pci_read_config8(dev, 0x4E);
275 pci_write_config8(dev, 0x4E, enables);
278 printk(BIOS_SPEW, "Entering vt8237r_init.\n");
280 * Enable SATA LED, disable special CPU Frequency Change -
281 * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
283 pci_write_config8(dev, 0xe5, 0x09);
285 /* REQ5 as PCI request input - should be together with INTE-INTH. */
286 pci_write_config8(dev, 0xe4, 0x4);
289 /* Set bit 3 of 0x4f (use INIT# as CPU reset). */
290 enables = pci_read_config8(dev, 0x4f);
292 pci_write_config8(dev, 0x4f, enables);
294 #if CONFIG_EPIA_VT8237R_INIT
296 * Set Read Pass Write Control Enable
298 pci_write_config8(dev, 0x48, 0x0c);
301 #if CONFIG_SOUTHBRIDGE_VIA_K8T800
302 /* It seems that when we pair with the K8T800, we need to disable
305 pci_write_config8(dev, 0x48, 0x0c);
308 * Set Read Pass Write Control Enable
309 * (force A2 from APIC FSB to low).
311 pci_write_config8(dev, 0x48, 0x8c);
316 southbridge_init_common(dev);
318 #if !CONFIG_EPIA_VT8237R_INIT
319 /* FIXME: Intel needs more bit set for C2/C3. */
322 * Allow SLP# signal to assert LDTSTOP_L.
323 * Will work for C3 and for FID/VID change.
325 outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
328 printk(BIOS_SPEW, "Leaving %s.\n", __func__);
329 printk(BIOS_SPEW, "And taking a dump:\n");
333 static void vt8237a_init(struct device *dev)
336 * FIXME: This is based on vt8237s_init() and the values the AMI
337 * BIOS on my M2V wrote to these registers (by loking
338 * at lspci -nxxx output).
343 /* Set bit 3 of 0x4f (use INIT# as CPU reset). */
344 tmp = pci_read_config8(dev, 0x4f);
346 pci_write_config8(dev, 0x4f, tmp);
349 * bit2: REQ5 as PCI request input - should be together with INTE-INTH.
350 * bit5: usb power control lines as gpio
352 pci_write_config8(dev, 0xe4, 0x24);
354 * Enable APIC wakeup from INTH
355 * Enable SATA LED, disable special CPU Frequency Change -
356 * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
358 pci_write_config8(dev, 0xe5, 0x69);
360 /* Reduce further the STPCLK/LDTSTP signal to 5us. */
361 pci_write_config8(dev, 0xec, 0x4);
363 /* Host Bus Power Management Control, maybe not needed */
364 pci_write_config8(dev, 0x8c, 0x5);
366 /* Enable HPET at VT8237R_HPET_ADDR. */
367 pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80));
369 southbridge_init_common(dev);
371 /* Share INTE-INTH with INTA-INTD for simplicity */
372 pci_write_config8(dev, 0x46, 0x00);
374 /* FIXME: Intel needs more bit set for C2/C3. */
377 * Allow SLP# signal to assert LDTSTOP_L.
378 * Will work for C3 and for FID/VID change.
380 outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
385 static void vt8237s_init(struct device *dev)
389 /* Put SPI base VT8237S_SPI_MEM_BASE. */
390 tmp = pci_read_config32(dev, 0xbc);
391 pci_write_config32(dev, 0xbc,
392 (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000));
395 * REQ5 as PCI request input - should be together with INTE-INTH.
397 pci_write_config8(dev, 0xe4, 0x04);
399 /* Reduce further the STPCLK/LDTSTP signal to 5us. */
400 pci_write_config8(dev, 0xec, 0x4);
402 /* Host Bus Power Management Control, maybe not needed */
403 pci_write_config8(dev, 0x8c, 0x5);
405 /* Enable HPET at VT8237R_HPET_ADDR., does not work correctly on R. */
406 pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80));
408 southbridge_init_common(dev);
410 /* FIXME: Intel needs more bit set for C2/C3. */
413 * Allow SLP# signal to assert LDTSTOP_L.
414 * Will work for C3 and for FID/VID change. FIXME FIXME, pre rev A2.
416 outb(0xff, VT8237R_ACPI_IO_BASE + 0x50);
421 static void vt8237_common_init(struct device *dev)
425 /* Enable addr/data stepping. */
426 byte = pci_read_config8(dev, PCI_COMMAND);
427 byte |= PCI_COMMAND_WAIT;
428 pci_write_config8(dev, PCI_COMMAND, byte);
430 /* EPIA-N(L) Uses CN400 for BIOS Access */
431 #if !CONFIG_EPIA_VT8237R_INIT
432 /* Enable the internal I/O decode. */
433 enables = pci_read_config8(dev, 0x6C);
435 pci_write_config8(dev, 0x6C, enables);
440 * 7 000E0000h-000EFFFFh
441 * 6 FFF00000h-FFF7FFFFh
442 * 5 FFE80000h-FFEFFFFFh
443 * 4 FFE00000h-FFE7FFFFh
444 * 3 FFD80000h-FFDFFFFFh
445 * 2 FFD00000h-FFD7FFFFh
446 * 1 FFC80000h-FFCFFFFFh
447 * 0 FFC00000h-FFC7FFFFh
448 * So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte.
450 pci_write_config8(dev, 0x41, 0x7f);
454 * Set bit 6 of 0x40 (I/O recovery time).
455 * IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so
456 * that PCI interrupts can be properly marked as level triggered.
458 enables = pci_read_config8(dev, 0x40);
460 pci_write_config8(dev, 0x40, enables);
462 /* Line buffer control */
463 enables = pci_read_config8(dev, 0x42);
465 pci_write_config8(dev, 0x42, enables);
467 /* Delay transaction control */
468 pci_write_config8(dev, 0x43, 0xb);
470 #if CONFIG_EPIA_VT8237R_INIT
471 /* I/O recovery time, default IDE routing */
472 pci_write_config8(dev, 0x4c, 0x04);
474 /* ROM memory cycles go to LPC. */
475 pci_write_config8(dev, 0x59, 0x80);
480 * 3 | Bypass APIC De-Assert Message (1=Enable)
481 * 2 | APIC HyperTransport Mode (1=Enable)
482 * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI"
483 * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
484 * 0 | Dynamic Clock Gating Main Switch (1=Enable)
486 pci_write_config8(dev, 0x5b, 0x9);
488 /* Set 0x58 to 0x42 APIC On and RTC Write Protect.*/
489 pci_write_config8(dev, 0x58, 0x42);
491 /* Enable serial IRQ, 6PCI clocks. */
492 pci_write_config8(dev, 0x52, 0x9);
494 /* I/O recovery time, default IDE routing */
495 pci_write_config8(dev, 0x4c, 0x44);
497 /* ROM memory cycles go to LPC. */
498 pci_write_config8(dev, 0x59, 0x80);
503 * 3 | Bypass APIC De-Assert Message (1=Enable)
504 * 2 | APIC HyperTransport Mode (1=Enable)
505 * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI"
506 * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
507 * 0 | Dynamic Clock Gating Main Switch (1=Enable)
509 pci_write_config8(dev, 0x5b, 0xb);
511 /* Set 0x58 to 0x43 APIC and RTC. */
512 pci_write_config8(dev, 0x58, 0x43);
514 /* Enable serial IRQ, 6PCI clocks. */
515 pci_write_config8(dev, 0x52, 0x9);
517 #if CONFIG_HAVE_SMI_HANDLER
521 /* Power management setup */
528 static void vt8237r_read_resources(device_t dev)
530 struct resource *res;
532 pci_dev_read_resources(dev);
534 /* Fixed ACPI Base IO Base*/
535 res = new_resource(dev, 0x88);
536 res->base = VT8237R_ACPI_IO_BASE;
538 res->limit = 0xffffUL;
539 res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
540 IORESOURCE_STORED | IORESOURCE_ASSIGNED;
542 /* Fixed EISA ECLR I/O Regs */
543 res = new_resource(dev, 3);
546 res->limit = 0xffffUL;
547 res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
548 IORESOURCE_STORED | IORESOURCE_ASSIGNED;
550 /* Fixed System Management Bus I/O Resource */
551 res = new_resource(dev, 0xD0);
552 res->base = VT8237R_SMBUS_IO_BASE;
554 res->limit = 0xffffUL;
555 res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
556 IORESOURCE_STORED | IORESOURCE_ASSIGNED;
558 /* Fixed APIC resource */
559 res = new_resource(dev, 0x44);
560 res->base = IO_APIC_ADDR;
562 res->limit = 0xffffffffUL;
565 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE |
566 IORESOURCE_STORED | IORESOURCE_ASSIGNED;
568 /* Fixed flashrom resource */
569 res = new_resource(dev, 4);
570 res->base = 0xff000000UL;
571 res->size = 0x01000000UL; /* 16MB */
572 res->limit = 0xffffffffUL;
573 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE |
574 IORESOURCE_STORED | IORESOURCE_ASSIGNED;
576 res = new_resource(dev, 1);
578 res->size = 0x1000UL;
579 res->limit = 0xffffUL;
580 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
583 static void init_keyboard(struct device *dev)
585 u8 regval = pci_read_config8(dev, 0x51);
590 static void southbridge_init_common(struct device *dev)
592 vt8237_common_init(dev);
593 pci_routing_fixup(dev);
594 setup_ioapic(IO_APIC_ADDR, VT8237R_APIC_ID);
599 static const struct device_operations vt8237r_lpc_ops_s = {
600 .read_resources = vt8237r_read_resources,
601 .set_resources = pci_dev_set_resources,
602 .enable_resources = pci_dev_enable_resources,
603 .init = vt8237s_init,
604 .scan_bus = scan_static_bus,
607 static const struct device_operations vt8237r_lpc_ops_r = {
608 .read_resources = vt8237r_read_resources,
609 .set_resources = pci_dev_set_resources,
610 .enable_resources = pci_dev_enable_resources,
611 .init = vt8237r_init,
612 .scan_bus = scan_static_bus,
615 static const struct device_operations vt8237r_lpc_ops_a = {
616 .read_resources = vt8237r_read_resources,
617 .set_resources = pci_dev_set_resources,
618 .enable_resources = pci_dev_enable_resources,
619 .init = vt8237a_init,
620 .scan_bus = scan_static_bus,
623 static const struct pci_driver lpc_driver_r __pci_driver = {
624 .ops = &vt8237r_lpc_ops_r,
625 .vendor = PCI_VENDOR_ID_VIA,
626 .device = PCI_DEVICE_ID_VIA_VT8237R_LPC,
629 static const struct pci_driver lpc_driver_a __pci_driver = {
630 .ops = &vt8237r_lpc_ops_a,
631 .vendor = PCI_VENDOR_ID_VIA,
632 .device = PCI_DEVICE_ID_VIA_VT8237A_LPC,
635 static const struct pci_driver lpc_driver_s __pci_driver = {
636 .ops = &vt8237r_lpc_ops_s,
637 .vendor = PCI_VENDOR_ID_VIA,
638 .device = PCI_DEVICE_ID_VIA_VT8237S_LPC,